JP2874198B2 - LCD drive circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a driving circuit of a liquid crystal display device.

[Conventional technology]

Conventionally, when driving a liquid crystal panel of a simple matrix or a liquid crystal panel using a two-terminal switching element such as a MIM, the drive stage is based on a voltage averaging method described in JP-B-57-57718. Generally, the driving circuit shown in FIG. 3 was used. Reference numeral 1 in FIG. 3 denotes a drive stage corresponding to the driver array unit of the signal electrode side (segment) drive circuit. V0 is the lighting potential on the high potential side (highest potential), V5 is the lighting potential on the low potential side (lowest potential), and V0 / V5
Constitutes a first potential having a large absolute value, V2 is a non-lighting potential on the high potential side, V3 is a non-lighting potential on the low potential side, and V2 ·
V3 forms a second potential having a small absolute value. PWM that pulse width modulated (hereinafter PWM) the video signal according to its luminance
The video signal _SU is converted into an alternating current by the liquid crystal alternating signal FR and the NOR gates 2 to 5, and is output from the drive output terminal 6 as a drive output waveform SEG obtained by combining the four potentials V0, V2, V3, and V5.

Japanese Patent Application Laid-Open No. 63-316896 discloses a drive circuit shown in FIG. In FIG. 4, those having the same numbers as those in FIG. 3 are circuits having equivalent functions, and those having the same symbols are equivalent signals or potentials. Transfer gate 7,8
Multiplexes the lighting potential V0 on the high potential side and the lighting potential V5 on the low potential side with the liquid crystal alternating signal FR as the gate input,
It outputs the lighting potential V _ON that has been converted to AC. The AC has been turned potential V _ON via a complementary transfer gate 9, 12 is controlled in PWM video signal S _U, also non-lighting voltage of the high potential side V2, the non-lighting voltage V3 on the low potential side A drive output terminal 6 via monolithic transfer gates 10 and 11 controlled by outputs of a NAND gate 3 and a NOR gate 4 which have the liquid crystal alternating signal FR and the PWM video signal _SU as gate inputs.
Output from

[Problems to be solved by the invention]

However, as the capacity of the liquid crystal panel has been increased, the liquid crystal drive circuit has been required to have more outputs. In the first example, when the liquid crystal drive circuit is formed into an integrated circuit (IC), a high breakdown voltage transistor is used. , The area of the drive stage 1 of the driver array unit is increased, and the increase in the number of outputs leads to an increase in the chip size, thereby deteriorating productivity.

In the second example, since the lighting potential V _ON is multiplexed by the transfer gates 7 and 8, the lighting potential V 0 on the high potential side or the lighting potential V 5 on the low potential side is output from the drive output terminal 6. Output resistance becomes higher. PWM video signal S _U to be inputted to the drive stage 1 of each driver array unit is not always random, depending video common impedance is generated by the output resistance, so that the image quality deterioration. That is, as shown in FIG. 5, for example, PWM video signal to drive stage one half of all the driver array unit S _U - type a, PWM video signal S _U in the other half - If you enter, respectively The drive output waveform becomes like SEG-, SEG-, and greatly deviates from the ideal value, thereby deteriorating the image quality.

Accordingly, an object of the present invention is to provide a liquid crystal drive circuit suitable for ICs having a small chip area and a small output resistance of a lighting potential in order to solve the above-mentioned problems of the conventional technology.

[Means for solving the problem]

In order to solve the problems of the prior art as described above, the liquid crystal driving circuit of the present invention is configured such that, based on a control signal, the magnitude relationship between the potentials is expressed by a first potential V0> second potential V2> third potential. In a liquid crystal drive circuit for selectively outputting a liquid crystal drive potential from a potential of potential V3> fourth potential V5, the second potential V2 and the third potential V3 are based on a liquid crystal alternating signal for controlling the liquid crystal to perform an AC drive. A complementary transfer gate that conducts when the control signal is at a first logic level and outputs the second or third potential selected by the selecting means; A first single-channel transfer gate for outputting a potential V0 of the first single-channel transfer gate; a second single-channel transfer gate for outputting the fourth potential V5; According to the activation signal A gate circuit for selectively controlling conduction of one of the first and second single-channel transfer gates; the complementary transfer gate, the first single-channel transfer gate, and the second single-channel transfer gate And an output terminal for receiving an output from the transfer gate and outputting the output as the liquid crystal drive potential.

Second, the control signal is a pulse width modulation signal, the first potential V0 and the fourth potential V5 are potentials for turning on a liquid crystal, and the second potential V2 and the The third potential V3 is a potential for turning off the liquid crystal.

[Action]

In the present invention, by the configuration described above, the non-lighting potential having a small absolute value is multiplexed by a transfer gate by a liquid crystal alternating signal and supplied to each drive circuit, and the lighting potential having a large absolute value is reduced. Supplied without multiplexing. In each drive circuit, the non-lighting potential is output from a complementary transfer gate controlled by a PWM signal, and the lighting potential is expressed by a first and a second gate to which the liquid crystal alternating signal and the PWM signal are input. Output from the first and second mono-channel transfer gates controlled by the output of the circuit.

Therefore, the liquid crystal drive circuit of the present invention obtains a lighting potential with a low output resistance from the drive output terminal.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a drive stage 1 of a driver array unit of a signal electrode side drive circuit according to the present invention so as to be easily compared with the conventional circuit shown in FIG. 3 and FIG. The circuits perform equivalent functions, and the same symbols indicate equivalent signals or potentials. 13 and 14 as a gate input the liquid crystal alternating signal FR by the transfer gate, the non-lighting voltage V3 unlit potential V2 and the low potential side of the high potential side and the multiplex output as non-lighting voltage V _OFF which is alternated I do. Reference numeral 16 denotes an inverter which receives the liquid crystal alternating signal FR and outputs an inverted signal ▲ ▼. The drive stage 1 of each driver array unit, that is, each drive circuit is configured as follows. 15 is an inverter, and inputs the PWM video signal S _U that PWM in accordance with video signals to the luminance, and outputs the inverted signal ▲ ▼. 2 is a NAND gate, which receives the liquid crystal alternating signal inversion signal ▲ ▼ and the PWM video signal _SU as a gate input and outputs an output S _NAND thereof,
Reference numeral 5 denotes a NOR gate, which receives the AC signal inverted signal ▼ and the PWM video signal inverted signal ▼ as gate inputs,
The output S _NOR is output. 10 and 11 in complementary transfer gate, the PWM video signal S _U and the PWM video signal inverted signal ▲ ▼ by a controlled its conduction, and outputs the non-lighting voltage V _OFF which is the AC to drive an output terminal 6 . 9 is a P-channel type transfer gate, said controlled its conduction by the NAND gate output S _NAND, and outputs the lighting voltage V0 on the high potential side to the driving output terminals 6, 12 in the transfer gate N-channel type, the NOR gate output S _NOR
, The conduction of which is controlled, and the lighting potential V5 on the low potential side is output to the drive output terminal 6. The drive output terminal 6 is
Each output of the complementary transfer gates 10 and 11, the P-channel transfer gate 9, and the N-channel transfer gate 12 is output as a drive output waveform SEG.

In the above configuration, the operation of the signal electrode side drive circuit according to the present invention will be described based on the timing chart shown in FIG. Here, PWM trailing edge shifting the PWM video signal S _U
And When the PWM video signal _SU is “L”, the inverted PWM video signal ▲ ▼ is “H”, the complementary transfer gates 10 and 11 are turned on, and the non-lighting potential V _OFF which is converted into AC is _{turned off.}
Are output to the drive output terminal 6. The non-lighting potential V _{OFF that} has been converted to the non-lighting potential V _OFF is such that when the liquid crystal alternating signal FR is “L”, the transfer gate 13 is turned on and becomes the non-lighting potential V2 on the high potential side, and the liquid crystal alternating signal FR becomes “H”. At the time of "", the transfer gate 14 is turned ON, and the non-lighting potential V3 on the low potential side is set. Further, when the PWM video signal _SU is “H”, the PWM video signal inversion signal “is“ L ”, and when the liquid crystal AC conversion signal FR is“ L ”, the liquid crystal AC conversion signal 信号 is Is “H”
Then, the NAND gate 2 outputs an active "L" to its output S _NAND , and when the liquid crystal alternating signal FR is "H", the liquid crystal alternating signal inversion signal ▲ ▼ becomes "L" and the NOR The gate 5 outputs active "H" to its output S _NOR .
P-channel type transfer gate 9, when the NAND gate output S _NAND are gate input becomes "L" turned ON, the driving output terminal the lighting voltage V0 on the high potential side 6
Output to The N-channel transfer gate 12
When the NOR gate output S _NOR that has been gate-inputted becomes “H”, the state is turned on, and the lighting potential V5 on the low potential side is output to the drive output terminal 6. In this way, drive output wave type SEG
Are generated from four liquid crystal driving potentials V0, V2, V3, and V5. That is, the output resistance of the lighting potentials V0 and V5 is only the ON resistance of the P-channel transfer gate 9 or the N-channel transfer gate 12, and there is basically no output resistance component that can be a common impedance.

Although the liquid crystal drive circuit of the present invention is particularly useful for a signal electrode side drive circuit, it goes without saying that the liquid crystal drive circuit can also be applied to a scan electrode side drive circuit.

〔The invention's effect〕

According to the present invention as described above, the following effects can be obtained.

1. When the lighting potentials V0 and V5 are output to the drive output waveform SEG, there is no transfer gate for alternating current as in the second conventional example on the line, so that no common impedance is generated basically. Spikes as shown in FIG. 5 do not occur on the drive output waveform SEG, and an ideal drive output waveform SEG is always obtained.

2. Since the non-lighting potentials V2 and V3 are multiplexed and the non-lighting potential V _OFF converted in advance is collectively supplied to the drive stage of each driver array unit, the second image can be obtained without deteriorating the image quality. The chip size of the IC can be reduced as in the conventional example. That is, in the drive stage of each driver array unit, it is possible to reduce the number of gates of high-voltage transistors 6, one wiring, and one power supply as compared with the first conventional example.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation of the embodiment.
3 and 4 are circuit diagrams showing a conventional example. FIG. 5 is a timing chart showing an abnormal drive output waveform. 1 Drive stage of driver array unit 2-5 Gate circuit 6 Drive output terminal 7-14 Transfer gate 15-17 Inverter V0 High potential side lighting potential V2 High potential side Lighting potential V3 ... Low-potential-side non-lighting potential V5 ... Low-potential-side lighting potential V _ON ... AC-converted lighting potential V _OFF ... AC-converted non-lighting potential FR ... LCD alternating-current signal S _U ... … PWM image signal ▲ ▼… LCD inverted signal inverted signal ▲ ▼… PWM image signal inverted signal S _NAND … Nand gate output S _NOR … Nor gate output SEG …… Drive output waveform

Claims (2)

(57) [Claims] 1. A method according to claim 1, wherein the magnitude relationship between the potentials is determined based on a control signal.
Potential V0> second potential V2> third potential V3> fourth potential V5
A liquid crystal drive circuit for selectively outputting a liquid crystal drive potential from a potential in the liquid crystal display device, a selecting means for multiplexing the second potential V2 and the third potential V3 based on a liquid crystal alternating signal for controlling the liquid crystal to perform an AC drive; A complementary transfer gate that conducts when the control signal is at a first logic level and outputs the second or third potential selected by the selection unit; and a first transfer gate that outputs the first potential V0. A single-channel transfer gate for outputting a fourth potential V5; a second single-channel transfer gate for outputting the fourth potential V5; and when the control signal is at a second logic level, A gate circuit for selectively controlling conduction of one of the first and second single-channel transfer gates; the complementary transfer gate and the first single-channel transfer gate; Liquid crystal drive circuit, characterized in that Fageto and receiving an output from the second single-channel transfer gate and an output terminal for outputting a liquid crystal drive voltage. 2. The control signal is a pulse width modulation signal,
The first potential V0 and the fourth potential V5 are potentials for turning on the liquid crystal, and the second potential V2 and the third potential V3 are potentials for turning off the liquid crystal. The liquid crystal drive circuit according to claim 1, wherein