JP2871295B2 - Surface type optical semiconductor device - Google Patents

Surface type optical semiconductor device

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Publication number
JP2871295B2
JP2871295B2 JP14016492A JP14016492A JP2871295B2 JP 2871295 B2 JP2871295 B2 JP 2871295B2 JP 14016492 A JP14016492 A JP 14016492A JP 14016492 A JP14016492 A JP 14016492A JP 2871295 B2 JP2871295 B2 JP 2871295B2
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JP
Japan
Prior art keywords
inp
layer
gaas
grown
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP14016492A
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Japanese (ja)
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JPH05308172A (en
Inventor
健一 笠原
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NEC Corp
Original Assignee
Nippon Electric Co Ltd
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Priority to JP14016492A priority Critical patent/JP2871295B2/en
Publication of JPH05308172A publication Critical patent/JPH05308172A/en
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Publication of JP2871295B2 publication Critical patent/JP2871295B2/en
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Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は機器間の光インターコネ
クションなどに使われる半導体面型光素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor optical device used for optical interconnection between devices.

【0002】[0002]

【従来の技術】面型光素子とは、半導体基板に対して垂
直な方向に光を出す素子であり、垂直共振器型の面発光
レーザ(VCSELD)や、半導体多層膜から成る分布
反射鏡(DBR)の間にpnpn構造を形成した垂直共
振器型面入出力光電融合素子(VC−VSTEP)など
を指す。面型光素子では基板に垂直な方向に光が取り出
せ、素子サイズ自体も小型にできるということから、面
型光素子の特徴は2次元集積化が可能になるという点に
ある。VCSELDやVC−VSTEPの材料系として
は主としてGaAs系が用いられているが、InP系で
のVCSELDも試作され始めている。
2. Description of the Related Art A surface optical device is a device that emits light in a direction perpendicular to a semiconductor substrate, and is a vertical cavity surface emitting laser (VCSELD) or a distributed reflector (multilayer semiconductor). DBR) and a vertical cavity surface input / output photoelectric fusion device (VC-VSTEP) having a pnpn structure formed between them. In the surface optical device, light can be extracted in a direction perpendicular to the substrate, and the device size itself can be reduced. Therefore, the feature of the surface optical device is that two-dimensional integration is possible. As a material system of VCSELD and VC-VSTEP, a GaAs system is mainly used, but an InP-based VCSELD has begun to be prototyped.

【0003】図3はInP系で作ったVCSELDの素
子構造を示してある。光スイッチング研究会(PST9
1−12,1991年)に報告されているものである。
材料系にInP系を用いると、光通信用光源として重要
な1μmの波長帯域がこれによってカバーできることに
なるので各所で関心が持たれている。
FIG. 3 shows an element structure of a VCSELD made of InP. Technical Committee on Optical Switching (PST9)
1-12, 1991).
If an InP-based material is used as a material system, a wavelength band of 1 μm, which is important as a light source for optical communication, can be covered by this, and is therefore of interest in various places.

【0004】図3において、31は基板のn−InP,
32はn−InGaAsP/InP−DBRで周期数は
30.5対である。33はn−InPでクラッド層、3
4はp−InGaAsPで活性層、35はp−InPで
クラッド層、36はp−InGaAsPでコンタクト
層、37はα−Si/SiO2 多層膜でp側の反射鏡と
して働く。38,39はそれぞれp電極、n電極であ
る。40,41はそれぞれp−InP,n−InPでこ
の部分に流れる電流を阻止する役目を果たす。
In FIG. 3, reference numeral 31 denotes n-InP,
Numeral 32 denotes an n-InGaAsP / InP-DBR whose number of periods is 30.5 pairs. 33 is an n-InP cladding layer, 3
4 is an active layer of p-InGaAsP, 35 is a cladding layer of p-InP, 36 is a contact layer of p-InGaAsP, and 37 is an α-Si / SiO 2 multilayer film which functions as a p-side reflector. 38 and 39 are a p electrode and an n electrode, respectively. Numerals 40 and 41 serve to block the current flowing in this portion with p-InP and n-InP, respectively.

【0005】[0005]

【発明が解決しようとする課題】従来のInP系面型光
素子の問題点は、99.9%といった高い反射率を有し
たDBRを作製するのが難しいという点にあった。そし
て、その理由はInP/InGaAsP系ではInPと
InGaAsPの間の屈折率差が小さいことにあった。
もちろんDBRの層数を増やせば反射率を上げることが
可能であるが、厚みも増えるので、成長に時間がかか
り、プロセスも段差がついて難しくなる。
A problem with the conventional InP-based surface optical device is that it is difficult to manufacture a DBR having a high reflectivity of 99.9%. The reason is that the refractive index difference between InP and InGaAsP is small in the InP / InGaAsP system.
Of course, the reflectivity can be increased by increasing the number of layers of the DBR. However, since the thickness is increased, the growth takes time and the process becomes difficult due to a step.

【0006】例えばGaAs系では15−20対で十分
な反射率が実現できるのに対して、InP系では40対
前後の半導体多層膜が必要となる。また1μm帯のIn
P系では0.8μm帯のGaAs系に比べて1層当りの
膜厚(λ/4波長)が厚くなるので、その分でも厚みが
余計いることになる。InP系VCSELDでは現状で
はGaAs系に比べて性能が良くなく、77Kでは連続
発振(閾値電流は6mA)が実現されているが、室温で
はパルス発振(閾値電流は150mA)にとどまってい
る。これはGaAs層や、GaAs層にInを少し添加
したInGaAs層を活性層に持つ短波系VCSELD
で1mA程度の閾値電流で室温連続発振が実現されてい
るにの比べると大幅に遅れていると言える。
For example, in the GaAs system, a sufficient reflectivity can be realized with 15-20 pairs, whereas in the InP system, about 40 pairs of semiconductor multilayer films are required. In addition, the 1 μm band In
The thickness of one layer (λ / 4 wavelength) in the P system is larger than that of the GaAs system in the 0.8 μm band, so that the thickness is excessive. At present, the performance of the InP-based VCSELD is not as good as that of the GaAs-based one, and continuous oscillation (threshold current is 6 mA) is realized at 77 K, but pulse oscillation (threshold current is 150 mA) at room temperature. This is a short-wavelength VCSELD having an active layer of a GaAs layer or an InGaAs layer in which a small amount of In is added to the GaAs layer.
Thus, it can be said that this is significantly delayed as compared with the case where room temperature continuous oscillation is realized with a threshold current of about 1 mA.

【0007】[0007]

【課題を解決するための手段】本発明はDBRの層数が
増大し、成長やプロセスが難しくなるといった従来の1
μm帯の面型光半導体素子の問題を解決しようとするも
のである。本発明になる面型光半導体素子は、GaAs
又はAlGaAs基板の上にAlx Ga1-x As(0<
x<1)とAly Ga1-y As(0<y<1)を交互に
積層した半導体分布反射鏡が成長され、その上にInP
バッファー層とInz Ga1-z Asw 1-w 活性層(0
<z,w<1)を含む中間層が成長され、さらにその上
に多層膜反射鏡が形成されている面型光半導体素子にお
いて、前記半導体分布反射鏡を成長した後、その上に誘
電体膜を形成し、一部を開口してそこに選択的に前記I
nPバッファー層と前記中間層を成長してあることを特
徴とする。
According to the present invention, there is provided a conventional one in which the number of layers of the DBR is increased and the growth and the process become difficult.
An object of the present invention is to solve the problem of the surface optical semiconductor device in the μm band. The surface type optical semiconductor device according to the present invention is made of GaAs.
Alternatively, Al x Ga 1 -x As (0 <
x <1) and Al y Ga 1-y As (0 <y <1) are alternately stacked, and a semiconductor distributed reflector is grown thereon.
The buffer layer and the In z Ga 1 -z Asw P 1 -w active layer (0
In the surface type optical semiconductor device in which the intermediate layer including <z, w <1) is grown and the multilayer mirror is formed thereon, after the semiconductor distributed reflector is grown, the dielectric material is grown thereon. A film is formed, a part of the film is opened, and the I
An nP buffer layer and the intermediate layer are grown.

【0008】[0008]

【作用】基板側のDBRをGaAs系で作製した構造と
するので1μm帯の波長に対して屈折率差を大きくとれ
る。それによってInP系でDBRを作製した時と比べ
て高反射率を得るのに必要な層数を減らすことができ
る。しかしながらAlx Ga1-x As/Aly Ga1-y
As−DBRの上にInP層を成長させることは一般的
に容易ではない。AlGaAs/GaAs系とInGa
AsP/InP系とでは格子不整合の問題があるので転
位が発生し、鏡面状の表面を得ることは難しいからであ
る。
Since the DBR on the substrate side is made of a GaAs-based structure, a large difference in the refractive index can be obtained for a wavelength in the 1 μm band. This makes it possible to reduce the number of layers required to obtain a high reflectivity as compared with the case where a DBR is manufactured using an InP system. However Al x Ga 1-x As / Al y Ga 1-y
It is generally not easy to grow an InP layer on an As-DBR. AlGaAs / GaAs system and InGa
This is because there is a problem of lattice mismatch with the AsP / InP system, dislocations are generated, and it is difficult to obtain a mirror-like surface.

【0009】本発明ではAlx Ga1-x As/Aly
1-y As−DBRを成長した後、その上に誘電体膜を
形成し、一部を開口してそこに選択的にInGaAsP
/InP系から成る中間層を成長する。このようにして
選択的に成長させると転位は初期的には発生するもの
の、選択成長層の側壁に達するとそこで止まる。そし
て、それ以上、上への進行が抑えられる。選択成長層の
側壁に達すると転位がそこで止まる理由は、歪が逃がせ
られるからである。
[0009] In the present invention Al x Ga 1-x As / Al y G
After growing a 1-y As-DBR, a dielectric film is formed thereon, a part of the film is opened, and InGaAsP is selectively formed therein.
A / InP-based intermediate layer is grown. When selectively grown in this way, dislocations are initially generated, but stop there when they reach the side wall of the selectively grown layer. Further, the upward progress is suppressed. The reason why the dislocation stops there when reaching the side wall of the selective growth layer is that strain can be released.

【0010】[0010]

【実施例】図1は本発明に関わる一実施例である。同図
において101はn−GaAs、102はλ/4厚のn
−AlAs(Siドープ、ドーピング濃度N=2x10
18cm-3)114、n−GaAs(Siドープ、N=2
x1018cm-3)113が交互に積層されて形成された
n型DBRである。λはInGaAs活性層106によ
る発振(波長1.5μm)に対応するAlAs(または
GaAs)内のの波長を表す。周期数は24.5であり
これで99.9%の反射率が実現できる。
FIG. 1 shows an embodiment according to the present invention. In the figure, 101 is n-GaAs, 102 is n of λ / 4 thickness.
-AlAs (Si doping, doping concentration N = 2 × 10
18 cm −3 ) 114, n-GaAs (Si-doped, N = 2)
x10 18 cm -3 ) 113 is an n-type DBR formed by alternately stacking. λ represents the wavelength in AlAs (or GaAs) corresponding to the oscillation (wavelength 1.5 μm) by the InGaAs active layer 106. The number of periods is 24.5, which can achieve a reflectivity of 99.9%.

【0011】103はn−InPバッファー層(N=2
x1018cm-3、層厚2.5μm)で、この部分は50
0℃で成長してある。成長にはMOCVD法を用いてい
るが、ここ以外は650℃で成長した。
Reference numeral 103 denotes an n-InP buffer layer (N = 2
x10 18 cm -3 , layer thickness 2.5 μm).
Growing at 0 ° C. Although the MOCVD method was used for the growth, the others were grown at 650 ° C.

【0012】n−InPバッファー層103の成長はn
型DBR102の上にSiO2 からなる誘電体膜120
の開口部121に選択的に成長させた。開口部121の
形状は円形でその直径は2.5μmである。また、誘電
体膜120は厚さ1000Aで熱CVD法で形成した。
The growth of the n-InP buffer layer 103 is n
Dielectric film 120 made of SiO 2 on DBR 102
The opening 121 was selectively grown. The opening 121 has a circular shape and a diameter of 2.5 μm. The dielectric film 120 was formed at a thickness of 1000 A by a thermal CVD method.

【0013】n−InPバッファー層103を500℃
と比較的低温で成長した理由を以下に説明する。InP
バッファー層を600〜700℃といった通常の温度で
GaAs系半導体の上に成長させると大きな島状にIn
Pの成長が進行してしまい表面が凹凸してしまう。それ
に対して550℃以下といった低温でInPバッファー
層を成長させると島の大きさが小さくなり、短時間に島
同志が一緒になって成長表面が平坦になってしまう。そ
して、この様なInPバッファー層を間に入れることに
よってInP系半導体を格子定数の異なるGaAs系半
導体の上に鏡面状に成長させることができる。
The n-InP buffer layer 103 is heated to 500 ° C.
The reason for growing at a relatively low temperature will be described below. InP
When a buffer layer is grown on a GaAs-based semiconductor at a normal temperature of 600 to 700 ° C., In
The growth of P proceeds and the surface becomes uneven. On the other hand, if the InP buffer layer is grown at a low temperature of 550 ° C. or less, the size of the islands becomes small, and the islands come together in a short time to flatten the growth surface. By interposing such an InP buffer layer, an InP-based semiconductor can be grown in a mirror-like manner on a GaAs-based semiconductor having a different lattice constant.

【0014】104はn−InP(Siドープ、N=2
x1018cm-3、層厚500A)である。InGaAs
活性層106の層厚は100Aで、アンドープである。
105,107はそれぞれn−InGaAsP,p−I
nGaAsPであり、両方とも層厚はδであり、ドーピ
ング濃度は2x1018cm-3(105はSiドープ、1
07はZnドープ)である。n−InGaAsP10
5,p−InGaAsP107は組成を放物線状に変化
させてあり、活性層106に接する側のバンドギャップ
波長は1.3μm、反対側のバンドギッップ波長はIn
Pと同じにしてある。108はn−InP(Znドー
プ、N=2x1018cm-3、層厚5000A)である。
109は厚さ1000Aのp−InGaAsP(バンド
ギャップ波長は1.3μm、Znドープ、N=2x10
18cm-3)であり、コンタクト層として働く。n−In
Pバッファー層103から一番上のp−InGaAsP
109までの層厚は7λ(λは発振波長、約1.5μm
のInGaAsP/InP系中間層内での波長)であ
る。
Reference numeral 104 denotes n-InP (Si-doped, N = 2
× 10 18 cm -3 , layer thickness 500A). InGaAs
The layer thickness of the active layer 106 is 100 A and is undoped.
105 and 107 are n-InGaAsP and p-I, respectively.
nGaAsP, both having a layer thickness of δ and a doping concentration of 2 × 10 18 cm −3 (105 is Si-doped, 1
07 is Zn-doped). n-InGaAsP10
5, the composition of p-InGaAsP 107 is parabolically changed, the band gap wavelength on the side in contact with the active layer 106 is 1.3 μm, and the band gap wavelength on the opposite side is In.
Same as P. Reference numeral 108 denotes n-InP (Zn-doped, N = 2 × 10 18 cm −3 , layer thickness 5000A).
Reference numeral 109 denotes p-InGaAsP having a thickness of 1000 A (bandgap wavelength is 1.3 μm, Zn-doped, N = 2 × 10
18 cm -3 ) and works as a contact layer. n-In
P-InGaAsP on the top of the P buffer layer 103
The layer thickness up to 109 is 7λ (λ is the oscillation wavelength, about 1.5 μm
(Wavelength in the InGaAsP / InP-based intermediate layer).

【0015】図2は図1のウェハーを用いて作製したメ
サ径が10μmのVCSELDの断面図である。111
5はp型DBRで、λ/4厚のα−Si116とSiO
2 117が3周期、繰り返して積層され形成されてい
る。110はCr/Au、111はn−GaAs113
の上に形成されたAuGe−Ni/Auであり、それぞ
れp型、n型の電極となる。光出力は基板側から得られ
る。発振閾値電流は約100μAであった。n型DBR
102の周期数は24.5で99.9%の反射率が実現
されているが、InP系で同じ反射率を得ようとすると
40周期は必要であるので、成長層厚を薄くできる。図
2では素子の全体の高さは5μm程度に抑えることがで
きた。
FIG. 2 is a sectional view of a VCSELD having a mesa diameter of 10 μm manufactured using the wafer of FIG. 111
Reference numeral 5 denotes a p-type DBR, which has a λ / 4 thickness of α-Si116 and SiO
2 117 are repeatedly formed in three cycles. 110 is Cr / Au, 111 is n-GaAs 113
AuGe-Ni / Au formed on the substrate, and serves as a p-type electrode and an n-type electrode, respectively. Light output is obtained from the substrate side. The oscillation threshold current was about 100 μA. n-type DBR
Although the number of periods of 102 is 24.5, a reflectivity of 99.9% is realized, but in order to obtain the same reflectivity in the InP system, 40 periods are required, so that the growth layer thickness can be reduced. In FIG. 2, the entire height of the element could be suppressed to about 5 μm.

【0016】[0016]

【発明の効果】本発明によればの光通信用光源として重
要な1μmの波長帯域でレーザ光が得られ、低閾値で動
作する面型光半導体素子が実現できる。本実施例ではV
CSELDについて説明したがVSTEPへの適用も可
能であることはもちろんである。
According to the present invention, laser light can be obtained in a wavelength band of 1 μm, which is important as a light source for optical communication, and a surface optical semiconductor device operating at a low threshold can be realized. In this embodiment, V
Although CSELD has been described, it goes without saying that application to VSTEP is also possible.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.

【図2】図1のウェハーを用いて作製した面発光レーザ
の断面図である。
FIG. 2 is a sectional view of a surface emitting laser manufactured using the wafer of FIG. 1;

【図3】従来の面発光レーザを示す斜視図である。FIG. 3 is a perspective view showing a conventional surface emitting laser.

【符号の説明】[Explanation of symbols]

101 n−GaAs 102 n型DBR 103 n−InPバッファー層 104,31,33,41 n−InP 105 n−InGaAsP 106 InGaAsP活性層 107,109,34,36 p−InGaAsP 108,35,40 p−InP 110 Cr/Au 111 AuGe−Ni/Au 112 SiN 113 n−GaAs 114 p−GaAs 116 α−Si 117 SiO2 115 p型DBR 32 n−InGaAsP/InP−DBR 37 α−Si/SiO2 多層膜 38 p電極 39 n電極 120 SiO2 誘電体膜 121 開口部101 n-GaAs 102 n-type DBR 103 n-InP buffer layer 104, 31, 33, 41 n-InP 105 n-InGaAsP 106 InGaAsP active layer 107, 109, 34, 36 p-InGaAsP 108, 35, 40 p-InP 110 Cr / Au 111 AuGe-Ni / Au 112 SiN 113 n-GaAs 114 p-GaAs 116 α-Si 117 SiO 2 115 p-type DBR 32 n-InGaAsP / InP-DBR 37 α-Si / SiO 2 multilayer film 38 p Electrode 39 n-electrode 120 SiO 2 dielectric film 121 opening

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 GaAs又はAlGaAs基板の上にA
x Ga1-x As(0<x<1)とAly Ga1-y As
(0<y<1)を交互に積層した半導体分布反射鏡が成
長され、その上にInPバッファー層とInz Ga1-z
Asw 1-w活性層(0<z,w<1)を含む中間層が
成長され、さらにその上に多層膜反射鏡が形成されてい
る面型光半導体素子において、前記半導体分布反射鏡を
成長した後、その上に誘電体膜を形成し、一部を開口し
てそこに選択的に前記InPバッファー層と前記中間層
を成長してあることを特徴とする面型光半導体素子。
1. A method in which A is placed on a GaAs or AlGaAs substrate.
l x Ga 1-x As ( 0 <x <1) and Al y Ga 1-y As
A semiconductor distributed reflector in which (0 <y <1) is alternately stacked is grown, and an InP buffer layer and In z Ga 1 -z are formed thereon.
In the surface type optical semiconductor device in which an intermediate layer including an As w P 1-w active layer (0 <z, w <1) is grown and a multilayer reflector is further formed thereon, the semiconductor distributed reflector A surface type optical semiconductor device, wherein a dielectric film is formed thereon, a part of the film is opened, and the InP buffer layer and the intermediate layer are selectively grown thereon.
JP14016492A 1992-04-30 1992-04-30 Surface type optical semiconductor device Expired - Fee Related JP2871295B2 (en)

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Application Number Priority Date Filing Date Title
JP14016492A JP2871295B2 (en) 1992-04-30 1992-04-30 Surface type optical semiconductor device

Publications (2)

Publication Number Publication Date
JPH05308172A JPH05308172A (en) 1993-11-19
JP2871295B2 true JP2871295B2 (en) 1999-03-17

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JP (1) JP2871295B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4497859B2 (en) * 2002-08-06 2010-07-07 株式会社リコー Surface emitting semiconductor laser device, optical transmission module, and optical transmission system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
1992年(平成4年)春季第39回応物学会予稿集 28a−SF−2 p.921

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Publication number Publication date
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