JP2871095B2 - Dual mode receiver with battery saving capability - Google Patents

Description

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to the field of communications receivers, and more particularly to a selective call communications receiver for high speed data and voice communications with battery saving capabilities.

2. Description of the Prior Art Many communication systems are currently in operation, including almost all paging systems today that utilize frequency (FM) modulation for addressing and transmission of data and voice. It is. Current communication receivers, including paging receivers, utilize advanced receiver architectures, and current paging systems utilize well-known established signaling formats. Current receiver architectures and signaling formats are optimized to provide higher receiver sensitivity and better battery savings.

In many urban areas, many paging systems were operating at or near maximum system capacity, both in terms of the number of subscribers available and available message transmission times .
As a result of such paging system operations, the hold time has increased, ie, the "camp-on" time required to access the paging system and the paging system's message transmission queue have similarly increased. , Delaying message delivery has hurt customer satisfaction. To improve message handling in such conventional systems, services such as voice paging have been abolished in many systems and replaced with newer services such as numeric and alphanumeric messages. These new services have significantly increased the number of subscribers that can be served by a paging system by significantly reducing the transmission time requirements for sending messages. But,
Improved paging, including improved methods for handling and processing large alphanumeric data messages
As demand for services increases, many paging systems are again approaching maximum system capacity. 1200 baud POCS to continuously improve the grade of service provided by such paging systems
New signaling formats, such as the AG signaling format, have been realized and have sought to reduce the burden on the paging system by further increasing message processing capacity.

When used in simulcast transmission systems, standard FM modulation is not suitable for high bit rate data transmission due to transmitter equalization issues. Due to the limitations of FM modulation for the transmission of high-speed messages, other forms of modulation, such as linear modulation techniques, are required for higher bit rate transmissions. Linear modulation techniques can be used for fast message transmission,
This modulation technique cannot be used with existing receiver architectures, is incompatible with current signaling techniques, and accepts and uses existing signaling protocols transmitted using standard FM modulation techniques. It requires more current drain to operate than the demodulation circuit requires. It is necessary to provide a receiver architecture that takes advantage of the battery saving capabilities of these existing paging signaling protocols by maintaining compatibility within existing FM modulated paging signaling protocols. Further, it provides a receiver architecture that performs linear demodulation with respect to voice and high-speed data capabilities, and increases the processing power of the messages required for these ever-expanding services without compromising the badge savings of existing paging signaling protocols. It is necessary.

SUMMARY OF THE INVENTION A first receiver for receiving and detecting information transmitted in a first modulation format, and receiving and detecting information transmitted in a second modulation format in response to information detected in the first modulation format. A dual mode communication receiver comprising a second receiver is described. The first and second receiving means share a common receiver front end.

In an alternative embodiment of the present invention, a first receiver receives and detects information transmitted in a first modulation format, and a second receiver receives and detects information transmitted in a second modulation format. A dual mode communication receiver configured is described. A power storage circuit is provided that supplies power to the first receiver to enable reception and detection of information transmitted in the first modulation format. The power storage circuit is further responsive to information received and detected in the first modulation format to power the second receiver to enable reception and detection of information transmitted in the second modulation format. . The first and second receiving means share a common receiver front end, respond to a battery saving protocol configured for information transmitted in the first modulation format, and are further addressed to a dual mode communication receiver. Also, in response to the information transmitted in the second modulation format, power is supplied to the front end from a power storage circuit.

BRIEF DESCRIPTION OF THE DRAWINGS The features of the invention which are believed to be novel are set forth with particularity in the appended claims. The invention itself, together with further objects and advantages thereof, will be better understood by reference to the following description and accompanying drawings. In some figures, the same reference numbers identify the same elements.

FIG. 1 is an electric block diagram of a dual mode communication receiver according to the present invention.

2A and 2B are timing diagrams illustrating a preferred signaling format of the dual mode communication receiver of the present invention.

FIG. 2C is a timing diagram illustrating the battery saving operation of the dual mode receiver of the present invention.

FIG. 2D is a timing diagram illustrating an alternative signaling format of the dual mode receiver of the present invention.

FIG. 3 is an enlarged electrical block diagram of the dual mode communication receiver of the present invention.

FIG. 4 is an electrical block diagram showing details of a battery saving function of the dual mode communication receiver of the present invention.

FIGS. 5A and 5B are flowcharts illustrating the operation of the dual mode communication receiver of the present invention.

Embodiments of the Invention As described above, conventional communication systems, such as paging systems, have transmitted addresses and messages using a predetermined signaling protocol using a single modulation format. Analog signaling protocols and analog voice messages, such as the two-tone and five-tone signaling protocols, can be used in either the phase or angle modulation format, or the direct frequency modulation format of FM modulation carrier systems currently in widespread use in the industry. Was modulated using Other signaling protocols, such as digital signaling protocols, use frequency shift keying (FSK) for both addressing and message transmission.
t keying) It was common to use a modulation format. 512 and 1200 bits per second POCSAG signaling protocol or 600 bits per second Golay S code
Existing signaling protocols, such as the equential Code) protocol, have been developed to provide better performance in wide area communication systems, such as systems that transmit simulcast messages. However, as described above, there is a limit to transmitting information at a high data bit rate using the FM modulation format. This limitation is often due to problems in equalizing simulcast transmission systems for such transmissions, and the frequency required to perform such high-speed data communications using conventional frequency modulation formats. It depends on the spectrum.

Other modulation formats for improving the processing capability of the message information are also available. These alternative modulation formats include a modulation format often referred to as a linear modulation format. These linear modulation formats allow modulation of the carrier signal,
Thereby, the message information is encoded in both the carrier amplitude and the instantaneous phase angle. Examples of linear modulation formats include quadrature amplitude modulation (QAM).
U.S. Patent No. 4,737,969 to Steel et al., "Spectrally Efficient Digital Modula," assigned to the assignee of the present invention and incorporated herein by reference.
Spectral Efficient Data Modulation (SEDM Modulation: spectrally efficient data)
modulation). Other forms of linear modulation include a modulation format that modulates both the amplitude and phase of a transmitted signal to encode message information, shapes the transmitted spectrum, and protects adjacent channels. One example of such a modulation format is a QPSK signaling format. Although such linear modulation formats can be used for transmitting message information at much higher data rates than with conventional frequency modulation formats, these linear modulation formats are generally superior. It cannot be used with already established paging signaling protocols that have been developed to obtain both receiver sensitivity and battery saving performance. These are incompatible mainly because of POCSAG
Or provide a linear receiver that requires much more power to operate than is required by a selective call receiver that operates in a paging system that employs well-known signaling formats such as the Golay sequential coding signaling protocol It depends on the necessary conditions when doing.

FIG. 1 is an electrical block diagram of a dual mode communication receiver of the present invention that overcomes the aforementioned problems and can be used in existing paging systems using existing paging signaling protocols. The dual mode communication receiver of the present invention comprises:
It enables data transmission at very high data bit rates of 8 kilobits per second or more. The dual mode communication receiver of the present invention provides excellent battery saving performance characteristics and uses existing paging signaling to maintain the receiver sensitivity characteristics of prior art communication receivers using conventional paging signaling protocols. Compatible with protocol. A dual mode communication receiver according to the present invention comprises first receiving means for receiving and detecting information transmitted in a first modulation format, such as a conventional FM modulated format, wherein the first receiving means uses the first modulation format. Providing a second receiving means for receiving and detecting information transmitted in a second modulation format, such as one of the linear modulation formats, which enables high-speed transmission of message information in response to the information detected by Operation can be performed. This transmission format is described in FIGS. 2A to 2C and described in detail below. The transmission protocol of FIGS. 2A to 2C enables the transmission of information modulated by the conventional FM modulation format, and the transmission of message information modulated by the linear modulation format that enables higher-speed data transmission. Will be possible. In FIG. 1, receiver 102 receives information modulated in either an FM modulation format or a linear modulation format. Battery Saving Switch (Battery Saver Switch) 10
4 is the receiver 10 under the control of the decoder / controller 106
Power 2 to enable reception of transmitted information. Battery saving switch 104 is also coupled to FM demodulator 108 to enable demodulation of FM modulation information received by receiver 102. The demodulated information is provided to decoder / controller 106. Coupled to the decoder / controller 106 is a code memory 110 for storing address information assigned to the dual mode communication receiver. When an address corresponding to predetermined address information assigned to the communication receiver is detected in the demodulated information, one of two operations is performed, which will be described in detail below. In the first case, a battery saving switch
104 maintains power to the FM demodulator 108 under the control of the decoder / controller 106 so that further demodulation of message information received in the FM modulation format occurs. The received message information is temporarily stored in a memory, usually located in the decoder / controller 106, such as a random access memory. The stored message information is called up by the user and displayed on the display 111. The operation of receiving and decoding the address information is well known to those skilled in the art.

However, unlike prior art receivers, FM demodulators
Power sent to 108 is interrupted by battery saver switch 104 under control of decoder / controller 106 and provided to linear demodulator 112 to demodulate information received in the second modulation format. The information received in the second modulation format is received by the receiver 102 and the receiver 1
02 couples the received information to the linear demodulator 112. The demodulated message information is coupled from the output of the linear demodulator 112 to the input of a data processing unit 114. Linear demodulator 112
Is enabled, the battery saving switch 104 supplies power to the data processing unit 114 and the data presenting means 116. Decoder / controller 106 is coupled to data processing unit 114 to enable data processing circuit 114 to process message information received in a second modulation format. The processed message information is
It can be temporarily stored in the memory 118, called up by the user, and displayed on the presentation means 116.

2A and 2B are timing diagrams illustrating the signaling format of the dual mode communication receiver of the present invention. As shown in FIG. 2A, when a message transmission is initiated on a channel, a preamble 202 modulated in an FM modulation format is transmitted on the channel, followed by a plurality of message batches 204-206. You. Each of the message batches 204-206 has a predetermined transmission time interval to allow for transmission of address and message information modulated in the FM modulation format or, for high speed data, modulated in the linear modulation format. Modulation of address and message information in the FM modulation format is well known in the art. Data modulation of linear modulation format such as SEDM modulation format
U.S. Pat.No. 4,737,969 to Steel et al., `` Spectral, assigned to the assignee of the present invention and incorporated herein by reference.
ly Efficient Digital Modulation Method and Apparat
us ". All information transmitted within a particular batch is modulated with a common modulation format. As described in further detail below, one or more batches of information may be modulated in an FM modulation format to intersperse one or more batches of information modulated in a linear modulation format. The channel load causes a break 208 during transmission, after which the preamble 202 is transmitted again, allowing the receiver to resynchronize with the batch transmission.

FIG. 2B shows in more detail the case where a batch modulated in a linear modulation format is interleaved with a batch modulated in an FM modulation format. In the preferred embodiment of the present invention, the preamble 202 is a sequence of alternating bits 1 and 0 modulated using the FM modulation format. The preamble 202 allows the receiver to wake up from the battery saving time interval, recognize that transmission has begun on the channel, and allow the receiver to obtain bit synchronization with the transmitted signal. After transmission of the preamble 202, each batch consists of a synchronization codeword 214 followed by an address 210 and message 212 information or high-speed data 216.
It is constituted by and. Synchronization codeword 214 is modulated in a modulation format appropriate for the type of data transmitted in the batch to allow synchronization with the transmitted information. No.
In the example shown in FIG. 2B, the synchronization codeword 214 is FM
Modulated in a modulation format, followed by an address 210 and a message 212, also modulated in an FM modulation format. Each transmission batch is encoded using an encoded synchronization codeword to effect a transmission of a predetermined number of addresses and / or message information codewords, for example, sixteen. As shown, a message 212 associated with a first receiver address 210 is transmitted, followed by a message 212 'associated with a second receiver address 210', and so on. Message 21 of second receiver
2 'is not a normal message information code word, but a predetermined "batch" index, the transmission batch in which the high-speed message information addressed to the receiver is transmitted, as shown in the next transmission batch 218'. To the receiver. As shown, batch 218 'includes high-speed message information 216 modulated in a linear modulation format. Batch 2
18 'begins with a synchronization codeword 214', which is used to signal the start on the message. This will be described below. Following transmission of batch 218 ', another high speed message information may be transmitted in another batch, address and message information modulated by another conventional modulation method may be transmitted in another batch, or as shown. Thus, the batch transmission can be ended until another address and message information can be transmitted.

FIG. 2C is a timing chart illustrating the battery saver operation of the dual mode communication receiver of the present invention. Power is first supplied to the receiver section during time interval 220 and the time interval 222
During which it is supplied to an FM demodulator to enable reception of preamble and synchronization codeword information modulated in an FM modulation format. The power supply to the linear demodulator is
Prohibited during 224, thereby saving power in the receiver. Upon detecting the preamble and the synchronization codeword, power is supplied to the receiver during time interval 220 '.
Power supply to the FM demodulator is maintained during time interval 222 'to receive the additional address and message information transmitted in the first transmission batch. For the next submission batch,
The power supply to the receiver section is maintained during the time interval 230 because of the high speed data intended for the receiver. However, power supply to the FM modulator is interrupted during time interval 228 and power is provided to the linear demodulator during time interval 232. If high-speed data information is received during the time interval 232, power supply to the receiver unit is interrupted during the time interval 234, and power supply to the linear demodulator is interrupted during the time interval 236. During the time interval 238, power is supplied to the receiver section again, and during the time interval 240, power is supplied to the FM demodulator, so that message information can be received again in the next sequence of message batch transmission. .

In summary, power is provided to the receiver and FM demodulator periodically to enable reception of address and message information using a signaling protocol that provides battery saving capabilities for the receiver. If the message information indicates that high-speed data transmission is approaching, power supply to the FM demodulator is interrupted and power is supplied to the linear demodulator to enable reception of high-speed data. Powering the linear demodulator and high-speed data storage only during high-speed data transmission can significantly increase the battery life of the receiver compared to receiving all information in a linear modulation format. it can.

An alternative embodiment of the signaling format of the dual mode receiver of the present invention is shown in FIG. 2D. In this embodiment, the information is a first channel 250 used for transmitting low speed message information modulated in the FM modulation format and a second channel 250 used for transmitting high speed message information modulated in the linear modulation format. It is transmitted on two channels of two channels 252. The batch of low speed data 204A-206A overlaps in time with the batch of high speed data 204B-206B. The dual mode receiver of the present invention operates on first channel receive message information, including conventional numeric or alphanumeric messages addressed to the dual mode receiver. If you are sending a long alphanumeric or voice message, the message indicator information
Direct the dual mode receiver to a predetermined message batch transmitted on the channel and transmitted on the second channel. After receiving the indicator information, the dual mode receiver selects a second channel to receive the high-speed message information during a given batch identified by the indicator. Upon receiving the fast message, the receiver again selects the first channel. In accordance with an alternative embodiment of the present invention shown in FIG. 2D, the modulation is performed in the FM modulation format by maintaining all of the low speed message transmissions on the first channel and all of the high speed message transmissions on the second channel. An efficient way of combining a conventional paging receiver for receiving information with the dual mode receiver of the present invention is possible. This allows the conventional signaling format to be converted to batches 204A-20A on the first channel.
It can be used for transmitting 6A information and can easily mix conventional receivers and dual mode receivers.

FIG. 3 is an enlarged electrical block diagram used to explain the receiver operation of the dual mode communication receiver of the present invention. The transmitted information signal is modulated in FM or linear modulation format,
Captured by Antenna 302 couples this information signal to the input of receiver portion 102, specifically a radio frequency (RF) amplifier 306. The message information is transmitted on appropriate RF channels such as the high band, UHF band and 900 MHz band. RF amplifier 306 amplifies a received information signal, such as a signal received at a 930 MHz paging channel frequency or the like, and couples amplified information signal 306 A to an input of first mixer 308. In the preferred embodiment of the present invention, the first oscillator signal 310A generated by the frequency synthesizer 310 is also coupled to the first mixer 308. The first mixer 308 mixes the amplified information signal 306A and the first oscillator signal 310A to form a 45 MHz
A first intermediate frequency or IF signal 308A, such as an IF signal of z, is provided. It is coupled to the input of the first IF filter 312. It should be understood that other IF frequencies may be utilized, especially if other paging channel frequencies are utilized. The output of IF filter 312 is an on-channel information signal 312A, which is coupled to the input of second converter 314. The conversion unit 314 will be described in detail below. The second converter 314 converts the on-channel information signal 312A into
This also uses the second oscillator signal 310B generated by the synthesizer 310 to mix to a lower intermediate frequency, such as 455 KHz. The second conversion unit 314 amplifies the intermediate frequency signal obtained as a result, and amplifies the FM demodulator unit 108 or the linear output unit 3
A second IF signal suitable for coupling to any of the 24 is provided.

Receiver section 304 operates in a manner similar to a conventional FM receiver, but unlike a conventional FM receiver, receiver section 304 of the present invention also includes an automatic frequency control section 316. Control unit 31
6 is coupled to the second converter 314 to appropriately sample the second IF signal to provide a frequency correction signal 316A. This signal couples to frequency synthesizer 310 to maintain receiver tuning for the assigned channel. Maintaining receiver tuning is particularly important for properly receiving high speed data information transmitted in a linear modulation format. The use of a frequency synthesizer to generate the first and second oscillator frequencies allows the receiver to make operation selections with respect to a plurality of operating frequencies selected by code memory programming or the like.
It should be understood that other oscillator circuits, such as fixed frequency oscillator circuits that can be adjusted from the automatic frequency controller 316 with the frequency correction signal, can be utilized as well.

An automatic gain controller 320 is also coupled to the second converter 314 of the dual mode receiver of the present invention. The automatic gain control unit 320
The 2IF signal is sampled to provide a gain correction signal 320A, which is coupled to RF amplifier 306 to maintain a predetermined gain of RF amplifier 306. The gain correction signal is also coupled to the second converter 314 to maintain a predetermined gain of the second converter 314. Maintaining the gain of the RF amplifier 306 and the second converter 314 is necessary for proper reception of high-speed data information transmitted in a linear modulation format, and makes the dual mode receiver of the present invention different from a conventional FM receiver. Further distinction.

When the message information is transmitted in the FM modulation format, the second IF signal is coupled to FM demodulator section. This will be described in detail below. FM demodulator section 108 demodulates the second IF signal in a manner well known to those skilled in the art, and returns the recovered data signal, which is a stream of binary information corresponding to the received address and message information transmitted in FM modulation format. Provides 108A. The recovered data signal 108A is coupled to an input of microcomputer 106. The microcomputer 106 has an input / output port or an I / O port 328.
Function as a decoder and controller through a single data input line. Microcomputer 106
Controls the complete operation of the communication receiver 300, and performs functions such as decryption, message storage and retrieval, display control, and notification, to name a few. Microcomputer
Reference numeral 106 is a microcomputer of a single chip, preferably a MC68HC05 manufactured by Motorola, and has a CPU 340 for performing operation control. Internal bus 330 is microcomputer 1
Connect each of the 06 operating elements. The I / O port 328 (shown separately in FIG. 3) is connected to the microcomputer 106 by the battery saver switch 104, the audio processor 114, the display 111, and the digital storage unit 368.
And provides multiple control and data lines for communication from external circuitry. Timing means such as a timer 334 are used to generate timing signals required for operation of the communication receiver, such as battery saver timing, warning timing, and message storage and display timing. The oscillator 332 serves as a clock for the operation of the CPU 340, and serves as a reference clock for the timer 334. RAM 338 is used to store information used in executing various firmware routines that control the operation of communication receiver 300, and may also be used to store short messages, such as numeric messages. The ROM 336 includes microcontrollers including routines necessary for decoding the recovered data signal 322A, controlling the battery saver, storing and retrieving messages in the digital storage unit 368, and generally controlling the pager operation and message presentation. Firmware routines used to control the operation of computer 106 are included. The notification generator 342 provides a warning signal 106G in response to decoding the FM modulated signaling information. The code memory 110 (not shown in FIG. 3) has an I / O port
It is connected to the microcomputer 106 through 328. The code memory is preferably an EEPROM (electrically erasable and programmable read-only memory) storing one or more predetermined addresses to which the communication receiver 300 responds.

When the FM modulated signaling information is received, it is decoded by microcomputer 106, which functions as a decoder, in a manner well known to those skilled in the art. Recovered data signal 322
If the information in A matches any of the stored predetermined addresses, the subsequently received information is decrypted,
It is determined whether additional information modulated in the FM modulation format is destined for the receiver, or whether additional information modulated in the linear modulation format is destined. If the additional information is transmitted in an FM modulation format, the recovered message information is received and stored in the microcomputer's RAM 338 or in a digital storage 368 described in detail below, and the broadcast signal 106G is broadcast. Generated by generator 342. The notification signal 106G is coupled to an audio processing circuit 344, which drives a transducer 346 to deliver an audible notification signal. Other forms of sensory alerts, such as tactile or vibration alerts, may also be provided to alert the user as well.

If the additional information is sent in a linear modulation format, microcomputer 106 decodes the index information.
The microcomputer 106 maintains the operation of monitoring and decoding information transmitted in the FM modulation format until the end of the current batch. At the end of the current batch, the power supply to the receiver is interrupted until the next assigned batch or batch identified by the indicator is reached,
During this time, high-speed data is transmitted. The microcomputer 106 generates a battery saving control signal 106D through the I / O port 328. This signal couples to the battery saver switch 104 to interrupt power to the FM demodulator 108 and to power the linear demodulator 112 including the linear output 324, quadrature demodulator 350, and digital storage 368. . This will be described in detail below.

The second IF output signal carrying high-speed data information
Combined with 24. The output of the linear output unit 324 is
50, specifically coupled to the input of the third mixer 352. Third
A local oscillator is also coupled to the third mixer 352, which is preferably in the range of 35 to 150 KHz. However, it should be understood that other frequencies can be utilized as well. The signal from the linear output unit 324 is the third local oscillator signal 3
54 to generate a third IF signal at the output of the third mixer 352. This signal is coupled to a third IF amplifier 356. The third IF amplifier is a low gain amplifier that buffers an output signal from an input signal. The third output signal is coupled to I-channel mixer 358 and Q-channel mixer 360. I / O
Oscillator 362 provides a quadrature oscillator signal at the third IF frequency, which is coupled to I-channel mixer 358 and Q-channel
Mixed with the third output signal of mixer 360 to provide a baseband I-channel signal and a Q-channel signal at the output of the mixer. The baseband I channel signal is coupled to a low pass filter 364 and the baseband Q channel signal is coupled to a low pass filter 366 to represent a stream of pairs of information codes corresponding to the encoded high speed data information. 1
A pair of baseband audio signals is provided.

The stream of information code pairs is coupled to an input of a digital storage 368, specifically an analog-to-digital (A / D) converter 370. The A / D converter 370 converts a pair of information codes into 364, 36
At least 2 of the highest frequency components (in Hz) of the output of 6
Sampling at double speed. For 3 kHz audio information encoded on the I and Q channels, the sampling rate is preferably 6 kHz for each I and Q channel or a total of 12 kHz. It should be understood that the data sampling rates shown here are only examples and other sampling rates may be used depending on the rate at which the message information was originally encoded.

During a batch in which high-speed data is being transmitted, microcomputer 106 issues a count enable signal 106A, which is coupled to address counter 372. The A / D converter 370 is also enabled, and sampling of the information code pair is performed. The A / D converter 370 generates a high speed sample clock signal 370A, which is used to synchronize (clock) the address counter 372, and which duplicates the sampled information code pair over a data line 370B. The addresses to be loaded into the port random access memory 374 are sequentially generated.
The information code pairs loaded in real time into the dual port RAM 374 at high speed are processed by the microcomputer 106 after all the high speed data has been received, thereby consuming it because the microcomputer 106 does not need to process the information in real time. Energy is greatly reduced. Microcomputer 106 accesses the stored information code pair via data line 106C and address line 106B, and in a preferred embodiment of the present invention,
The information code pair is processed to generate ASCII encoded information when alphanumeric data is transmitted, and CVSD encoded data when audio data is transmitted. Other data formats can be used as well, such as the BCD data format for numeric messages and the LPC coded data format for voice messages. ASCII-encoded data or CVSD-encoded data is used until information is requested by the user of the communication receiver.
Stored in dual port RAM. The stored ASCII encoded data is recovered by the user using a switch (not shown) for selecting and reading the stored message. When reading the stored ASCII encoded message, the user selects the message to be read, activates the read switch, the microcomputer 106 recovers the data, and the recovered data 106E is displayed on the display 111 such as a liquid crystal display. Be able to present. When reading a CVSD encoded message, the user selects the message to read, activates the read switch, and the microcomputer 106
And enable the recovered data 106E to be presented to the audio processor 114. Processor 1
14 functions as a CVSD decoder, converts digital audio information into an analog audio signal, and this signal is
To present a voice message to the user. The microcomputer 106 receives the frequency selection signal 106H
, But this signal is coupled to the frequency synthesizer 310 to allow selection of different operating frequencies as described above.

FIG. 4 is an electrical block diagram showing details of a battery saving function of the dual mode communication receiver of the present invention. Microcomputer 106 controls battery saving operation of the communication receiver through a battery saver control signal 106D coupled to battery saver switch 104. The battery saver switch 104 stores the power in the receiver unit 102 via the receiver supply line 104A, the right angle detector 350 via the right angle detector supply line 104B, and the digital storage via the digital storage unit supply line 104C. In section 368, FM modulator supply line 104D
Data limiter 380 coupled to FM demodulator 322 via
To the FM demodulator section 108, and to the linear output supply line 104
Power can be selectively supplied to the linear output unit 324 via E. Elements for selectively switching the power supply to each of the receiver sections are well known and include, to name a few, switching devices such as transistor switches and switching current source references. The microcomputer 106 includes an RF amplifier 306, a first mixer 308, a frequency synthesizer 310, an IF filter 312, a second mixer 382, a second IF amplifier 384, and an automatic gain control unit 3.
It controls power supply to the receiver unit 102 including elements such as 20 and the automatic frequency control unit 316, and power supply to the FM demodulator 108 during transmission of FM-modulated message information.
The microcomputer 106 also controls the power supply to the receiver, the linear demodulator and the digital storage during transmission of the linearly modulated message information. The microcomputer 326 also controls the supply of power to the digital storage during processing of stored high-speed message information and reading of stored messages. In summary, the battery saver switch 104, under the control of the microcomputer 106, powers only those circuits currently used to receive or process information, thereby minimizing battery energy consumption. I am holding it down.

FIGS. 5A and 5B are flowcharts illustrating the operation of the dual mode communication receiver of the present invention. In FIG. 5A, when the user turns on the power to the receiver in step 500, the microcomputer is initialized in step 502 and the battery saving routine is enabled. In step 504, power is supplied to the receiver, and in step 506, the power is also supplied to the FM demodulator section, so that a preamble search and acquisition routine is started. In step 508, the decoder monitors the information received on the channel for a preamble signal or other signal that can obtain bit synchronization. At step 508, if no preamble signal or other signal is detected within a predetermined search window time interval, at step 510, the microcomputer communicates with the receiver and FM.
The power supply to the demodulator is interrupted and the process returns to the battery saving routine at step 512 until the next time interval. In the next time interval, power is again supplied to the receiver and FM demodulator.

If a preamble is detected at step 508, bit synchronization is obtained in a manner well known in the art, and the microcomputer starts a synchronization codeword acquisition routine at step 514. If no synchronization codeword is detected within the predetermined time interval at step 514, the microcomputer interrupts the power supply to the receiver and the FM demodulator at step 510, and at step 512, the battery saving routine continues until the next time interval. Go back to In the next time interval, the power is again
Supplied to FM demodulator.

When the synchronization code word corresponding to the batch to which the receiver was assigned is detected in step 514, the microcomputer monitors the received address and message information, and in step 516 the address and message destined for the receiver are Make it detectable. If the address is not found in the current batch, the microcomputer monitors the received signal for a synchronization codeword at step 514.

When the address is detected in step 516, the microcomputer evaluates the next received codeword in step 518 to determine whether the message information being transmitted is low-speed message information or high-speed message information. If the transmitted information is slow message information, the microcomputer retrieves the information from the code memory at step 520 to identify whether the received address is a data address or a tone only address. If the address is a data address in step 520, the message information following the address is stored in step 522 and the user is alerted that the message has been received. If the address is identified as a tone-only address in step 520, the user is alerted that the page has been received. Step 522 or 524
At step 510, after receiving and processing the message, if no other information is received in the current batch, the microcomputer returns to the battery saving routine,
Interrupt the power supply to the receiver.

If the information received in the first modulation format indicates in step 518 that the high speed data message is to be received in the second modulation format, the microcomputer decodes the data indicator in step 526 of FIG. 5B. I do. When the end of the current batch is detected, the step
At 528, the power supply to the FM demodulator is interrupted. At step 530, the microcomputer determines whether high-speed message information is transmitted on the second channel. Second
If a high speed message is to be sent on the channel, the second channel is selected in step 532. If the second channel is not selected in step 530, or step 532
If selected at step 534, power is then provided to the linear demodulator during the batch indicated by the indicator at step 534 and to the digital storage at step 536. Step 538
The microcomputer is an address counter and D / A
Sends an enable signal to the
At 540, high speed sampling and storage of the received data is enabled. End of message (EOM) at step 540
When a character is received, or a predetermined number of message bits are received, step 544 informs the user that a message has been received. In step 546, the microcomputer interrupts the power supply to the linear demodulator. While the received high-speed data is being processed, power is maintained in the digital storage. When the processing of the high-speed message information is completed, the supply of power to the digital storage unit is interrupted in step 548. At step 550, the microcomputer determines whether the second channel has been selected for receiving high-speed message information. If the second channel is selected in step 550,
The microcomputer again selects the first channel in step 552. When the first channel is selected at step 550 or 552, the microcomputer returns to the normal battery saving routine at step 512 of FIG. 5A.

Thus, a dual mode receiver capable of receiving addresses and messages transmitted in FM modulation format and receiving high speed data messages transmitted in linear modulation format on the same or different radio frequency channels Was explained. This dual mode receiver has a battery saving feature that individually controls the supply of power to the FM demodulator, linear demodulator and digital storage, thereby consuming during normal receiver operation in FM modulation mode. Minimize power supply. When high-speed message information is being received, the digital storage samples and stores the high-speed message information in real time, after which the stored information is processed by a microcomputer decoder to prepare for display of the information.

While a particular embodiment of the present invention has been shown and described, different modifications and improvements will occur to those skilled in the art. All modifications which maintain the basic underlying principles disclosed and claimed herein have the scope and spirit of the invention

Continuation of the front page (72) Inventor Schwendman, Robert Jay 590 S.A.S.Avenue, Pompano Beach, Florida, United States of America 590 (58) Surveyed field (Int.Cl. ⁶ , DB name) H04B 1/16-1/28 H04B 7/24-7/26 102 H04Q 7/00-7/38

Claims (10)

(57) [Claims] 1. means for receiving information transmitted on a common channel in a first and second modulation format; first means for detecting information transmitted on a common channel in a first modulation format; and first modulation. A second means for detecting information transmitted in the second modulation format in response to the information detected in the format. 2. The dual mode selective call receiver according to claim 1, wherein the first modulation format is frequency shift key FM modulation. 3. The dual mode communication receiver according to claim 1, wherein the second modulation format is a linear modulation format. 4. The dual mode communication receiver according to claim 1, wherein the information transmitted in the first modulation format is transmitted in the first signaling format. 5. The dual mode communication receiver according to claim 1, wherein the information transmitted in the second modulation format is transmitted in a second signaling format. 6. A means for receiving information transmitted in an FM modulation format and a linear modulation format; a first means for detecting information transmitted in an FM modulation format; and in response to information detected in the FM modulation format. , Second means for detecting information transmitted in a linear modulation format; and a dual mode communication receiver. 7. The dual mode communication receiver according to claim 6, wherein the information transmitted in the FM modulation format is transmitted in the first signaling format. 8. The dual mode communication receiver according to claim 6, wherein the information transmitted in the linear modulation format is transmitted in the second signaling format. 9. A means for receiving information transmitted in a first and second modulation format on a common channel; a first means for detecting information transmitted in a first modulation format on a common channel; a first modulation format A second means for detecting information transmitted in the second modulation format in response to the information detected in the step (a); and supplying power to the reception means to detect the information transmitted in the first and second modulation formats. A third means for enabling reception, further supplying power to the first means,
Allows the detection of information transmitted in the modulation format,
Said third means for further powering said second means in response to information detected in the first modulation format to enable detection of information transmitted in the second modulation format. A dual mode communication receiver, characterized in that: 10. A means for receiving information transmitted in an FM modulation format and a linear modulation format; a first means for detecting information transmitted in an FM modulation format; in response to information detected in the FM modulation format, Second means for detecting information transmitted in a linear modulation format; and third means for supplying power to the receiving means to enable reception of information transmitted in an FM and linear modulation format, Further supplying power to the first means to enable detection of information transmitted in the FM modulation format, and further supplying power to the second means in response to the information detected in the FM modulation format; A dual mode communication receiver, characterized in that said third means enables detection of information transmitted in a modulation format.