JP2870756B2 - Spatial filter image processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a spatial filter image processing device.

2. Description of the Related Art Conventionally, in a digital copying apparatus, spatial filter image processing such as smoothing, edge extraction, and edge enhancement has been performed. For example, a plurality of n rows and a plurality of n rows (hereinafter, n × n
). In the spatial filter image processing of the image data composed of the pixels of the above, a window of an image composed of 5 × 5 pixels centered on one pixel A in the image data composed of the n × n pixels is set and set. 5 for each pixel in the window
The data obtained by performing the spatial filter image processing on the pixel A is obtained by multiplying the pixel A by a filter coefficient of × 5 and calculating the sum of the multiplied data. Here, the image data of each pixel is, for example, 6-bit image data representing 64 gradations.

For example, an image matrix X composed of 5 × 5 pixels Xij is represented by the following equation. On the other hand, if a filter coefficient matrix W composed of 5 × 5 filter coefficient elements Wij is expressed by the following equation, The pixel data FW after the spatial filter image processing is represented by the following equation.

_{FW = W 11 X 11 + W} 12 X 12 + W 13 X 13 + W 14 X 14 + W 15 X 15 + W 21 X 21 + W 22 X 22 + W 23 X 23 + W 24 X 24 + W 25 X 25 + W 31 X 31 + W 32 X 32 + W ₃₃ X ₃₃ + W ₃₄ X ₃₄ + W ₃₅ X ₃₅ + W ₄₁ X ₄₁ + W ₄₂ X ₄₂ + W ₄₃ X ₄₃ + W ₄₄ X ₄₄ + W ₄₅ X ₄₅ + W ₅₁ X ₅₁ + W ₅₂ X ₅₂ + W ₅₃ X ₅₃ + W ₅₄ X ₅₄ + W ₅₅ X ₅₅ (3) FIG. 2 is a block diagram of a spatial filter image processing apparatus that performs spatial filter image processing on a 5 × 5 image matrix X with a 5 × 5 filter coefficient matrix W.

In the processing circuit 51 in FIG. 2, the data X ₁₁ , X
_{12, X 13, X 14,} X 15 is in the order at a cycle of a predetermined clock signal, the multiplier M ₁₁ each having a multiplication coefficient _{W 11, W 12, W 13} , W 14, W 15, M 12, M 13, The data input to M ₁₄ and M ₁₅ and multiplied by the multipliers M ₁₁ to M ₁₅ are respectively stored in a register D 51 and adders A 51 to A 5.
4 is input to each first input terminal. At this time, the register D51 temporarily stores the input data at the clock cycle, and then inputs the data to the second input terminal of the adder A51. The adders A51 to A54 add the data input to the first input terminal and the data input to the second input terminal, and then add the data of the addition result to the register D5.
Output to 2 or D55. In response to this, the registers D52 to D54 temporarily store the input data at the above-described clock cycle, and then input the data to the adders A52 to A54. The register D55 temporarily stores the input data at the clock cycle, and then inputs the data to the first input terminal of the adder ADD as the output of the processing circuit 51.

The processing circuits 52 to 55 are configured in the same manner as the processing circuit 51 except that the processing circuits 52 to 55 include a multiplier having a multiplier of a value of each element from the second row to the fifth row of the filter coefficient matrix W, Each of the processing circuits 52 to 55 respectively receives input pixel data X ₂₁ to X ₂₅ , X ₃₁ to X ₃₅ , X ₄₁ to
After performing image filter processing on X ₄₅ , X ₅₁ to X _{55 in the same} manner as the processing circuit 51, each data of the processing result is output to the second to fifth input terminals of the adder ADD, respectively. Further, the adder ADD adds each data input to the first to fifth input terminals and outputs data FW as an addition result.

Further, for example, if a filter coefficient matrix Ws in the case of performing symmetric image filter processing on an image is represented by the following equation, The image FWs after the spatial filter image processing is represented by the following equation.

FWs = W ₁₁ X ₁₁ + W ₁₂ X ₁₂ + W ₁₃ X ₁₃ ± W ₁₂ X ₁₄ ± W ₁₁ X ₁₅ + W ₂₁ X ₂₁ + W ₂₂ X ₂₂ + W ₂₃ X ₂₃ ± W ₂₂ X ₂₄ ± W ₂₁ X ₂₅ + W ₃₁ X ₃₁ + W ₃₂ X ₃₂ + W ₃₃ X ₃₃ ± W ₃₂ X ₃₄ ± W ₃₁ X ₃₅ + W ₄₁ X ₄₁ + W ₄₂ X ₄₂ + W ₄₃ X ₄₃ ± W ₄₂ X ₄₄ ± W ₄₁ X ₄₅ + W ₅₁ X ₅₁ + W ₅₂ X ₅₂ + W ₅₃ X ₅₃ ± W ₅₂ X ₅₄ ± W ₅₁ X ₅₅ (Problems to be Solved by the Invention) Using the above-described conventional image filter processing device, the multiplier of the multiplier is set to the filter coefficient of the formula (4). The left and right symmetric image filter processing of (5) can be performed by setting as shown in each element of the matrix. However, as shown in FIG. 2, each processing for processing one row of pixel data is performed. Since five registers are connected in cascade between the inputs and outputs of the circuits 51 to 55, it takes five times the period of the clock to perform this spatial filter image processing. It takes a long processing time There was a problem point.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to provide a spatial filter image processing apparatus having a higher processing speed than the conventional example when performing the above-mentioned symmetric spatial filter image processing.

[Means for Solving the Problems] According to a first aspect of the present invention, a predetermined n-row and n-column element is set for an input image matrix X composed of n-rows and n-columns of pixel data Xij. Wij is a filter coefficient matrix W in which each element in columns other than the (n + 1) / 2-th column has the same data symmetrically around the (n + 1) / 2-th column,
In a spatial filter image processing device that performs spatial filter image processing, pixel data Xij of each row of an image matrix X that is sequentially input for each of a plurality of n rows is divided into a plurality of m systems and input, and n pieces of data are provided for each row. Input means;
The pixel data Xij of each row of the image matrix X, which is divided into a plurality of systems and input by the input means, is multiplied by the element Wij at the position of the corresponding matrix, and all the data of the multiplication result are obtained for each row. Addition is performed to calculate the sum of each row, and a plurality of m · n calculation means provided for each row and each system, and a different system among the sums calculated for each row by the calculation means based on an input clock signal. The data output from each of the arithmetic means are selectively switched and output, and a plurality of n switching means provided for each row, and the data output from each of the switching means are added to perform the spatial filter image processing. And adding means for outputting the subsequent data.

According to a second aspect of the present invention, for an input image matrix X composed of a plurality of n rows and a plurality of n columns of pixel data Xij, an (n + 1) / In a spatial filter image processing apparatus that performs spatial filter image processing using a filter coefficient matrix W in which each element of a column other than the two columns has the same data symmetrically with respect to the (n + 1) / 2 column, a plurality of n rows The pixel data Xij of each row of the image matrix X, which is separately input in sequence, is divided into a plurality of m systems and input, and is divided into a plurality of systems by n input means provided for each row and the n input means. The input pixel data Xij of each row of the image matrix X is multiplied by the element Wij at the position of the corresponding matrix, and all data of the multiplication result is added to each matrix to calculate the sum of each row. Provided for each line and for each system A plurality of m · n calculation means, and a plurality of m addition means provided for each system by adding data of each row calculated by a corresponding system among the data calculated by the calculation means, and inputted Switching means for selectively switching data output for each system from each of the adding means based on a clock signal and outputting the data as data after the spatial filter image processing.

[Operation] With the configuration as in the first invention, the n input means provided for each row can convert the pixel data Xij of each row of the image matrix X sequentially input for each of a plurality of n rows into a plurality m. After dividing and inputting, the plurality of m · n pieces of arithmetic means provided for each row and each line are divided into a plurality of systems by the n input means, and the image is input. The pixel data Xij of each row of the matrix X is multiplied by the element Wij at the position of the corresponding matrix, and all the data of the multiplication result are added for each row to calculate a total sum for each row. Next, the plurality of n switching units selectively switch each data output from each of the different types of arithmetic units in the sum calculated by each row by the arithmetic unit based on the input lock signal. Then, the addition means adds the data output from the switching means and outputs the data after the spatial filter image processing. Therefore, spatial filter image processing can be performed on the image matrix X using the filter coefficient matrix W.

Further, as in the second invention, the switching means and the addition means in the first invention are replaced with each other, and the data of each row calculated by the corresponding system out of the data calculated by the calculation means. Are added by the above-mentioned adding means, and the data output from each of the adding means for each system are selectively switched based on the input clock signal and output as the data after the spatial filter image processing. Therefore, spatial filter image processing can be performed on the image matrix X using the filter coefficient matrix W.

Embodiment FIG. 1 is a block diagram of a spatial filter image processing apparatus according to one embodiment of the present invention. In FIG. 1, the same components as those in FIG. 2 are denoted by the same reference numerals.

The spatial filter image processing apparatus according to the present embodiment is an apparatus that performs spatial filter image processing using a filter coefficient matrix W composed of 5 × 5 elements with respect to an image matrix X composed of 5 × 5 pixels. And five processing circuits 1 to 5 corresponding to the processing circuits 51 to 55 for performing a spatial filter process on one row of the image matrix X. After dividing the data of the pixel to be divided into two systems using flip-flops FF1 and FF2 having different storage times, the circuits of each system perform the above-mentioned spatial filter image processing, and each of the processing circuits 1 to 5
Is characterized in that the maximum number of registers cascaded between input and output is reduced to four.

In FIG. 1, an image matrix X expressed by the above equation (1)
Data X ₁₁ of each pixel of the first row _{of, X 12, X 13, X} 14, X
₁₅ is the clock CK output from the clock signal generator 11
Are sequentially input to the flip-flops FF1 and FF2 in the cycle of. Each of the flip-flops FF1 and FF2 has a period twice as long as the period of the clock CK output from the clock signal generator 11 and is an inverted clock signal from each other.
At the time of rising of CK1 and CK2, the input data is temporarily stored, and the multipliers M1 to M3 and the multiplier M4 are respectively stored.
Or output to M6. Hereinafter, the data X ₁₁ , X
The time between the input of X ₁₂ , X ₁₃ , X ₁₄ , and X ₁₅ to the processing circuit 1 and five times the clock CK is referred to as a first time. Data X ₁₁ , X ₁₂ ,
The time during which X ₁₃ , X ₁₄ , and X ₁₅ are input to the processing circuit 1 and that is five times the clock CK is referred to as a second time.
Here, in the first time, the multiplier M1 to data input to M3 are _{X 11, X 13, X 15} , The data is input to the multiplier M4 to M6 are X _12, X ₁₄ It is. Then, in the second time, data input to the multiplier M1 to M3 are X _12, X _14, The data is input to the multiplier M4 to M6 is X _11, X _13, X ₁₅ is there.

Before the spatial filter image processing, data W ₁₁ , W ₁₃ , W ₁₂ , W ₁₁ , W ₁₃ , and W ₁₂ of each element in the first row of the filter coefficient matrix Ws expressed by the above equation (4) are previously stored. Each multiplier
Multiplier data of M1 to M6 is input from the CPU 10 to the multipliers M1 to M6 via flip-flops FF3 to FF8. Each multiplier M1 to M6, after the input data multiplied by each multiplier _{W 11, W 13, W 12} , W 11, W 13, W 12 inputted from FF8 to not the flip-flop FF3,
The data of the multiplication result are respectively input to the first input terminal of the adder A1, the register D1, the second input terminal of the adder / subtractor AS1, the register D5, the first input terminal of the adder / subtractor AS2, and the register D11.
And the first input terminal of the adder A3, the first input terminal of the adder / subtractor AS3, the register D15 and the first input terminal of the adder / subtractor AS4.

Here, as shown in FIG. 1, in the adder / subtractor AS1,
The input from the multiplier M2 is added (+), and the input from the register D1 is added or subtracted (±). Also, the adder / subtractor AS
In 2, the input from the multiplier M3 is added (+), and the input from the register D5 is added or subtracted (±). Further, in the adder / subtractor AS3, the input from the multiplier M5 is added (+), and the input from the register D11 is added or subtracted (±). Furthermore, in the adder / subtractor AS4, the input from the multiplier M6 is added (+), and the input from the register D15 is added or subtracted (±).

As shown in FIGS. 3 and 4, registers D1 through D6
Respectively, temporarily stores and outputs input data at the rise of the clock CK1 at the cycle of the clock CK1. Each of the registers D11 to D17 temporarily stores and outputs the input data at the rising edge of the clock CK2 at the cycle of the clock CK2.
In FIGS. 3 and 4, the symbol * indicates multiplication.

A central processing circuit (hereinafter, referred to as a CPU) 10 has a + or-of the data of each of the fourth and fifth columns of the above equation (4) set using a keyboard (not shown). Is output to adders / subtractors AS1 to AS4 via flip-flops FF9 to FF12. The data output from the register D1 is input to a second input terminal of the adder / subtractor AS1. The adder / subtractor AS1 adds or subtracts the data input to the first input terminal and the data input to the second input terminal in accordance with the sign data input from the flip-flop FF9, and calculates the data of the operation result. Is output to the second input terminal of the adder A1 via the register D2. Adder A1
Adds the data input to the first input terminal and the data input to the second input terminal, and outputs the added data to the first input terminal of the adder A2 via the register D3. The adder A2 adds the data input to the first input terminal and the second input data, and outputs the addition result data to the a side of the switch SW via the register D4.

Data output from the register D5 is input to a second input terminal of the adder / subtractor AS2. The adder / subtractor AS2 adds or subtracts the data input to the first input terminal and the data input to the second input terminal according to the sign data output from the flip-flop FF10, and via the register D6. And outputs it to the first input terminal of the adder A4.

The data output from the register D11 is input to a second input terminal of the adder / subtractor AS3. The adder / subtractor AS3 adds or subtracts the data input to the first input terminal and the data input to the second input terminal to the code input from the flip-flop FF11 according to the data, and outputs the data of the operation result. To the second input terminal of the adder A3 via the register D12. The adder A3 adds the data input to the first input terminal and the data input to the second input terminal, and outputs the addition result data to the first input terminal of the adder A4 via the register D13. Output. The adder A4 adds the data input to the first input terminal and the data input to the second input terminal,
The data of the addition result is output to the b side of the switch SW via the register D14.

The data output from the register D15 is input to a second input terminal of the adder / subtractor AS4. The adder / subtractor AS4 adds or subtracts the data input to the first input terminal and the data input to the second input terminal according to the code data output from the flip-flop FF12, and
Output to the second input terminal of the adder A2 via 6 and D17.

The switch SW repeatedly switches to the a side or the b side based on the level of the clock CK1 output from the clock signal generator 11, and switches the data input to the a side or the data input to the b side. To the first input terminal of the adder ADD. Here, the switch SW is connected to the clock
When CK1 is at the H level, it is switched to the a side, while when the clock CK is at the L level, it is switched to the b side. Accordingly, as shown in FIG. 4, the first of the image data X ₁₁ not for each pixel is input at time to data calculated by performing the spatial filtering image processing based on X ₁₅
FWs starts from the clock CK from the start time of the first time.
After four times the period of the clock CK, the data is output from the register D4 via the switch SW a side. Then, after five times the period of the clock CK from the start time of the first time, The data is output from the register D14 via the switch b side.

The processing circuit 1 configured as described above includes multiplier data W ₁₁ , W ₁₃ , W ₁₂ , W ₁₁ , W ₁₃ , and W ₁₂ previously input from the CPU 10 to each of the multipliers M1 to M6. From the sign data input to each of the adders / subtractors AS1 to AS4, and the data successively input during the spatial filter image processing.
Based on X ₁₁ , X ₁₂ , X ₁₃ , X ₁₄ , and X ₁₅ , the data of the first row of the image matrix X of the above equation (1) on the right side of the above equation (5) and the above equation (4) The data of the operation results of the five terms relating to the first row of the filter coefficient matrix Ws of the
Output to the input terminal. As described above, the processing circuit 1
Since it has two circuits, for example, the processing circuit 1
When the first image matrix X ₁ of the image data X ₁₁ to the image data X ₁₁ to X ₁₅ in X ₂ of the second image matrix Following X ₁₅ is inputted to the processing circuit 2, the first image first data FW which to no image data X ₁₁ of the matrix X ₁ is calculated based on X ₁₅
s is the adder ADD from the register D4 via the a side of the switch SW.
First after being input, after one cycle time of the clock CK, to the free second image data X ₁₁ of the image matrix X ₂ X ₁₅
Is input from the register D14 to the first input terminal of the adder ADD via the b side of the switch SW.

The processing circuits 2 to 5 are configured and operate in the same manner as the processing circuit 1.

Here, the processing circuit 2 sends the above-mentioned multipliers M from the CPU 10 in advance.
Multiplier data W ₂₁ , W ₂₃ , W ₂₂ , W ₂₁ , W ₂₃ , W ₂₂ respectively input to the six multipliers corresponding to 1 to M 6
The sign of the data from the CPU10 are inputted into four subtractor corresponding to AS4 to the absence each subtractor AS1, data X ₂₁ to be input to the space-time filter image _{processing, X 22, X 23, X} 24, X
Based on ₂₅ , the above (1) of the right side of the above equation (5)
The data of the second row of the image matrix X of the equation and the data of the operation results of the five terms relating to the second row of the filter coefficient matrix Ws of the equation (4) are input to the second input terminal of the adder ADD. Output.

In addition, the processing circuit 3 previously transmits each of the multipliers M1
And multiplier data W ₃₁ , W ₃₃ , W ₃₂ , W ₃₁ , W ₃₃ , W ₃₂ respectively input to the six multipliers corresponding to M6 and CP in advance.
The sign of the data input to the four subtractor corresponding to AS4 to the absence each subtractor AS1 from U10, the data X ₃₁ to be input to the space-time filter image _{processing, X 32, X 33, X} 34, X 35
, The data on the third row of the image matrix X of the above equation (1) on the right side of the above equation (5) and the five data on the third row of the filter coefficient matrix Ws of the above equation (4) The data of the operation result of the term is output to the third input terminal of the adder ADD.

Further, the processing circuit 4 previously transmits each of the multipliers M
Multiplier data W ₄₁ , W ₄₃ , W ₄₂ , W ₄₁ , W ₄₃ , W ₄₂ input to the six multipliers corresponding to 1 to M 6 respectively,
Code data input from the CPU 10 to the four adders / subtractors corresponding to the adders / subtractors AS1 to AS4, and data X ₄₁ , X ₄₂ , X ₄₃ , X ₄₄ , and X input during spatial filter image processing.
Based on ₄₅ , the above (1) of the right side of the above equation (5)
The data of the fourth row of the image matrix X of the equation and the data of the operation results of the five terms relating to the fourth row of the filter coefficient matrix Ws of the equation (4) are input to the fourth input terminal of the adder ADD. Output.

Further, the processing circuit 5 further includes multiplier data W ₅₁ , W ₅₃ , W ₅₂ , W ₅₁ , W ₅₃ , W ₅₃ previously input from the CPU 10 to each of the six multipliers corresponding to each of the multipliers M 1 to M 6. ₅₂ ,
Code data previously input from the CPU 10 to the four adders / subtractors corresponding to the adders / subtractors AS1 to AS4, and data X ₅₁ , X ₅₂ , X ₅₃ , input during spatial filter image processing.
Based on X ₅₄ and X ₅₅ , the data of the fifth row of the image matrix X of the above equation (1) on the right side of the above equation (5) and the above (4)
The data of the operation results of the five terms relating to the fifth row of the filter coefficient matrix Ws in the expression are output to the fifth input terminal of the adder ADD.

Further, the adder ADD adds each data input to the first to fifth input terminals and outputs data FW as an addition result. As described above, when a plurality of image matrices X are sequentially input to this spatial filter processing circuit, at the output terminal of the adder ADD, at the cycle of the clock CK,
The calculated data FWs can be obtained.

As described above, five data items related to the pixel data in the first to fifth rows of the image matrix X on the right side of the data FW after the spatial filter image processing represented by the above equation (5) In each of the processing circuits 1 to 5 for calculating the terms, the data of each row of the image matrix X input using the flip-flops FF1 and FF2 is divided into two operation systems and input, and then the space of Since the filter image processing operation is performed and the maximum number of registers cascaded between the input and output of each of the processing circuits 1 to 5 is constituted by four, the image matrix X expressed by the above equation (1) On the other hand, in the left-right symmetric spatial filter image processing using the filter coefficient matrix Ws represented by the above equation (4), the image processing operation including multiplication and addition / subtraction inside the filter is performed by the clock CK1 having a cycle twice as long as the clock CK. For, CK2 Therefore, it is possible to cope with a case where high-speed processing is required as compared with the conventional example in which all operations need to be processed at the cycle of the clock CK.

In each of the processing circuits 1 to 5 of the above embodiment, the image data of the pixel to be input and processed is divided into two systems and input. However, the present invention is not limited to this. Accordingly, the spatial filter image processing operation may be performed after the input is divided into three or more systems using flip-flops in the same manner as described above.

In the above embodiment, in each of the processing circuits 1 to 5, data FWs output from the register D4 or the register corresponding to the register D4 and data FWs output from the register D14 or the register corresponding to the register D14 are alternatively selected. After switching and outputting, the addition is performed by the adder ADD. However, the present invention is not limited to this. Each data output from the registers D4 and four registers corresponding to the register D4 in the processing circuits 1 to 5 is added to the first adder. , While
Each data output from the register D14 and the register corresponding to the register D14 is added by a second adder, and the data FWs output from the first adder and the data FWs output from the second adder are added. May be selectively switched and output by another switch.

In the above embodiment, the case where the image matrix X is 5 × 5 and the filter coefficient matrix W is 5 × 5 is described. However, the present invention is not limited to this. This can be easily applied when the filter coefficient matrix W is a column and the filter coefficient matrix W has a plurality of rows and a plurality of columns.

[Effects of the Invention] As described above in detail, according to the present invention, the pixel data Xij of each row of the image matrix X sequentially input for each of a plurality of n rows is divided into a plurality of m systems and input, and provided for each row. N input means, and pixel data Xij of each row of the image matrix X, which is divided into a plurality of systems by the n input means, and is input to the element W
ij, multiply by ij, add all the data of the above multiplication result for each row, calculate the sum for each row, and based on a plurality of m · n calculation means provided for each row and each system, based on the input clock signal A plurality of n switching means provided for each row by selectively switching and outputting each data output from each of the calculating means of a different system among the sums calculated for each row by the calculating means; Means for adding data output from the means and outputting data after the spatial filter image processing, wherein pixel data of each row of the image matrix X sequentially input for each of a plurality of n rows
Since Xij is divided into a plurality of m systems and input, and the spatial filter image processing is performed for each system,
The spatial filter image processing can be performed on the input image matrix X with the filter coefficient matrix W at a higher speed than in the conventional example.

[Brief description of the drawings]

FIG. 1 is a block diagram of a spatial filter image processing apparatus according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional spatial filter image processing apparatus, and FIG. 3 is a spatial filter image processing of the present embodiment. FIG. 4 is a timing chart showing a part of the operation of the spatial filter image processing device of the present embodiment. 1 to 5 processing circuit, 10 CPU, 11 clock signal generator, FF1 to FF12 flop flop, M1
Or M6: Multiplier, D1 to D6, D11 to D17: Register, AS1 to AS4: Adder / subtractor, A1 to A4, ADD ...
… Adder, SW …… Switcher.

Claims (2)

(57) [Claims] 1. An input pixel data of a plurality of n rows and a plurality of n columns.
With respect to the image matrix X composed of Xij, each element of a column other than the (n + 1) / 2-th column is composed of a predetermined plurality of n rows and a plurality of n-column elements Wij. In a spatial filter image processing apparatus that performs spatial filter image processing with a filter coefficient matrix W having the same data symmetrically at the center, a plurality of pixel data Xij of each row of an image matrix X sequentially input for each of a plurality of n rows n input means which are divided into m systems and are provided for each row, and pixel data Xij of each row of the image matrix X which are divided into a plurality of systems and input by the n input means.
Is multiplied by the element Wij at the position of the corresponding matrix, all the data of the multiplication results are added for each row, and a total sum for each row is calculated.
n operation means, and, among the sums calculated for each row by the operation means based on the input clock signal, selectively output and output each data output from each operation means of a different system. Spatial filter image processing, comprising: a plurality of separately provided n switching means; and an adding means for adding data output from each of the switching means and outputting data after the spatial filter image processing. apparatus. 2. Input pixel data of plural n rows and plural n columns
With respect to the image matrix X composed of Xij, each element of a column other than the (n + 1) / 2-th column is composed of a predetermined plurality of n rows and a plurality of n-column elements Wij. In a spatial filter image processing apparatus that performs spatial filter image processing using a filter coefficient matrix W having the same data symmetrically at the center, pixel data Xij of each row of an image matrix X sequentially input for each of a plurality of n rows is represented by a plurality m N input means provided divided for each row and provided for each row, and pixel data Xij of each row of the image matrix X which is divided and input into a plurality of systems by the n input means, respectively.
Is multiplied by the element Wij at the position of the corresponding matrix, all the data of the multiplication results are added for each row, and a total sum for each row is calculated.
n pieces of arithmetic means, a plurality of m pieces of adding means provided for each row by adding the data of each row calculated by the corresponding system among the data calculated by the above arithmetic means, and A spatial filter image processing apparatus comprising: a switching unit that selectively switches data output from each of the addition units for each system and outputs the data as the spatial filter image processing image data.