JP2868159B2 - Static word line redundant memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device and method for implementing word line redundancy without penalty in access time.

Applying word line redundancy to increase the yield of memory arrays is accepted throughout the semiconductor industry. To be attractive, chip performance (eg, access time), power requirements,
Word line redundancy needs to be performed without significantly affecting the size. A number of approaches have been proposed with varying degrees of success. For example:

U.S. Pat. No. 4,365,319, issued to Takemae on December 21, 1982, discloses two types of decoders and drivers: a PROM decoder for determining whether an incoming address is a defective address, and a redundant array. Redundancy is implemented by using redundant drivers to drive, row address decoders and drivers to drive the main memory cell matrix. The first embodiment taught in the above patent (FIG. 1) is disadvantageous in terms of access time due to the switch 7 and in the semiconductor space since the switch must be large to handle large currents. Also occurs. In the second embodiment (FIG. 2-FIG. 4), a plurality of AND gates D ₀ to D ₆₃ is replaced the large switch 7 (FIG. 1), which has become a much improved Absent. This is because memory devices still have a penalty in access time (eg, AND gates) and AND gates D ₀ -D ₆₃
This is because there is still a disadvantage in the semiconductor space because the collective area of is still large. Third Embodiment (FIG. 5 to FIG.
FIG. 10) includes AND gates D ₉₁ -D ₉₄ (No. 6) to control the activation of the decoder and drivers 9 and 10 respectively.
FIG. 8) and AND gates D _{0 to} D ₃ (FIG. 8A) have a disadvantage in access time due to the AND gate delay.

U.S. Pat. No. 3,753,244, issued Aug. 14, 1973 to Sumilas et al., Discloses an extra line of memory cells on a memory chip along with a defective address store and comparator circuit. In addition, redundancy is implemented by prohibiting use of a defective cell line and replacing it with an extra cell line.

The Intel 2164A 64K DRAM represents a memory device that will have the same access time regardless of whether the regular word line in use is a redundant word line or not, but this product is expected to have redundant repairs Since the chip timing is set up at any time, regardless of whether or not the word line has been repaired, there is always a penalty in access time. More specifically, the redundant word
After the decoder senses a match with the incoming address, chip performance is slowed down due to the need to deselect the word decoder for the faulty word line. When a match is detected, the deselect generator is invoked to deselect the entire row of ordinary word decoders. After deselection of the faulty word line word decoder is performed, the word line drive is enabled. For more information about the 2164A, see the Intel Application
Description AP-131 (pp.14-16) and “An Analysis
of the i2164A ”(Mosaid Incorporated, p.5, 41-5
2, April 1982). Also note that IBM has a 72k DRAM that uses a similar approach.

Bell Labs 64K DRAM (RT Smith, JD
Chilipala, JFM bindels
s), RG Nelson, FH Fisher (Fis
cher), TF Mantz's paper (Laser Programma)
ble Redundancy and Yield Improvement in a 64K DRA
M ”(IEEE Journal of Solid-State Circuits, Vol.S
C-16, No. 5, pp. 506-514, October 1981) and 265K
DRAM (CA Benevit, JM Cassard (C
assard) KJ Dimmler, AC Damburi (D
umbri), MG Mound (Mound), FJ Procik (Proc
yk), WR Rosenzweig, AW Yanof's paper "A 256k Dynamic Random Access"
Memory "(IEEE Journal of Solid-State-Circuits,
Vol.SC-17, No.5, pp.857-816, October 1982)
By using laser fuse redundancy on the word line pitch, word line redundancy without affecting access time is implemented. There is no access time penalty because the defective word line is permanently disconnected by disconnecting the programmable link within the word line. This redundancy method is disadvantageous because the tighter the design rules for current and future high density memory products, the smaller the word line pitch. As a result, laser spot sizes and laser beam position accuracy are required that exceed those available from current laser programming systems. Thus, laser fuse redundancy is disadvantageous in that current levels of laser technology require an increased off-wordline pitch method or memory chip size due to the need for increased wordline pitch.

IBM 32K DRAM (BF Fitzgeral
d) and EP Thomas's paper "Circuit Implem
entation of Fusible Redundant Addresses on RAMs fo
r Producivity Enhancement ”(IBM Journal of Resear
ch and Development, Vol.24, No.3, pp.291-295, 198
(May 0), word line redundancy without disadvantage in access time is implemented by adding an individual sense amplifier array for redundant word lines. The redundant word line and the defective word line operate in parallel, and during the sensing operation,
There is no access penalty because the selection of the amplifier versus the normal sense amplifier is made. This approach is disadvantageous in that it requires an extra latch for each bit line along the redundant word line, thereby significantly increasing chip size.

Similarly, the papers "A Fault-Tolerant 64K Dynamic" by RP Senker, DG Clemons, WR Huber, JB Petrizzi, FJ Procyk, GM Trout
Random Access Memory ″ ”IEEE Transactions on Elec
tron Devices Vol.ED-26, No.6, June 1979)
Although there is no penalty in access time, it requires the placement of a disable fuse in each redundant and non-redundant decoder, thus teaching a word redundancy technique that greatly increases the required chip area.

BF Fitzgerald and DW Kemerer
r) Paper “Memory System With High-Perfomance Wor
d Redun dancy ”(IBM Technical Disclosure
Bulletin, Vol. 19, No. 5, October 1976) describes an embodiment of word redundancy that does not penalize access by accessing both normal and redundant rows in an independent array. ing. The selection of good data is made in the data out buffer.

EP-A-0 336 101 discloses a semiconductor memory device and a method for implementing word line redundancy. The redundant word decoder compares the incoming address signal with a list of defective addresses, generates at least one comparison signal in response to the comparison, and controls propagation of a redundant driver signal along at least one redundant word line. I do. The main trigger receives the comparison signal and, in response, activates activation of the main word line driver to generate a main driver signal. The main word line driver and the redundant word decoder are configured to operate in opposite states of the compare signal such that for a given compare signal, only one of the main driver signal and the redundant driver signal is applied to the memory array. respond.

EP-A-0 0 322 discloses a semiconductor device in which a redundant memory cell array is integrated with a main memory cell matrix. One memory cell array is selected by two types of decoders and drivers. When a redundant memory cell array is selected by a decoder, the decoder directly disables one type of decoder and driver, which in turn disables the other decoder and driver.

The redundant memory cell array is
A semiconductor memory device integrated with a matrix is disclosed in U.S. Pat. No. 4,392,11. The memory cells of the main memory cell matrix are the first
And a third memory selected by the third decoder
The memory cells of the cell array are selected by the second and third decoders. When the redundant memory cell array is selected by the second decoder, transmission of the clock signal to the first decoder is stopped by the switching circuit.

Although the above approach represents a significant advance in semiconductor manufacturing description, there remains a need for improved memory devices and techniques that can provide word line redundancy.
Accordingly, it is an object of the present invention to provide an improved memory device and method for implementing word line redundancy.

The object of the invention is solved by the features stated in the claims.

The memory device of the present invention includes a set of word decoders and a set of word line drivers. The number of word line drivers is greater than the number of word decoders. This means that since each word line driver is connected to another word line, the physical real address space is larger than the addressable address space. If one or more word lines are defective, a subset of word line drivers that do not include the word line driver belonging to the defective word line is selected. This set of word line drivers differs from the normal set of word line drivers used when none of the word lines are defective.

The memory device further includes storage means for storing information indicating the defective word line. This can be achieved by a "fuse address". memory·
Given that the device has the power supply voltage applied to it, in response to the information indicating the defective word line, such a subset of word line drivers is selected by the logic means. Part 1
Permanently assigned to a set of word decoders. Further, the logic means controls a switch between the word decoder and the word line driver, and connects a subset of the word line drivers selected by the logic means to the set of word decoders. Thereby, each word line driver of the selected subset of word line drivers is permanently connected to a particular one of the word decoders.

The selection and connection of the word line driver is made before the memory device is used, for example, for reading and writing data. Once the permanent connection of the word line driver is established, no additional steps need to be taken to implement word line redundancy since the connection between the word line driver and the word decoder is static. Therefore, when the memory device is actually used for reading and writing data, there is no need to further perform a decoding operation or a switching operation.

In principle, the present invention does not limit the number of redundant word lines. For example, if there is only one redundant word line, this also requires one additional switch. Therefore, since each word line driver requires one switch, if the number of word decoders is n, then n +
N + 1 word line drivers consisting of one word line and n
+1 switches are required.

The logic means in the example considered here needs to generate three control states for each switch. That is, the first control state indicates that the corresponding switch must be connected to its "normal" word decoder to which the switch is connected even when there are no defective word lines.

The second control state indicates that the associated switch needs to disconnect its associated word line driver from the word decoder because the word line driver belongs to the defective word line and should be replaced with another word line driver. . As a result, the use of the word line driver belonging to the defective word line is prohibited. This can be done by grounding the word line driver.

The third state of the logic means indicates that the word line driver need not be connected to a "normal" word decoder to which the word line driver is connected when there are no defective word lines by a corresponding switch. In this case, the word line driver is connected to another word decoder not yet connected to the word line driver via the switch in the first control state. For example, this
The word line preceding the "normal" word decoder to which the word line driver is connected when there are no defective word lines
Can be a decoder. This principle of operation can likewise be realized in the case of two or more redundant word lines.

Implementing word line redundancy does not cause any permanent disadvantages, so that computer systems incorporating a memory device according to the present invention are characterized by improved operating speeds over the prior art. Furthermore, the present invention is advantageous in that it requires relatively few electronic components to implement the principles of the present invention, and consequently requires less space on a chip.

A method for practicing the present invention will be described in detail below with reference to the following drawings.

FIG. 1 is a schematic diagram showing a connection between a word decoder and a word line driver by a switch.

FIG. 2 is a schematic diagram showing an implementation of a logic means including a plurality of logic blocks.

FIG. 3 is a circuit diagram illustrating one implementation of a logic block in more detail.

FIG. 4 is a diagram showing in more detail the implementation of the decoder incorporated in the logic block.

FIG. 5 is a circuit diagram illustrating one implementation of a switch.

As shown in FIG. 1, a set of word decoders 1 are connected by a plurality of switches 3 to a subset of a set of word line drivers 2. One set of word decoders in the example considered here is a word decoder W ₀ ,
W _1, W comprises _{2, ···, W m-1} , W m, W m + 1, ···, the W _n-1, W _n. One set of word line drivers 2 is a word line driver
_{WL 0, WL 1, WL 2} , ···, WL m-1, WL m, WL m + 1, ··· WL
_n-1, WL _n, including WL _{n + 1.} Each word line driver WL of the set of word line drivers 2 is connected to one word line. This word line is not shown in the figure. Since the number of word line drivers WL is greater than the number of word decoders, the physically addressed space is larger than the addressable address space. In the case considered here, there is one more word line driver than the word decoder.

One of the plurality of switches 3 is associated with each word line driver WL. Switch S ₀ of the plurality of switch 3 is connected to WL _0, S ₁ to WL _1, S ₂ is WL
₂ , ..., S _m-1 is WL _m-1 , Sm is WL _m , S _{m + 1} is WL _{m + 1}
, ..., S _n-1 is WL _n-1 , Sn is WL _n , S _{n + 1} is WL _{N + 1}
, Respectively. The number of switches S is equal to the number of word line drivers WL.

In the example considered here, it is assumed that there is a defect in the word line WL _m. As a result, the word line driver WL _m switches S
_m connects word line WL _m to ground, or by another word, switch Sm switches defective word line driver WL
_m is disconnected from the set of word decoders 1 so that
To disable the word line driver WL _m.

This situation is different from the normal situation where there is no defective word line driver. In the usual case, each word decoder of the set of word decoders 1 is connected to a predefined first subset of the word line drivers of the set of word line drivers 2. In this example, the first subset of word line drivers predefined for the normal case is a set of word line drivers WL ₀ , W
L _1, WL _2, ···, a WL _n-1, WL _n. Therefore, in the normal operation mode, a word decoder W ₀ is connected to the word line driver WL _0, W ₁ to WL _1, W ₂ in the WL _2, · · ·, W
_m-1 is WL _m-1 , W _m is WL _m , W _{m + 1} is WL _{m + 1} , ... W _n-1
Is connected to WL _n−1 and W _n is connected to WL _n . The word line driver WL _{n + 1} is connected to ground by its switch S _{n + 1} , and as a result is disabled.

The situation shown in FIG. 1 is different from a normal situation and shows a defect situation in which a defective word line exists. In the case shown in FIG. 1, one of the word line drivers, WL _m in this example, is defective, so that the addressable addressed space needs to have a different distribution of physical address space from normal situations. is there. This is performed by connecting all the decoders of the set of word decoders 1 to the word line drivers of the second subset of the set of word line drivers 2. The second subset excludes the defective word line driver WL _m, composed of two entire sets of word line drivers.

Word decoders W ₀ ~W _m-1, like the normal there is no defective word line driver situation, are connected to the respective word line drivers WL ₀ ~WL _m-1. In contrast, the word decoder W _m to _W-n, the word line driver WL _{m + 1} to WL
Connected to _{n + 1} . This has a defective word line WL _m, the word line is because they become disabled by a switch S _m. Word line drivers WL _{n + 1} is not longer disabled, word by switch S _{n + 1}
It is connected to the decoder W _n. Thus, it replaces the functionality of the defective word line driver WL _m.

Memory device shown in FIG. 1, the switch S ₀ to S _{n + 1}
Further comprises logic means 4 connected to the plurality of switches 3 for controlling each of the switches. The control logic means 4 is connected to the storage device 5. If there is a defective word line, the storage device 5 has the address of the defective word line and the address of the corresponding word line driver stored therein. In the example considered here, the address of the word line drivers WL _m resulting address Am of the word line m is stored in the storage device 5. The storage device 5 can be realized by a plurality of fuses programmed after testing the memory device.

FIG. 2 shows an overview of one implementation of the control logic 4. The control logic means 4 includes a plurality of address space distribution logic blocks 5, 6, 7,. One such address space distribution logic block (ASDL) exists for each switch S of the plurality of switches 3. Logical block 5 (ASDL0) belongs to switch S0, logical block 6 (ASDL1) belongs to S1, and logical block 7 (ASDL2)
Belongs to S2. The other logical blocks ASDL3 to ASDLn + 1 belonging to the switches S3 to Sn + 1 are not shown in FIG. Each logical block is provided with an input connected to FUSADR in the storage device 5 for input address A _m. Furthermore, each logical block has a decoder 8. Address A _m is the case that corresponds to the address of the word line the word line drivers of a switch logic block belongs match, the decoder 8 issues a signal. This results in two output signals S0 and S1 per logic block. The switch S0 outputs the output signal S0_0 of the logical block 5 (ASDL0).
And S1_0. Similarly, switches S1 and S2 are controlled by output signals S0_1, S1_1, and S0_2D, S1_2, respectively. Other output signals S0_3 to S0
_n + 1, S1_3 to S1_N + 1 are not shown in FIG.

Signal S0_x is equal to a logical 1, if the signal S1-x is equal to a logical 0, the switch of the corresponding word line driver WL _x S _x
By means that it is necessary to connect to the normal word decoder W _x. If the signal S0_x and S1_x is equal both to a logical 0, the switch S _x is controlled to disable the word line driver WL _x. Signal S0_x is equal to a logical 0, if the signal S1_x is equal to a logical 1, switch S _x is controlled to connect the word line driver WL _x, to the word decoders W _x-1.

The logic block 5 has another input signal FUSE.
_ENB is applied. This input signal FUSE_ENB becomes logic 1 when there is a defective word line. In the opposite case,
FUSE_ENB goes to logic 0. If FUSE_ENB is logic 0, this signal passes through AND gate 9 and reaches the corresponding input S0IN of the next logic block 6. As a result, the input signal
FUSE_ENB takes all logical blocks and propagates them.

As an example, FIG. 3 shows one of the logical blocks, logical block 5, in more detail. However, it should be noted that the circuit diagrams of all the logic blocks are the same.

The logic block 5 includes a decoder 8, an AND gate 9,
And an inverter 10. The input signal FUSADR is input to the decoder 8. And address stored in the storage device 5, if the result of the signal FUSADR is, that matches the address A _m of word lines m logical block ASDLm belongs decoder 8 signal
HIT_MISS will be issued. If both addresses match, signal HIT_MISS goes to logic zero.

In the case of the logical block 5, when the address stored in the storage device 5 is the address A0 of the word line 0, the signal HIT_
MISS goes to logic 0. The signal HIT_MISS is input to the AND gate 9 like the other input signal S0IN. In the case of the logic block 5, the input signal S0IN becomes the signal FUSE_ENB.
This PUSE enable signal FUSE_ENB goes to logic 0 when there are no defective word lines. In this case, the output of the AND gate 9 and the resulting S0_0 always become logic 0 irrespective of the state of the signal HIT_MISS.

If the signal FUSE_ENB is a logical one, this indicates that there is a defective word line. In this case, the AND gate 9
Output depends on the signal HIT_MISS. Inverter 10 is input
Connected to S0IN to generate output S1_0.

The example considered here has a 5-bit address space. Correspondingly, the decoder 8 has five inputs A0, A
A NAND gate having 1, A2, A3, and A4 is provided. Signal F
USADR includes address bits B0-B4 and complements of the address bits ▲ -〜. Either the true number of bits or complement bit FUSADR is connected to one input of NAND gate decoder 8 is determined by the address A _m logical block is assigned to the decoder 8 belongs.

This will be explained in more detail in connection with FIG. 4. The first line of FIG. 4 shows the bit positions of the signal FUSADR, namely B0-B4 and B0-B4. The second row of FIG. 4 shows the inputs A0 to A of the NAND gate of the logic block 5 (ASDL0).
Indicates which of the four is connected to which bit of the input signal FUSADR. ASDL0 uses only the complement bits B0-B4. B0 bar is connected to A0, ▲ ▼ is A1
, ▲ ▼ to A2, ▲ ▼ to A3, ▲ ▼ to A4
, Respectively.

Assuming that word line 0 having address 00000 is defective, the result is that the input to the NAND gate of decoder 8 of ASDL0 is 11111. Therefore, the signal HIT_MI of ASDL0
SS goes to logic 0, indicating that an address match has occurred. Similarly, bit B0 of FUSADR is set to N of decoder 8 of ASDL1.
It is connected to the input A0 of the AND gate, and the inputs of A1 to A4 remain unchanged. This principle is based on the fact that the bit position of the signal FUSADR is changed to other logic blocks ASDL2, ASDL3,. ASDLn +
This is also true when connecting to 1.

FIG. 5 shows an embodiment of the switch S. As an example, switch 11 shown in FIG. 5 is considered to be switch _{Sm + 1} . The switch Sm + 1 is connected to the word decoder W
having _{m + 1} and W _m connected to the input 12 and 13. In addition, switch S _{m + 1} has its ASDLm + at inputs 14 and 15
1 signals S0_m + 1 and S1_m + 1. The output 16 of the switch S _{m + 1} is connected to the word line driver WL of this switch.
Connected to _{m + 1} . The switch S _{m + 1} is connected to the control signal S0_m + 1
And the state of S1_m + 1, the word decoder W _{m + 1}
Or serve to establish selectively a connection between W _m and the word line drivers WL _{m + 1.} When the word line driver WL _{m + 1} belongs to the defective word line m + 1, the switch S _{m + 1} disables the use of the word line driver WL _{m + 1} . This is the fifth
This is performed by an internal circuit of the switch _{Sm + 1} as shown in the figure.

The control signals S0_m + 1 and S1_m + 1 are connected to the NOR gate 12, and the output of the NOR gate 12 is connected to the base of the transistor 13. One terminal of transistor 13 is output 16
And the other terminal of the transistor 13 is connected to the ground. When a match between the address stored in the storage device 5 and the address of the word line m + 1 occurs, the control signal
Both S0_m + 1 and S1_m + 1 become logic 0 (see FIGS. 3 and 4). As a result, the output of NOR gate 12 will be a logic one, and transistor 13 will connect output 16 of switch _{Sm + 1} to ground. As a result, the word line driver WL _{m + 1} is disconnected from the word decoder, and its use is prohibited.

Further, the switch S _{m + 1} includes pass gates 17 and 18. One terminal of the pass gate 17 is connected to the input 12 and consequently to the word decoder Wm _{+ 1} . The other terminal of pass gate 17 is connected to output 16 and consequently to word line driver WLm _{+ 1} . Pass gates 17 and 18 are comprised of two complementary transistors in CMOS technology used to implement this preferred embodiment. The gate of the transistor in pass gate 17 is connected to input 14, and the P-type transistor in pass gate 17 includes an inverter interconnected in the signal path. This applies to pass gate 18 as well. The gate of pass gate 18 is connected to input 15 and consequently to control signal S1_m + 1. If both control signals are equal to logic 0, pass gate 17 and
Not both 18 will be conductive, and no connection between the word decoder and word line driver WLm _{+ 1} will be established. If the control signal S0_m + 1 is logic 1, word decoders W _{m + 1} is connected to a word line driver WL _{m + 1,} in this case, one word can be connected at a time to the word line driver WL _{m + 1}・ Control signal S1 because it is limited to the decoder
_m + 1 becomes logic 0.

In the control signal S0_m + 1 is logic 0, the control signal S1_m + 1 be a logic 1, resulting in the word decoder W _m is connected to a word line driver WL _{m + 1.} This situation corresponds to the case shown in FIG.

The switching operation of the switch is performed when the power supply voltage is already applied to the memory device. Control logic means 4
When the connection between the word decoder and the word line driver is established by the switch under the control of the above, this connection remains unchanged at least as long as the power supply voltage is applied to the memory device. As a result, there is no need to perform switching or decoding operations "on the fly" when performing read / write operations using the memory device, so that there is no penalty in access time. Information that the word line is defective is indicated by the signal FUSE_ENB
After testing the device to program the same, and also testing the address of the defective word line to program the signal FUSADR, is stored in the memory device.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventors Beutner, Stephan Sindelfingen, Germany, Zomerhoenstraße 166/1 (72) Inventors Wernicke, Friedrich, Kristian Holzgarlingen, Germany 49 (56) reference Patent flat 3-8200 (JP, a) JP flat 7-122096 (JP, a) JP flat 6-150687 (JP, a) (58 ) investigated the field (Int.Cl. ⁶ , DB name) C11C 29/00 C11C 11/413

Claims (8)

(57) [Claims] A set of word decoders (1), a set of word line drivers (2), and a plurality of switches for connecting a subset of the word line drivers to the set of word decoders. 3) and a storage device (5) for storing identification information indicating a defective word line, wherein the set of word line drivers is used when none of the word lines has a defect. A plurality of second subsets of word lines, wherein the set of word line drivers is used when one of the word lines is defective. A driver, the memory device being responsive to an identification information signal read from the storage device, the first and the plurality of second devices being
An electrical logic circuit (4) for outputting control signals for activating said switches to selectively connect one of said subsets to said set of word decoders; and n word decoders; , Including at least n + 1 word line drivers and at least n + 1 switches S, wherein a control signal from the electrical logic circuit activates the switch to a next connected state; If 0 <i <n, each switch Si connects the word line driver i to the corresponding word decoder i, and the switch S
_{n + 1} connects word line driver n + 1 to ground potential; b) if word line m of said word line is defective, then when 0 <= i <m, each switch S _i is connected to word line driver connect the i to the corresponding word decoder i, switch S _m connects the word line driver m to the ground potential, when m <i of <= n + 1, the switch S _i is the corresponding word line driver i + 1 A memory device connected to a word decoder i. Wherein said electric logic circuit, respectively, comprise at least n + 1 pieces of logical block (ASDL) assigned to one of at least (n + 1) switches S, each of the logic blocks, switch S _i 2. The memory device according to claim 1, wherein the control signal can be generated. If wherein each of said logic block has an input for inputting an address A _m of defective word lines m, corresponding to the address A _m is the logical block is assigned the word line driver m A decoding means (8) for outputting a signal (HIT_MISS) to the
The memory device according to claim 2. 4. Each of said logical blocks (ASDL _i )
But a pair of signals of the switches S _i control a corresponding S0 and
S1 is configured to generate as an output, and is connected as a first input (S0IN) to _one of the output signal pair S0 and S1 of the preceding logical block (ASDL _i-1 ), and the first preceding block (ASDL ₀₎ ) First input (S0IN) is an enable signal (F
4. The memory device of claim 3, wherein each of the logic blocks (ASDL _i ) is connected as a second input to a signal identifying a defective word line. 5. The memory device according to claim 1, wherein said storage device is a ROM. 6. An integrated circuit chip incorporating the memory device according to claim 1. 7. A computer system comprising the memory device according to claim 1. 8. An electrical logic circuit comprising: one of three predetermined selectable connection states for each of said switches belonging to said first subset of word line drivers in response to said identification information signal. 2. The memory device according to claim 1, wherein a control signal is generated to select the memory device.