JP2862527B1 - Spread spectrum communication equipment - Google Patents

Abstract

Abstract: [PROBLEMS] To improve communication quality for a plurality of channel transmissions in which data having different required characteristics are mixed. When transmitting a plurality of data channels having different required data quality, transmission rate, and transmission delay,
For the channel Ch1 such as CB which requires high-speed demodulation and the data channel Ch2 with high importance, QPSK modulation is performed in the modulator 1 by controlling the former data cycle and adaptively changing the latter signal point arrangement. Further, when there is transmission data in the channels Ch3 and Ch4, the data rate is set in parallel according to the communication path conditions and the quality required for each data, and the QPS
K modulation is performed, and each QPSK modulation symbol is converted to an orthogonal code 1,
2 and 3 are multiplexed in parallel.
The signal is directly spread by N sequences and transmitted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum communication apparatus capable of transmitting a plurality of channels in which data having different qualities, transmission rates, and transmission delays are mixed.

[0002]

2. Description of the Related Art CDMA (Code Divis) in the mobile communication field.
DS (Direct Multiple Access)
There is IS-95 standardized as a CDMA cellular telephone system using spread spectrum of the (Sequence) system, and transmission of voice and low-speed data is realized. This C
In DMA, a near-far problem caused by a difference in the distance between a mobile station and a base station causes system capacity degradation. The near-far problem means that the received power of the signal transmitted from the mobile station to the base station rapidly decreases as the distance from the base station increases, so that the signal transmitted from the mobile station located near the base station causes Is masked. That is, a mobile station close to the base station can perform communication without hindrance, but a mobile station far from the base station is masked when there is a mobile station transmitting near the base station and hinders communication.

[0003] In order to solve the distance problem, a power control for controlling the transmission power of the mobile station to an appropriate value according to the distance from the base station is adopted. In a closed-loop power control method, which is one type of power control, a power control bit (PCB) is transmitted from a base station to control transmission power transmitted from a mobile station. In this case, the transmission power of the mobile station is controlled by the PCB so that the reception power received from all the mobile stations in the base station becomes the same. By transmitting the PCB from the base station to the mobile station in this way, the near-far problem can be solved.

[0004]

By the way, in order to improve the quality of data, interleaving and FEC (Forwar) are required.
d Error Correction) is required, and it is conceivable that this error correction method is applied to a PCB to improve the quality. However, in the error correction method using interleaving and FEC, the receiving side requires error correction processing such as deinterleaving and Viterbi decoding, so that the delay time required for decoding increases. For example, in the case of IS-95, the delay time becomes 40 ms or more. However, in the power control using the PCB, since the transmission power of the mobile station is controlled in real time from the reception power of the base station, a high-speed response is required. Therefore, the PCB is transmitted without using interleaving and FEC, and the receiving side is designed to increase the speed by extracting the demodulated data obtained by demodulating the received signal as PCB data as it is. However, if an error correction method is not applied to the PCB, desired power control cannot be performed when the PCB is erroneous.

For example, FIG. 13 shows an example of a conventional data structure.
In the IS-95, as shown in FIG. 13, in the Traffic channel, 24 modulation symbols (1.25
(ms) Two consecutive symbols in the period are allocated to the power control channel as lost symbols, and a PCB consisting of two modulation symbols is inserted at that position.
In this method, since the processing gain (Gp) of the PCB is equivalent to the modulation symbol of another channel and no FEC is added, the error rate characteristic of the demodulated symbol greatly deteriorates, and the transmission power is power-controlled by the erroneous PCB. Fear arises. For this reason, there is a problem that the transmission power of the mobile station may vary greatly when controlled by a PCB that does not perform the error correction method.

In recent years, a high-speed data transmission method having a data rate of 1 Mbps (bits per second) or more has been studied in mobile communications.
Research on the DMA method is being conducted. As a high-speed data transmission in the CDMA system, a system in which a data rate and a chip rate are increased in one channel and transmission is conceivable is considered. Become.
For this reason, when a device is implemented, extremely high-speed signal processing is required, and it is difficult to realize the signal processing. Also,
As described above, in the CDMA system, a channel such as a PCB which responds at high speed is required. However, since an FEC cannot be added to this channel, there is a problem that an error rate characteristic is deteriorated.

Further, the propagation environment in mobile communication is a fading channel, and the condition of the communication channel changes every moment. Therefore, realizing a variable data rate transmission method that can adaptively change the data rate and a hierarchical structure that can change the communication quality according to the importance of data are the element technologies for realizing high-speed data transmission.

Accordingly, the present invention provides a spread spectrum communication apparatus capable of obtaining improved error rate characteristics even when data requiring high-speed demodulation such as PCB is transmitted without employing an error correction method. Its primary purpose is to provide. Also, the present invention provides a spread spectrum communication having elemental technologies necessary for a high-speed data transmission system by CDMA, such as variable data rate transmission and hierarchical transmission of data, according to the quality, transmission rate, and transmission delay required for each channel. It is a second object to provide a device.

[0009]

In order to achieve the first object, a spread spectrum communication apparatus according to the present invention multiplexes low-speed first data and second data faster than the first data. A communication device for transmitting data on the same channel during a first code period, allocating modulation symbols arranged in a first quadrant and a third quadrant in QPSK to the second data and performing QPSK modulation. , While the first data is in a second code period, QPSK is applied to the second data.
QPSK modulating means for performing QPSK modulation by allocating modulation symbols arranged in the second quadrant and the fourth quadrant in
And a spreading modulation means for spreading and modulating the QPSK modulation signal output from the QPSK modulation means.
According to the present invention, the four modulation symbols in QPSK are divided into two sets, and the second modulation symbols are divided into two sets according to the code of the low-speed first data.
Since different sets of modulation symbols are assigned to data, the first data and the second data can be multiplexed and transmitted on the same channel. At this time, the first data can be transmitted with high quality,
The second data can obtain a better error rate than QPSK equivalent to BPSK. Also, since the first data is not subjected to interleaving or error correction coding, high-speed demodulation becomes possible.

In order to achieve the above first and second objects, a spread spectrum communication apparatus according to the present invention multiplexes low-speed first data and second data faster than the first data. A communication unit for transmitting the same data in the same channel, comprising: a unit period setting means capable of setting a unit period of the first data in a burst-like manner; QPSK modulation is performed by assigning modulation symbols arranged in the first and third quadrants of QPSK to data, and the second data is assigned to the second quadrant and fourth quadrant of QPSK in the second data during the period of the second code. QPSK by allocating modulation symbols arranged in quadrants
QPSK modulation means for performing modulation and, when the first data does not exist, allocating modulation symbols arranged in a first quadrant and a third quadrant in QPSK to the second data to perform QPSK modulation; And a spread modulation means for spreading and modulating the QPSK modulated signal output from the means. According to this invention, the same operation and effect as those of the above invention can be obtained. Further, the data period of the first data can be varied in a burst manner in accordance with the condition of the communication path, required quality and transmission delay.

Furthermore, in order to achieve the first and second objects, a spread spectrum communication apparatus according to the present invention comprises a first data having a low speed and a second data having a higher speed than the first data.
A communication device for multiplexing data and transmitting the same data on the same channel, comprising: a unit period setting means variably setting a unit period of the first data in a time-division manner in a burst manner; During the period of the sign of “
The modulation symbols arranged in the first and third quadrants of the SK are assigned and QPSK modulated, and the first data is added to the second and fourth quadrants of the QPSK during the period of the second code. QPSK modulation is performed by allocating modulation symbols to be arranged, and when the first data does not exist, the first data in QPSK is added to the second data.
QPSK modulation means for performing QPSK modulation by allocating modulation symbols arranged in a quadrant and a third quadrant, and spreading modulation means for spreading and modulating a QPSK modulation signal output from the QPSK modulation means. According to this invention, the same operation and effect as those of the above invention can be obtained.

Furthermore, in order to achieve the first and second objects, the spread spectrum communication apparatus according to the present invention provides a spread spectrum communication apparatus in which low-speed first data is faster than the first data during a first code period. By assigning modulation symbols arranged in the first quadrant and the third quadrant in QPSK to the second data,
First QPSK modulating means for performing K modulation and allocating modulation symbols arranged in a second quadrant and a fourth quadrant in QPSK to the second data while the first data is in a second code, and performing QPSK modulation; A second QPSK modulator provided for each data for performing QPSK modulation on another data to be transmitted at a data rate set for each data; the first QPSK modulator and the second QPSK; Multiplexing means for multiplexing each QPSK modulation symbol sequence output from the modulation means by multiplying and adding the orthogonal codes orthogonal to each other, and spreading the multiplexed signal output from the multiplexing means; At least spreading modulation means for performing direct spreading by a sequence. According to this invention, the same operation and effect as those of the above invention can be obtained. Further, other data can be transmitted in addition to the first data and the second data, and a variable data rate transmission and a data hierarchy can be performed according to a required transmission rate for each channel, required quality and transmission delay time. Transmission can be performed.

Still further, in order to achieve the first object, the spread spectrum communication apparatus according to the present invention is arranged such that, during a period in which the low-speed first data is a first code, the second data having a higher speed than the first data. Are allocated to modulation symbols arranged in the first quadrant and the third quadrant in QPSK, and the first data is arranged in the second quadrant and the fourth quadrant in QPSK for the second data during the period of the second code. A spread spectrum communication apparatus comprising demodulation means for demodulating the first data and the second data from a QPSK modulated signal on which QPSK modulation is performed by assigning modulation symbols, wherein the QPSK demodulates the QPSK modulated signal. Demodulating means, and phase means for rotating the demodulated symbols output from the QPSK demodulating means by π / 4 and -π / 4 phases, respectively.
Integrating means for respectively integrating the in-phase channel components having one polarity in the two demodulated symbols which have been phase-rotated by the phase means over one unit period of the first data; and The integrated values are compared, and when the integrated value in the demodulated symbol rotated by π / 4 is large, the first data is determined to be the first code, and when the integrated value in the demodulated symbol rotated by -π / 4 is large. Is a first data demodulating means for judging the first data as a second code and outputting the code as demodulated data of the first data; and in the first data demodulating means, the value of the first data is During the period determined to be the code of 1, the phase of the demodulated symbol output from the QPSK demodulation unit is rotated by π / 4, and the first data demodulation unit performs the first data demodulation. During the period when the value is determined to be the second code, the phase of the demodulated symbol output from the QPSK demodulation unit is rotated by -π / 4, and the signal of the in-phase channel component is output as the demodulated data of the second data. A second data demodulation unit. According to the present invention, the QP
The four modulation symbols in SK are divided into two sets, and the first data multiplexed by differentiating the set of modulation symbols assigned to the second data according to the code of the first data at a low speed is used to integrate the multiplexed first data using an integrating means. Demodulation can be performed with a small error rate, and the second data can be demodulated by the QPSK demodulation unit. In addition, in the demodulation of the first data, deinterleaving and error correction processing are not required.
High speed demodulation is possible. Furthermore, the error rate of the second data demodulated by the QPSK demodulation unit is equivalent to BPSK better than QPSK.

Furthermore, in order to achieve the first object, the spread spectrum communication apparatus according to the present invention is characterized in that, during a period in which the low-speed first data is in the first code period, the second data is transmitted faster than the first data. Are allocated to modulation symbols arranged in the first and third quadrants of QPSK, and the first data is arranged in the second and fourth quadrants of QPSK for the second data during the period of the second code. A spread spectrum communication apparatus comprising demodulation means for demodulating the first data and the second data from a QPSK modulated signal on which QPSK modulation is performed by assigning a modulation symbol, wherein the QPSK demodulates the QPSK modulated signal. Demodulating means, and a demodulated symbol obtained by multiplying the demodulated symbol demodulated by the QPSK demodulating means by the in-phase channel component and the quadrature channel component. No. is the case of the first polarity to the phase of [pi / 4 rotation of the demodulated symbols, the sign of the result of the multiplication, in the case of the second polarity to the phase of the demodulated symbols -π
Phase rotation means for performing / 4 rotation, integration means for performing integration over a unit cycle of the first data with the polarity of the in-phase channel component of the demodulated symbol rotated by the phase rotation means as one polarity, and the integration means When the integration result of the means is the first polarity, the first data is determined to be the first sign, and when the integration result of the integration means is the second polarity, the first data is the second sign. And a first data demodulation means for outputting the code as demodulated data of the first data, and a period in which the value of the first data is determined to be the first code by the first data demodulation means. The phase of the demodulated symbol output from the QPSK demodulation unit is rotated by π / 4, and the period in which the value of the first data is determined to be the second code by the first data demodulation unit is equal to the period of the QPSK demodulation unit. The output is the phase of the demodulated symbol -
The signal of the in-phase channel after the rotation of π / 4 is
Second data demodulating means for outputting the data as demodulated data. According to the sixth spread spectrum communication apparatus, the same operation and effect as those of the above-described invention can be obtained. Further, the number of integrating means can be reduced to simplify the apparatus.

As described above, according to the present invention, a plurality of data having different required data qualities, transmission rates, and transmission delays are transmitted on the same channel. At this time, data requiring high-speed demodulation such as PCB is multiplexed and transmitted to a data channel of high importance. Specifically, while controlling the data period required for the former data, the latter is used to perform QPSK modulation by adaptively changing the constellation of the latter, and when there is data to be transmitted, the parallel Communication channel situation,
QPSK modulation is performed by setting a data rate according to the quality required for each data, and each QPSK modulated symbol is multiplexed in parallel by orthogonal codes, and is directly spread by a PN sequence for transmission.

On the other hand, on the receiving side, QPSK demodulation is performed on all assigned channels, and re-demodulation is performed on a data channel of high importance in which data that is adaptively QPSK-modulated and needs high-speed demodulation is multiplexed. By doing so, the error rate characteristics can be improved as compared with QPSK demodulation. In addition, data requiring high-speed modulation can be demodulated with a small error rate by integrating QPSK-demodulated data of high importance for a predetermined period by the integration means. Therefore, a spread spectrum communication apparatus equipped with elemental technologies required for a high-speed data transmission method by CDMA, such as variable data rate transmission and hierarchical transmission of data, according to the quality, transmission rate, and transmission delay required for each channel. Can be.

[0017]

Embodiments of the spread spectrum communication apparatus according to the present invention will be described below with reference to the drawings. First, a signal arrangement of a signal transmitted from a transmission unit in a spread spectrum communication apparatus according to the present invention will be described with reference to FIG. FIG. 1A is a diagram showing an example of a signal arrangement of a conventionally known QPSK (Quaternary Phase Shift Keying). As shown in FIG.
Since four modulation symbols of π / 4 and ± 3π / 4 are used, two input bits can be transmitted together by one modulation symbol. At this time, 2 bits are "11".
Is the modulation symbol (1, 1) of π / 4 arranged in the first quadrant, and if 2 bits are “01”, the modulation symbol (−1, 1, 3π / 4) arranged in the second quadrant. 1), and when two bits are “00”, it is a modulation symbol (−1, −1) of −3π / 4 arranged in the third quadrant, and 2
When the bit is “10”, −π /
4 modulation symbols (1, −1).

In the spread spectrum communication apparatus of the present invention, for example, low-speed first data such as PCB data requiring high-speed demodulation in channel Ch1 is transmitted to channel Ch1.
2 is multiplexed with the high-speed second data using QPSK and transmitted. For example, when the first data is “0”, the second data is QPSK-modulated by the first signal constellation BPSK-a shown in FIG. 1B and transmitted. That is, when the second data is "0", it is a symbol (-1, -1) of -3π / 4 arranged in the third quadrant, and when the second data is "1", it is arranged in the first quadrant. Π / 4 symbol (1, 1). As described above, when the first data is “0” at the time of QPSK modulation, the second data includes the symbols arranged in the first quadrant and the third quadrant of (1, 1) and (−1, −1). Are transmitted. When the first data is “1”, the second signal arrangement BPSK orthogonal to the first signal array BPSK-a shown in FIG.
The second data is QPSK-modulated by -b and transmitted. That is, when the second data is “0”, the symbol is a 3π / 4 symbol (−1, 1) arranged in the second quadrant, and when the second data is “1”, the symbol is arranged in the fourth quadrant. −π /
4 symbols (1, -1). Thus, QP
If the first data is “1” at the time of SK modulation, symbols arranged in the second and fourth quadrants of (1, −1) and (−1, 1) are assigned to the second data. Transmitted.

As described above, when the first data is "0" among the four modulation symbols in QPSK, two modulation symbols located in the first quadrant and the third quadrant are used when the second data is QPSK-modulated. However, when the first data is “1”, the second data and the fourth quadrant are subjected to QPSK modulation of the second data.
By using two modulation symbols located in the quadrant, the first data and the second data are multiplexed and can be transmitted by one channel. The configuration of this modulator will be described later. Then, on the receiving side of the spread spectrum communication apparatus of the present invention, the BP comprising the modulation symbol (1, 1) and the modulation symbol (-1, -1) shown in FIG.
When SK-a is received, the first data is demodulated to "0", and the modulation symbol (1, -1) and the modulation symbol (-1, -1) are demodulated.
When BPSK-b shown in FIG. 1C composed of 1) is received, the first data is demodulated to “1”. This demodulation is performed by a re-demodulation unit. The re-demodulation unit demodulates the second data by shifting the phase of a demodulated symbol demodulated by the QPSK demodulation unit in accordance with the demodulated first data. ing. The configuration of the re-demodulation unit will be described later.

Next, FIG. 2 shows an example of the data structure in the spread spectrum communication apparatus of the present invention, and FIG. 3 shows an example of the frame structure thereof. In this example, channels Ch1, Ch2, Ch3, Ch4 Are assigned. The channel Ch1 includes a channel Ch1-a and a channel Ch1-b.
Channel Ch1-a is a channel for transmitting a power control bit (PCB) for performing closed-loop power control, and channel Ch1-b is control information (data 1, data 2) requiring high-speed demodulation or data with the highest weight. (Data 3). Further, channels Ch2 and Ch
Channels 3 and Ch4 are channels for transmitting the second, third and fourth highest weighted data, respectively. The period of one frame is, for example, 614.4 μs.

FIG. 2 shows a data structure A,
Two examples of B and C are shown in FIGS. 2A, 2B and 2C, wherein the first data consisting of PCB and other data transmitted on channel Ch1 and the first data transmitted on channel Ch2. The two data are multiplexed and transmitted through the first transmission channel. The third data and the fourth data transmitted on the channels Ch3 and Ch4 are transmitted on the second transmission channel and the third transmission channel, respectively. Therefore, four code channels are transmitted by three transmission channels. In this case, the first data is only the PCB, or the burst PCB and control information (data 1 and data 2) requiring high-speed demodulation or data with the highest weight (data 3).
Are sequentially arranged.

In the example of the data structure A shown in FIG.
In the channel Ch1, only the PCB is transmitted. Less than,
The channel of the PCB is shown as channel Ch1-a. Since this PCB has a small number of bits to be transmitted, 1
One bit is transmitted in the power control group (PCG). Thus, the data rate of the channel Ch1-a is set to be low. The frame specification at this time is shown as a data structure A in FIG. As shown in the data configuration A, the bit rate of the channel Ch1-a (PCB) is set to a low speed of 1.627 kbps, and no error correction coding is performed. The number of BPSK-modulated symbols transmitted in one PCG, which is one frame, is one symbol.

The bit rate of the second data transmitted on the channel Ch2 in which the channel Ch1 is multiplexed is set to 312.5 kbps as shown in FIG. 3, and the convolutional coding at a coding rate of 1/2 is performed. ing. Therefore, the number of bits in one PCG is 192 bits, but the number of code symbols is twice as large as 384 symbols. In the channel Ch2, the first data and the second data are QPSK-modulated as described above. That is, the second data is QPSK-modulated using two modulation symbols located in the first quadrant and the third quadrant (when the first data is “0”), or the second data is subjected to the second quadrant and the fourth quadrant. QP using two modulation symbols located at
SK modulation is performed (when the first data is “1”). Therefore, the number of modulation symbols in one PCG, which is one frame in channel Ch2, is 384 symbols, which is the same as the number of code symbols.

Further, the bit rate of the third data transmitted on the channel Ch3 is 6 as shown in FIG.
25 kbps, coding rate 1/2, constraint length 7
Has been convolutionally coded. Therefore, the number of bits in one PCG is 384 bits, but the number of code symbols is twice as large as the number of 768 symbols. In channel Ch3, the third data is QPSK-modulated, so that the number of modulation symbols is one of the number of code symbols.
/ 2, which is 384 symbols. Further, the bit rate of the fourth data transmitted in the channel Ch4 is 937.5 kbps as shown in FIG. 3, and after the convolutional coding with a coding rate of 拘束 and a constraint length of 7, Punctured coding is performed at a conversion rate of 3/4. Therefore, the number of bits in one PCG as one frame is 512 bits, but the number of code symbols is 512 × 2 × (3/4) times the number of 768 symbols. In channel Ch4, since the fourth data is QPSK-modulated, the number of modulation symbols is 384, which is の of the number of code symbols.

Next, in the example of the data structure B shown in FIG. 2B, only the PCB is transmitted for the half frame period in the channel Ch1. Channel Ch1 of this PCB
In -a, the number of bits to be transmitted is small as described above.
Even if B is transmitted, transmission can be performed without increasing the error rate. The frame specification at this time is shown in FIG.
It is shown as Channel Ch1-a (PCB)
Is 1.627 kb in the same manner as the data configuration A.
ps, and no error correction encoding is performed. In addition, the number of BPSK-modulated modulation symbols transmitted in one PCG, which is a half frame, is one symbol. The data structure of the channels Ch2 to Ch4 is the same as the data structure A.

Further, in the example of the data structure C shown in FIG. 2C, the PCB is transmitted on the channel Ch1 for only 1/3 frame period, and the remaining data 1 to 3 which require higher quality are 2/3. It is transmitted during the frame period. Hereinafter, the channels of data 1 to data 3 are referred to as channel Ch1-b. That is, in one frame, the channel Ch1-a has a 1/3 frame period and the channel C
h1-b is composed of 2/3 frame periods. The frame specification at this time is shown as a data structure C in FIG. The bit rate of the channel Ch1-a (PCB) is set to a low speed of 1.627 kbps similarly to the data configuration A, and error correction coding is not performed. And 1/3
The number of BPSK-modulated modulation symbols transmitted in one PCG framed is one symbol. Also,
The bit rate of channel Ch1-b (data 1) is 6.510 kbps, and no error correction coding is performed. The number of bits transmitted in one PCG as one frame is four bits, the number of code symbols is four, and the number of modulation symbols subjected to BPSK modulation is four.

The bit rate of the channel Ch1-b (data 2) is 13.02 kbps, and no error correction coding is performed. Therefore, when the number of bits transmitted in one PCG as one frame is eight, the number of code symbols is eight and the number of modulation symbols is eight. Furthermore, the bit rate of channel Ch1-b (data 3) is 13.0.
It is set to 2 kbps, and convolutional coding with a coding rate of 1/2 and a constraint length of 7 is performed. Therefore, if the number of bits transmitted in one PCG as one frame is 8 bits, the number of code symbols is twice as large as 16 symbols,
The number of modulation symbols subjected to BPSK modulation is 16 symbols. Note that channels Ch2 to Ch4
Is the same as the data configuration A.

In the present invention, it is possible to transmit the above three types of data configurations, that is, the data configuration A, the data configuration B, and the data configuration C. Each of the data configurations is switched every frame of 614.4 μs and transmitted. It is possible. By the way, in the data structure B and the data structure C, the channel Ch1-a is not limited to the フ レ ー ム frame cycle or the ３ frame cycle, and the cycle is variable according to the condition of the communication path, the required quality, and the transmission delay. You may make it. Also, channel Ch1-a (PCB)
And channel C that is sequentially arranged and transmitted
For the data transmitted in h1-b, the configuration of data 1 or the configuration of data 3 is selected according to the condition of the communication path and the required quality.

Next, FIG. 4 shows a schematic configuration of the transmitting section of the spread spectrum communication apparatus according to the present invention which realizes the data configuration shown in FIG. 2 and the frame specifications shown in FIG. FIG.
, The frame generation unit 1 (101) transmits the data of the PCB in the channel Ch 1 -a to which the FEC is not added and the channel Ch 1-1 to which the FEC is added in some cases.
A code symbol is generated from the data in b, and the frame generation unit 2 (102, 103, 104) generates a code symbol according to the coding rate set for each data of the channels Ch2 to Ch3. Further, the modulation section 1 (105) performs QPSK from the input code symbols of the channels Ch1 and Ch2.
The modulation is performed and a modulation symbol is output.

Further, the modulation unit 2 (106, 107) uses the code symbol supplied from the frame generation unit 2 to perform QP
The SK modulation is performed, and a modulation symbol corresponding to the two code symbols is output. The multiplier 108, the multiplier 109, and the multiplier 1
Numeral 10 performs orthogonal coding by multiplying each modulation symbol output from the modulation unit 1 or the modulation unit 2 by the orthogonal code 1 to the orthogonal code 3 assigned to the modulation symbol. The amplifier 113 amplifies each of the orthogonally coded modulation symbols with a gain assigned to each modulation symbol. Then, the adder 114 adds all the orthogonally coded modulation symbols, and the spreading unit 115
-Spreading is performed using the PN code assigned for SS (Direct Sequence-Spread Spectrum), and a DS-SS signal is output. This DS-SS signal is transmitted.

Next, FIG. 5 shows a schematic configuration of the frame generation unit 1 indicated by reference numeral 101 in the spread spectrum communication apparatus shown in FIG. In FIG. 5, a Ch timing setting unit 201 outputs the symbol generation timing according to the processing gain (Gp) assigned to each frame for the data of the channel Ch1-a and the channel Ch1-b. The buffer 203 temporarily stores data of the channels Ch1-a and Ch1-b. In addition, when there is data that needs error correction processing in channel Ch1-b, convolutional encoder 204 has, for example, a coding rate of 1/2 and a constraint length of 7 according to the symbol generation timing output from Ch timing setting section 201. The convolutional encoding is performed, and the symbol generation unit 205 generates a code symbol from the convolutionally encoded code bits. Further, interleaver 206 performs interleaving to rearrange the order of code symbols, and selector 207 selects channel Ch1-a according to the symbol generation timing output from Ch timing setting section 201.
And the code symbol of the channel Ch1-b are selected and output.

FIG. 6 shows a schematic configuration of the frame generation unit 2 indicated by reference numerals 102, 103 and 104 in the spread spectrum communication apparatus shown in FIG. In FIG. 6, the input buffer 301 includes a channel Ch2.
Is temporarily stored, the convolutional encoder 302 performs convolutional coding with a coding rate of 、 and a constraint length of 7, for example, and the symbol generation unit 303 converts a code symbol from the convolutionally coded code bits. The interleaver 304 performs interleaving to rearrange the order of the code symbols.

FIG. 7 shows a schematic configuration of the modulation section 1 indicated by reference numeral 105 in the spread spectrum communication apparatus shown in FIG. In FIG. 7, an AND circuit 4
01 calculates the logical product of the code symbol of the channel Ch1 and the symbol generation timing sent from the Ch timing setting unit 201. The EXOR circuit 402 calculates the exclusive OR of the code symbol of the channel Ch2 and the symbol supplied from the AND circuit 401.
The QPSK modulator 403 sets the code symbol of the channel Ch2 to the in-phase channel Ich,
QPSK modulation is performed using the symbol supplied from 02 as the orthogonal channel Qch, and the modulated symbol is output.

In the EXOR circuit 402, if the code symbol of the channel Ch1 is "0", the code symbol of the channel Ch2 is used as is in the EXO circuit.
Output from the R circuit 402. Therefore, channel C
If the code symbol of h2 is “0”, the in-phase channel Ich and the quadrature channel Qch of the QPSK modulator 403 are used.
Is supplied with two code symbols “00” and the channel C
When the code symbol of h2 is “1”, the in-phase channel Ich and the quadrature channel Qch of the QPSK modulator 403 are used.
Is supplied with a two-code symbol "11". Further, when the code symbol of the channel Ch1 is “1”, the code symbol of the channel Ch2 is inverted and
Output from the XOR circuit 402. Therefore, when the code symbol of the channel Ch2 is “0”, the in-phase channel Ich and the quadrature channel Q of the QPSK modulator 403 are
ch is supplied with two code symbols “01”, and when the code symbol of the channel Ch2 is “1”, the in-phase channel Ich and the quadrature channel Q
The two-code symbol “10” is supplied to ch. Thus, the BP shown in FIGS. 1B and 1C obtained by multiplex-modulating the data of the channel Ch1 to the data of the channel Ch2.
Signal arrangements of SK-a and BPSK-b can be obtained.

Further, FIG. 8 shows a schematic configuration of the modulation section 2 indicated by reference numerals 106 and 107 in the spread spectrum communication apparatus shown in FIG. In FIG.
The S / P converter 501 performs a serial / parallel conversion for converting the input serial code symbol into two code symbols in parallel. QPSK modulator 502 has S / P
The parallel signal of two code symbols supplied from the converter 501 is supplied to the in-phase channel Ich and the quadrature channel Qch, and the QPSK modulation shown in FIG.
The modulation symbol is output.

Here, the operation of the transmission section in the spread spectrum communication apparatus according to the present invention will be described with reference to FIGS. P in channel Ch1-a
CB input data is input to the frame generation unit 1 (101) in accordance with the symbol generation timing sent from the Ch timing setting unit 201, and the internal input buffer 202
Is stored. Then, the data is read from the input buffer 202 and output to the selector 207 according to the symbol generation timing. FIG. 3 in channel Ch1-b.
When there is transmission data of data 1, data 2, or data 3 having the data configuration C shown in FIG. 6, the input data is stored in the input buffer 203 in accordance with the symbol generation timing transmitted from the Ch timing setting unit 201.

When the data has the structure of data 1 or data 2, the data is read from the input buffer 203 and output to the selector 207 in accordance with the symbol generation timing. When the data 3 is configured, the data is read from the input buffer 203 in accordance with the symbol generation timing and convolutionally coded by the convolutional encoder 204 at a coding rate of 、 and a constraint length of 7. Further, a code symbol is generated from the convolutional code in the symbol generation unit 205, and 61
The data is interleaved every 4.4 μs frame and output to the selector 207. In the selector 207, the data of the channel Ch1-a supplied from the input buffer 202 and the input buffer 203 or the interleaver 2 are supplied in accordance with the timing transmitted from the Ch timing setting unit 201.
And the data of the channel Ch1-b supplied from the selector 06 is selected and output. As a result, Ch1 data including the channels Ch1-a and Ch1-b is generated.

Further, channel Ch2, channel Ch
3, the data input to the channel Ch4 are the frame generator 2 (102) and the frame generator 2 (10
3), input to the frame generation unit 2 (104), and stored in the input buffer 301 inside the frame generation unit 2;
Then, the convolutional coded data is read out from the input buffer 301 and convolutionally coded by the convolutional coder 302 at a coding rate of 、 and a constraint length of 7, and a symbol generation unit 303 generates a code symbol from the convolutional code.
In 04, interleaving is performed every 614.4 μs frame.

The code symbol of the channel Ch1 output from the frame generator 1 (101) and the channel Ch2 output from the frame generator 2 (102)
Are supplied to the modulation section 1 (105).
The modulation unit 1 (105) assigns “1” when the code symbol of the channel Ch 1 exists, and “0” when the code symbol does not exist.
The logical product with the code symbol of h1 is calculated by the AND circuit 401. The output of the AND circuit 401 is supplied to the EXOR circuit 402, where the exclusive OR with the code symbol of the channel Ch2 is calculated, and the QPSK modulator 403
Supplied to Since the data of the channel Ch2 output from the EXOR circuit 402 is non-inverted / inverted according to the sign of the data of the channel Ch1, the modulation symbol output from the QPSK modulator 403 is
BPSK-a or BP shown in FIGS.
This is a modulation symbol based on the signal arrangement of SK-b.

In the modulation section 2 (106, 107) to which the code symbol output from the frame generation section 2 (103) or the frame generation section 2 (104) is supplied, the input code symbol is changed every two bits. S / P converter 50
1 is converted to serial / parallel by the QPSK modulator 5
02 and QPSK-modulated every two bits. At this time, the four signal points of the QPSK modulation are arranged as shown in FIG. Further, the multiplier 108 to which the modulation symbol from the modulation unit 1 (105) is supplied, and the modulation unit 2 (1
06) is supplied with the modulation symbol from
In the multiplier 110 to which the modulation symbol from the modulation unit 2 (107) is supplied, each of the preceding modulation units 105, 10
The QPSK signal input from each of the orthogonal codes 6, 107 and the orthogonal code 1, orthogonal code 2, and orthogonal code 3 are multiplied.

As a result, the modulation unit 1 (105) and the modulation unit 2
(106) The modulation symbol input from the modulation unit 2 (107) is orthogonally coded and input to the amplifier 111, the amplifier 112, and the amplifier 113, respectively. Amplifier 111,
After the amplifiers 112 and 113 amplify the orthogonally coded signals with the assigned gains, the adder 114 calculates the sum of the signals. The output from the adder 114 is directly spread by the PN code assigned to each user in the spreading section 115 to generate a DS-SS signal to be transmitted. As described above, in the transmission unit in the spread spectrum communication apparatus according to the present invention, the data of the channel Ch1 requiring high-speed demodulation is multiplexed with the data of the channel Ch2 and transmitted on the first transmission channel. Further, a second transmission channel Ch3 data is transmitted to the first transmission channel.
And the third transmission channel for transmitting the data of channel 4 are orthogonally multiplexed and spread spectrum and transmitted as DS-SS signals.

Next, FIG. 9 shows a schematic configuration of a receiving section of the spread spectrum communication apparatus according to the present invention which receives and demodulates the DS-SS signal as described above. The spread spectrum receiving apparatus shown in FIG. 9 includes three fingers, that is, a finger 1, a finger 2, and a finger 3 that can receive a rake (RAKE). In FIG. 9, A / D
The converter 601 performs analog-to-digital conversion of the received signal down-converted to baseband, and the A / D converter 601
The digitally converted received signal is stored. The finger 1, finger 2, and finger 3 are supplied with the received signal read from the buffer 602, apply despreading and inverse orthogonal transform to the received signal, and perform QPSK demodulation of the received signal.

The three fingers, finger 1, finger 2 and finger 3, have the same configuration, and the detailed configuration is shown in finger 1. Finger 1
In, the PN generator 603 generates a PN code according to the phase offset assigned to the finger 1, and the despreading unit 604 reverses the received signal output from the buffer 602 by the PN sequence output from the PN generator 603. Spreading. The orthogonal code generator 605 generates an orthogonal code according to the phase offset and the orthogonal channel number assigned to the finger 1. The inverse orthogonal transform is performed by the orthogonal code output from the unit 605. Further, demodulation section 607 performs QP of the inverse orthogonal transform signal output from inverse orthogonal transform section 606.
SK demodulation is performed and complex soft-decision demodulation symbols are output. Finger 1, finger 2, and finger 3 each have the same configuration as finger 1, and perform despreading, inverse orthogonal transform, and QPSK demodulation according to the assigned phase offset and orthogonal channel number, and output a complex soft-decision demodulated symbol. ing.

The channel combiner 608 performs the maximum ratio combining of the complex soft-decision demodulated symbols output from the fingers 1, 2 and 3. The re-demodulator 609 includes the channels Ch1 and C.
For the complex soft-decision demodulated symbol on which the data of h2 is multiplexed, the data of Ch1 is re-demodulated, and the data of channel Ch2 is re-demodulated based on the re-demodulated data of channel Ch1. Further, decoding section 610 performs parallel / serial conversion of the complex soft-decision demodulation symbol supplied from channel synthesis section 608 or the re-demodulation symbol supplied from re-demodulation section 609 as necessary, and then deinterleaves and performs Viterbi decoding. To perform error correction processing, and perform channel Ch2 and channel Ch.
3. The decoded data of channel Ch4 is output.

Next, FIG. 10 shows a schematic first configuration example of the re-demodulation section 609 in the receiving section of the spread spectrum communication apparatus according to the present invention shown in FIG. In FIG. 10, a Ch timing setting unit 701 assigns a processing gain (G
Each symbol generation timing is output according to p). The delay section 702 delays the maximum ratio-combined complex soft-decision demodulated symbols supplied from the channel combining section 608 in accordance with the symbol generation timing sent from the Ch timing setting section 701, and outputs a π / 4 phase shifter 70.
Numeral 3 rotates the phase of the complex soft-decision demodulation symbol by π / 4, and the −π / 4 phase shifter 704 rotates the phase of the complex soft-decision demodulation symbol by −π / 4.

The integral dump unit 705 and the integral dump unit 706
Are π / 4 phase shifters 703,-according to the symbol generation timing sent from the Ch timing setting section 701.
The integral dump is performed after the absolute value or the square operation of the in-phase channel Ich of the complex symbol output from the π / 4 phase shifter 704 is set to one polarity.
In this integration dump, the data in the channel Ch1 is integrated for a period corresponding to one unit cycle, and is dumped for each unit cycle. The comparison / determination unit 707 demodulates the demodulated code symbol of the channel Ch1 by comparing and determining two integration dump results immediately before the dump output from the integration dump unit 705 and the integration dump unit 706.
At this time, when the former integral value is large, the demodulation code symbol of “1” is outputted, and when the latter integral value is large, the demodulation code symbol of “0” is outputted. Furthermore, the data (for example, data without the FEC) added to the demodulated code symbol according to the generation timing sent from the Ch timing setting unit 701
Data 1 and data 2 in PCB and data structure C)
Or data with FEC (for example, channel Ch
2, data 3) in data structure C is determined.

When the demodulated code symbol determined by the comparison / determination section 707 is “1”, the phase shifter 708
02, the combined signal from the channel combining unit 608 delayed by π / 4 is rotated by π / 4, and when the demodulation code symbol is “0”, the delayed combined signal is rotated by π / 4 and output as the in-phase channel Ich component doing. Then, the 1: 2 selector 709 selects and outputs the PCB to which FEC is not added, the data 1 or the data 2 of the data configuration C based on the determination result of the comparison determination unit 707. Further, the 2: 1 selector 710 is provided in the comparison
Based on the determination result of 7, the demodulation code symbol of channel Ch2 and the demodulation code symbol of data 3 of data configuration C are selected and output.

Next, FIG. 11 shows a second schematic configuration example of the re-demodulation section 609 in the receiving section of the spread spectrum communication apparatus according to the present invention shown in FIG. In the second example of the re-demodulation unit 609, the configuration is simplified as compared with the first example. In the second example of the re-demodulation unit 609, the Ch timing setting unit 801 determines a processing gain (G) assigned to each frame with respect to the data of the channels Ch1-a and Ch1-b constituting the channel Ch1.
According to p), each symbol generation timing is output. The delay unit 802 delays the maximum soft-ratio complex soft-decision demodulated symbols supplied from the channel combining unit 608 according to the symbol generation timing sent from the Ch timing setting unit 801.

The I / Q multiplier 803 performs multiplication of the in-phase channel Ich symbol × orthogonal channel Qch symbol, and the phase shifter 804 outputs the result when the polarity sign of the multiplication result in the I / Q multiplier 803 is-. The input complex soft-decision demodulated symbol is rotated by π / 4 phase, and when the polarity sign of the multiplication result of the I / Q multiplier 803 is +, the phase is rotated by -π / 4. Further, according to the symbol generation timing sent from the Ch timing setting unit 801, the integration dump unit 805 sets the in-phase of the complex symbol output from the phase shifter 804 when the polarity sign of the multiplication result of the I / Q multiplier 803 is −. The channel Ich data is integrated as one polarity by an absolute value operation or a square operation. Also,
When the polarity sign of the multiplication result of the I, Q multiplier 803 is +,
The result obtained by multiplying the in-phase channel Ich data of the complex symbol output from the phase shifter 804 by -1 as one polarity by an absolute value operation or a square operation is integrated.

Further, when the polarity of the integration dump result output from integration dump section 805 is +, comparison / determination section 806 outputs “1” as the demodulation code symbol of channel Ch 1, and the polarity of the integration dump result changes. In the case of-
"0" is output as the demodulation code symbol of channel Ch1. Further, when the demodulated code symbol determined by the comparison determination unit 806 is “1”, the phase shifter 807
The phase of the combined signal from the channel combining section 608 delayed by 2 is shifted by π / 4, and the demodulated code symbol is set to “0”.
In this case, the delayed synthesized signal is rotated by -π / 4 phase and output as the in-phase channel Ich component. And
The 1: 2 selector 808 is based on the determination result of the comparison determination unit 806, and has no FEC added PCB and data structure C
Data 1 or data 2 is selected and output. Further, the 2: 1 selector 809 selects and outputs one of the demodulated code symbol of the channel Ch2 and the demodulated code symbol of the data 3 of the data configuration C based on the determination result of the comparison determination unit 806.

Next, the operation of the receiving section of the spread spectrum communication apparatus according to the present invention shown in FIG. 9 will be described. The received DS-SS signal down-converted to baseband is converted to a digital signal by an A / D converter 601 and stored in a buffer 602. Buffer 6
02 is read from the despreading unit 6
At 04, finger 1 is fed to finger 1
Generator 6 according to the phase offset assigned to
Despreading is performed by using the PN code generated from 03.
Next, the despread signal output from the despreading unit 604 is supplied to an inverse orthogonal transform unit 606, and is multiplied by the orthogonal code assigned to the channel number of the code channel desired to be demodulated and output from the orthogonal code generator 605, thereby performing inverse decoding. An orthogonal transform is performed. The inverse orthogonal signal output from the inverse orthogonal transform unit 606 is supplied to a demodulation unit 607, where the inverse orthogonal signal is QPSK-demodulated and a complex soft-decision demodulation symbol is output.

When RAKE reception is performed by finger 1, finger 2, and finger 3,
Received DS- sent from buffer 602 to finger 1
The SS signal is supplied to fingers 2 and 3, despreading is performed according to the phase offset assigned to each finger, and inverse orthogonal transform is performed using the same orthogonal code as finger 1. Then, the signals subjected to the inverse orthogonal transform are QPSK-demodulated, and complex soft-decision demodulated symbols are output. These operations are performed until data of all channels is demodulated.

When RAKE reception is performed and data of all channels is demodulated, channel combining section 608
In, the maximum ratio combining of the complex soft-decision demodulated symbols output from fingers 1, 2 and 3 is performed. Further, data of channel Ch1-a and channel Ch1-b constituting channel Ch1,
The complex soft-decision demodulation symbol multiplexed with the data of channel Ch2 is supplied to re-demodulation section 609, and the complex soft-decision demodulation symbol demodulated on channel Ch3 or Ch4 is supplied to decoding section 610.

Here, when the re-demodulation section 609 has the configuration of FIG. 10, the complex soft-decision demodulated symbols supplied from the channel synthesis section 608 are stored in the delay section 702, and the π / 4 phase shifters 703 and- In the π / 4 phase shifter 704, the phase is rotated by π / 4 and −π / 4, respectively, and is converted into an absolute value for the in-phase channel Ich. This absolute value is
The polarity of the in-phase channel Ich of the complex soft-decision demodulated symbol after the phase rotation is set to one polarity, and may be set to one polarity by a square operation instead of the absolute value. Then, the complex soft-decision demodulated symbol having one polarity is integrated by the integration dump unit 705 and the integration dump unit 706 for a period corresponding to one unit cycle of the data in the channel Ch1, and is dumped for each one unit cycle. The integral dump unit 705 and the integral dump unit 706 immediately before dumping
The two integrated dump values are supplied to a comparison / determination unit 707, and the two integrated dump values are compared. Here, the integral dump unit 7
When the level of the integral dump value in 05 is large, “1” is output as the determination result, and otherwise, “0” is output as the determination result. This determination result is a demodulated code symbol demodulated on channel Ch1.

Incidentally, the integral dump units 705, 70
In the integration dump in step 6, when the frame specification shown in FIG. 3 is used, the complex soft decision demodulated symbol having one polarity is integrated by the processing gain Gp / 64 symbol of the channel Ch1, and the dump is performed immediately thereafter. Will be. To explain the reason, in the case of the frame specification shown in FIG. 3, the chip rate is 40 Mcps and the modulation symbol rate is 625 kmsps (modulation-symbol per seco).
nd), and the processing gain Gp is equal to the chip rate divided by the modulation symbol rate. At this time, the number of modulation symbols in one frame is 384 symbols. Then, integrating the complex soft-decision demodulated symbol having one polarity by the processing gain Gp / 64 symbols of the channel Ch1 is equivalent to integrating for a period corresponding to one unit cycle of the data in the channel Ch1. .

A specific example will be described.
In the case of the data configuration A shown in (A), since the PCB transmits one modulation symbol per frame in the channel Ch1, the processing gain Gp is 64 × 3.
84. Therefore, in this case, the complex soft-decision demodulated symbols having one polarity are integrated by 384 symbols, and the number of 384 symbols is the number of modulation symbols of one frame in the channel Ch2. That is, in the data configuration A, the integral dump is performed for each frame corresponding to one unit cycle of the data in the channel Ch1. In addition, since one symbol of the PCB is demodulated based on the integrated dump value integrated for one frame period, the error rate of the PCB can be reduced.

In the case of the data structure B shown in FIG. 2 (B), the channel Ch1-
The processing gain Gp of a becomes 64 × 192, and the complex soft-decision demodulated symbols having one polarity are integrated by 192 symbols, but the number of 192 symbols is the channel Ch2.
, The number of modulation symbols of 1/2 frame. That is, in the data structure B, the integral dump is performed every １ ／ frame corresponding to one unit cycle of the data in the channel Ch1. In this case, one-symbol demodulation of the PCB is performed based on the integrated dump value obtained by integrating the half frame period, and the error rate of the PCB can be reduced.

In the case of the data structure C shown in FIG. 2C, the channel Ch1-
The processing gain Gp of a becomes 64 × 128, and the complex soft-decision demodulated symbols having one polarity are integrated and dumped for 128 symbols. And the channel Ch1-a
When the channel Ch1-b is specified to have the frame specification of the data 1, the processing gain Gp of the channel Ch1-b is 6
The complex soft-decision demodulated symbols having a polarity of 4 × 64 and having one polarity are integrated and dumped for 64 symbols. Further, when the channel Ch1-b has the frame specification of the data 2, the processing gain Gp of the channel Ch1-b is 64 × 32, and the complex soft-decision demodulated symbol having one polarity is equivalent to 32 symbols. Will be integrated. Further, when the channel Ch1-b has the frame specification of data 3, the processing gain Gp of the channel Ch1-b becomes 64 × 16, and the complex soft-decision demodulated symbol having one polarity is integrated dump of 16 symbols. Will be done.

Next, when the level of the integral dump value in the integral dump unit 705 is large, the comparison / judgment unit 707 outputs "1" as the judgment result, and otherwise outputs "0" as the judgment result. The reason why this determination result is a demodulated code symbol demodulated in channel Ch1 will be described. In the present invention, the channel Ch2 in which the data of the channel Ch1 is multiplexed is transmitted by the signal arrangement shown in FIG. 1B or FIG. 1C. Here, since the data of the channel Ch1 is set to “0”, it is assumed that the data is transmitted with the signal arrangement shown in FIG. When it is assumed that the transmitted signal is received in an ideal state without noise, the re-demodulation unit 609
Is rotated by π / 4 by the π / 4 phase shifter 703, the symbol is positioned on the orthogonal channel Qch axis. When the phase of the complex soft-decision demodulation symbol supplied to re-demodulation section 609 is rotated by -π / 4 by -π / 4 phase shifter 704, this symbol is positioned on the in-phase channel Ich axis.

Therefore, π / 4 phase shifter 703 and-
π / 4 and −π / 4 in the π / 4 phase shifter 704, respectively.
The complex soft-decision demodulated symbols that have been phase-rotated and have one polarity with respect to the in-phase channel Ich are integrated in the integration dump unit 705 and the integration dump unit 706, respectively.
The integral dump value in the integral dump unit 705 decreases, and the integral dump value in the integral dump unit 706 increases. At this time, “0” is output from the comparison determination unit 707, and the data of the channel Ch1 is demodulated by the comparison determination unit 707. When the data of channel Ch1 is set to “1” and transmitted with the signal arrangement shown in FIG. 1C, the phase of the complex soft-decision demodulation symbol supplied to re-demodulation section 609 is shifted by π / 4 phase shifter. When the phase is rotated by π / 4 according to 703, this symbol is positioned on the in-phase channel Ich axis. When the phase is rotated by −π / 4 by the −π / 4 phase shifter 704, the symbol is positioned on the Qch axis of the quadrature channel. Will be located.

Therefore, the π / 4 phase shifter 703 and-
π / 4 and −π / 4 in the π / 4 phase shifter 704, respectively.
The complex soft-decision demodulated symbols that have been phase-rotated and have one polarity with respect to the in-phase channel Ich are integrated in the integration dump unit 705 and the integration dump unit 706, respectively.
The integral dump value in the integral dump unit 705 increases, and the integral dump value in the integral dump unit 706 decreases. At this time, “1” is output from the comparison / determination unit 707, and the data of the channel Ch1 is demodulated by the comparison / determination unit 707.

Returning to the description of the re-demodulation unit 609 shown in FIG. 10, when the determination result of the comparison determination unit 707 is “1” in the phase shifter 708, the phase of the complex soft-decision demodulated symbol output from the delay unit 702 Is rotated by π / 4, and the comparison determination unit 70
When the determination result of 7 is “0”, the phase of the complex soft-decision demodulated symbol output from delay section 702 is rotated by −π / 4. That is, as can be understood with reference to FIGS. 1B and 1C, the phase of the complex soft-decision demodulation symbol is rotated by the phase shifter 708 so as to be on the in-phase channel Ich axis. Therefore, the output of the phase shifter 708 is
It becomes a demodulated code symbol of channel Ch2.
The delay unit 702 includes a π / 4 phase shifter 703 and -π /
This is a delay unit for compensating a processing delay time from the four-phase shifter 704 to the comparison determination unit 707.

In the 1: 2 selector 709, when the result of the judgment by the comparison / judgment unit 707 is PCB, the demodulated code symbol output from the comparison / judgment unit 707 is output as demodulated data of the channel Ch1-a. FIG.
If the comparison and determination unit 707 determines that the FEC is not added when the data configuration is C shown in (C), the demodulated code symbol output from the comparison and determination unit 707 is the data in the channel Ch1-b. It is output as 1 or data 2 demodulated data. further,
In the 2: 1 selector 710, the demodulated code symbol output from the phase shifter 708 is output as the demodulated code symbol of the channel Ch2, and the demodulated code symbol in the data 3 of the data configuration C output from the comparison / determination unit 707 is: It is selected and output according to the timing sent from the Ch timing setting unit 701.

The decoding section 610 performs serial / parallel conversion on the complex soft-decision demodulated symbols output from the channel synthesis section 608, performs deinterleaving, and further performs Viterbi decoding according to the FEC coding rate. . In addition, deinterleaving is performed on the demodulated code symbol of data 3 in data configuration C output from re-demodulation section 609, and Viterbi decoding is performed according to the FEC coding rate. These decoded data are the decoded data of the channel Ch1-b, the channel C
The decoding unit 610 is divided into decoded data of h2, decoded data of channel Ch3, and decoded data of channel Ch4.
Output from

The operation of re-demodulation section 609 when re-demodulation section 609 has the configuration shown in FIG. 11 will be described.
In the re-demodulation section 609 shown in FIG. 11, the complex soft-decision demodulated symbols input from the channel synthesis section 608 are stored in the delay section 802 and delayed by a predetermined time. The complex soft-decision demodulated symbol input from the channel combining unit 608 is multiplied (I × Q) of the in-phase channel Ich component and the orthogonal channel Qch component of the complex soft-decision demodulated symbol by the I / Q multiplier 803. Then, the positive or negative polarity sign of the multiplication result is output.

Further, the phase of the complex soft-decision demodulated symbol input from channel combining section 608 is
Are shifted in phase. The phase amount in the phase shifter 804 is rotated by π / 4 when the polarity code output from the I / Q multiplier 803 is-, and when the polarity code output from the I / Q multiplier 803 is +. Is rotated by -π / 4 phase. In the phase shifter 803, the absolute value of the complex soft-decision demodulated symbol whose phase has been rotated by π / 4 or -π / 4 according to the polarity code output from the I and Q multipliers 803 is calculated for the in-phase channel Ich component. Alternatively, after being squared to have one polarity, the integral dump unit 805 integrates the data in the channel Ch1 for a period corresponding to one unit cycle, and dumps the data for each unit cycle. The integral dump value immediately before dumping in the integral dump unit 805 is supplied to a comparison / determination unit 806, and the polarity of the integral dump value is determined. Here, when the polarity of the integral dump value in the integral dump unit 806 is +, “1” is output as the determination result, and otherwise, “0” is output as the determination result. This determination result is a demodulated code symbol demodulated on channel Ch1.

In the integral dump performed by the integral dump unit 805, if the frame specification shown in FIG. 3 is used, the complex soft decision demodulated symbol having one polarity is equivalent to the processing gain Gp / 64 symbol of the channel Ch1. The integration and the immediate dumping are the same as in the re-demodulation unit shown in FIG. Also, in the phase shifter 807, when the determination result of the comparison determination unit 806 is “1”, the phase of the complex soft-decision demodulation symbol output from the delay unit 802 is rotated by π / 4, and the determination result of the comparison determination unit 806 is In the case of “0”, the phase of the complex soft-decision demodulated symbol output from delay section 802 is rotated by −π / 4. That is, as can be understood with reference to FIGS. 1B and 1C, the phase of the complex soft-decision demodulated symbol is rotated by the phase shifter 807 so as to be on the in-phase channel Ich axis. Therefore, the phase shifter 80
The output of 7 is a demodulated code symbol of channel Ch2. Note that the delay unit 802 is a delay unit for compensating for a processing delay time from the phase shifter 804 to the comparison determination unit 806.

In the 1: 2 selector 808, when the result of the determination by the comparison / determination section 806 is determined to be PCB, the demodulated code symbol output from the comparison / determination section 806 is output as demodulated data of the channel Ch1-a. FIG.
If the comparison and determination unit 806 determines that the FEC is not added in the case of the data structure C shown in (C), the demodulated code symbol output from the comparison and determination unit 806 is the data in the channel Ch1-b. Output as demodulated data of 1 or data 2. further,
In the 2: 1 selector 809, the demodulated code symbol output from the phase shifter 807 is output as the demodulated code symbol of the channel Ch2, and the demodulated code symbol in the data C of the data configuration C output from the comparison / determination unit 806 is: It is selected and output according to the timing sent from the Ch timing setting unit 801.

Next, FIGS. 12A and 12B show WGN (Whit
e Gaussian Noise) channel Ch1,
Channel Ch2, channel Ch3, channel Ch
4 shows error rate characteristics after demodulation by the re-demodulation unit having the configuration shown in FIG. 10 and the re-demodulation unit shown in FIG.
12A and 12B, the vertical axis represents the bit error rate and the horizontal axis represents the CNR. In FIG. 12A, the processing gain Gp of the channel Ch1 is 64 × 64.
In 2 (b), the processing gain Gp of the channel Ch1 is 64 ×
32. Channel Ch2, Channel Ch
3, the channel Ch4 has a processing gain Gp = 64,
The error rates of the channels Ch3 and Ch4 are set to substantially the same values as the ideal error rates of QPSK since general QPSK demodulation is performed.

The channel Ch shown in FIG.
In 1, the integration period is 64 times as large as one symbol of channel Ch2, channel Ch3, and channel Ch4.
It is greatly improved compared to K. Further, since the integration period of the channel Ch1 shown in FIG. 12B is 32 times as long as one symbol of the channel Ch2, the channel Ch3, and the channel Ch4, also in this case, the error rate is equal to the CNR and the QPSK. It is greatly improved compared to. Further, comparing FIG. 12A and FIG. 12B, the error rate of the channel Ch1 is more improved than that shown in FIG. The error rate of the channel Ch2 is almost 3 dB higher than the error rates of the channels Ch3 and Ch4, and is substantially equal to the error rate of BPSK.

Here, in CNR> 0 dB which is a practical range, the channel Ch1 can be transmitted almost without error. Channel Ch1 and channel Ch2 are Q
Although it is PSK modulation, it is multiplexed by employing the signal point arrangement shown in FIGS. 1B and 1C, and demodulated by the re-demodulation unit having the configuration shown in FIG. 10 or FIG. Can be improved. in this case,
As shown in FIG. 12, the CNR of the re-demodulation unit having the configuration shown in FIG. 10 is slightly higher than that of the re-demodulation unit having the configuration shown in FIG.
Can be improved. Thus, channel Ch1
If a channel requiring high-speed demodulation, such as a PCB, is allocated to the device, highly reliable demodulation can be performed, so that the variation in transmission power controlled by power control can be reduced, and this is effective for near-far problems. Becomes If a channel requiring high reliability is assigned to the channel Ch2, BPSK demodulation is equivalently performed, and higher quality can be obtained as compared to a channel transmitted by QPSK.

[0072]

Since the spread spectrum communication apparatus of the present invention is configured as described above, a plurality of data having different required data quality, transmission rate and transmission delay are transmitted on the same channel. . At this time, the PCB
Such data that requires high-speed demodulation are multiplexed and transmitted to a data channel of high importance. Specifically, while controlling the data period required for the former data, the latter is used to perform QPSK modulation by adaptively changing the constellation of the latter, and when there is data to be transmitted, the parallel QPS by setting the data rate according to the communication channel conditions and the quality required for each data
K modulation is performed, each QPSK modulation symbol is multiplexed in parallel by an orthogonal code, and is directly spread and transmitted by a PN sequence.

On the other hand, on the receiving side, QPSK demodulation is performed on all assigned channels, and re-demodulation is performed on data channels of high importance, which are multiplexed adaptively QPSK-modulated data requiring high-speed demodulation. By doing so, the error rate characteristics are improved as compared with QPSK demodulation. In addition, data requiring high-speed modulation is QP without deinterleaving or error correction processing.
By integrating the SK-demodulated data of high importance by the integration means for a predetermined period, high-speed demodulation can be performed and demodulation can be performed with a small error rate. As described above, a spread spectrum communication apparatus provided with element technologies required for a high-speed data transmission method by CDMA, such as variable data rate transmission and hierarchical transmission of data, according to the quality, transmission rate, and transmission delay required for each channel. can do.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a signal arrangement in a spread spectrum communication apparatus according to the present invention.

FIG. 2 is a diagram showing an example of a data configuration in a spread spectrum communication apparatus according to the present invention.

FIG. 3 is a diagram showing an example of a frame specification in the spread spectrum communication apparatus according to the present invention.

FIG. 4 is a diagram showing a schematic configuration of a transmission unit in the embodiment of the spread spectrum communication apparatus of the present invention.

FIG. 5 is a diagram showing a schematic configuration of a frame generation unit 1 in a transmission unit of the spread spectrum communication apparatus according to the present invention.

FIG. 6 is a diagram showing a schematic configuration of a frame generation unit 2 in a transmission unit of the spread spectrum communication apparatus according to the present invention.

FIG. 7 is a diagram showing a schematic configuration of a modulator 1 in a transmitter of the spread spectrum communication apparatus according to the present invention.

FIG. 8 is a diagram showing a schematic configuration of a modulator 2 in a transmitter of the spread spectrum communication apparatus according to the present invention.

FIG. 9 is a diagram showing a schematic configuration of a receiving unit in the embodiment of the spread spectrum communication apparatus of the present invention.

FIG. 10 is a diagram illustrating a first schematic configuration example of a re-demodulation unit in a reception unit of a spread spectrum communication apparatus according to the present invention.

FIG. 11 is a diagram illustrating a second schematic configuration example of the re-demodulation unit in the reception unit of the spread spectrum communication apparatus according to the present invention.

FIG. 12 is a diagram illustrating an error rate characteristic of the spread spectrum communication apparatus according to the present invention.

FIG. 13 is a diagram showing a conventional data configuration.

[Explanation of symbols]

 101 Frame generator 1 102, 103, 104 Frame generator 2 105 Modulator 1 106, 107 Modulator 2 108, 109, 110 Multiplier 111, 112, 113 Amplifier 114 Adder 115 Spreader 201 Ch timing setting unit 202, 203 input buffer 204 convolutional encoder 205 symbol generator 206 interleaver 207 selector 301 input buffer 302 convolutional encoder 303 symbol generator 304 interleaver 401 AND circuit 402 EXOR circuit 403 QPSK modulator 501 S / P converter 502 QPSK modulator 601 A / D converter 602 Buffer 603 PN generator 604 Despreading unit 605 Orthogonal code generator 606 Inverse orthogonal conversion unit 607 Demodulation unit 608 Channel combining unit 609 Re-demodulation unit 61 0 decoding unit 701 Ch timing setting unit 702 delay unit 703 π / 4 phase shifter 704 −π / 4 phase shifter 705, 706 integral dump unit 707 comparison judgment unit 708 phase shifter 709 1: 2 selector 710 2: 1 selector 801 Ch timing setting section 802 Delay section 803 I, Q multiplier 804 Phase shifter 805 Integral dump section 806 Comparison judgment section 807 Phase shifter 808 1: 2 selector 809 2: 1 selector

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04J 13/04 H04B 1/04 H04B 7/24 H04L 27/18

Claims (6)

(57) [Claims] 1. A communication device for multiplexing low-speed first data and second data faster than the first data and transmitting the multiplexed data on the same channel, wherein the first data is in a period of a first code, The second data is QPSK-modulated by assigning modulation symbols arranged in a first quadrant and a third quadrant in QPSK, and the first data is in a second quadrant in QPSK during a second code period. And QPSK modulation means for performing QPSK modulation by allocating modulation symbols arranged in the fourth quadrant, and spreading modulation means for spreading and modulating the QPSK modulation signal output from the QPSK modulation means. Spread spectrum communication equipment. 2. A communication apparatus for multiplexing low-speed first data and second data faster than the first data and transmitting the multiplexed data on the same channel, wherein a unit cycle of the first data is variable in a burst manner. A unit period setting means that can be set as the first data, and a modulation symbol arranged in a first quadrant and a third quadrant in QPSK is allocated to the second data during the period of the first code, and QPSK modulation is performed. During the period when the first data is the second code, QPSK modulation is performed by assigning modulation symbols arranged in the second quadrant and the fourth quadrant in QPSK to the second data, and the first data does not exist. A QPSK modulating means for allocating modulation symbols arranged in a first quadrant and a third quadrant in QPSK to the second data to perform QPSK modulation; Spread-spectrum communication means for spreading-modulating the QPSK modulated signal. 3. A communication apparatus for multiplexing low-speed first data and second data faster than the first data and transmitting the multiplexed data on the same channel, wherein a unit cycle of the first data is burst-multiplexed in a time-division manner. Unit period setting means that can be set variably, and QPSK by allocating modulation symbols arranged in the first quadrant and the third quadrant in QPSK to the second data during the period when the first data is the first code. And performing QPSK modulation by assigning modulation symbols arranged in a second quadrant and a fourth quadrant in QPSK to the second data while the first data is in a second code period. When there is no QPSK modulation means for allocating modulation symbols arranged in the first quadrant and the third quadrant in QPSK to the second data to perform QPSK modulation, And a spread-spectrum modulating means for spread-modulating the QPSK-modulated signal output from the MS. 4. The method according to claim 1, wherein the low-speed first data is in a period of a first code,
The modulation symbols arranged in the first quadrant and the third quadrant in QPSK are allocated to the second data faster than the first data, and QPSK modulation is performed. Are assigned modulation symbols arranged in the second and fourth quadrants of QPSK.
A first QPSK modulating means for performing modulation; and a second QPSK modulating means provided for each data to perform QPSK modulation at another data to be transmitted at a data rate set for each data.
QPSK modulating means, the first QPSK modulating means and the second QPSK
In each QPSK modulation symbol sequence output from the modulation means,
Multiplexing means for performing multiplexing by multiplying and adding orthogonal codes which are orthogonal to each other, and spreading modulation means for directly spreading a multiplexed signal output from the multiplexing means with a spreading sequence, A spread spectrum communication apparatus, comprising: 5. A period in which low-speed first data is a first code,
Modulation symbols arranged in the first quadrant and the third quadrant in QPSK are allocated to second data faster than the first data, and the second data is allocated to the second data in QPSK during the period of the second code. A spread spectrum communication apparatus comprising demodulating means for demodulating the first data and the second data from a QPSK modulated signal on which QPSK modulation is performed by allocating modulation symbols arranged in two quadrants and a fourth quadrant. QPSK demodulating means for QPSK demodulating the QPSK modulated signal; phase means for rotating the demodulated symbols output from the QPSK demodulating means by π / 4 and -π / 4, respectively; The in-phase channel components having one polarity in the two demodulated symbols are respectively integrated over one unit period of the first data. And comparing the respective integrated values integrated by the integrating means. When the integrated value in the demodulated symbol rotated by π / 4 is large, the first data is determined to be the first sign, and -π
When the integral value of the demodulated symbol rotated by / 4 is larger, the first data is determined to be the second code, and the first data is output as the demodulated data of the first data. During the period in which the value of the first data is determined to be the first code by the first data demodulating means, the phase of the demodulated symbol output from the QPSK demodulating section is rotated by π / 4, The value of the first data is the second
The second data demodulation outputs the signal of the in-phase channel component as the demodulated data of the second data by rotating the phase of the demodulated symbol output from the QPSK demodulation section by -π / 4 during the period determined as A spread spectrum communication apparatus, comprising: 6. A period in which low-speed first data is a first code,
Modulation symbols arranged in the first quadrant and the third quadrant in QPSK are allocated to second data faster than the first data, and the second data is allocated to the second data in QPSK during the period of the second code. A spread spectrum communication apparatus comprising demodulating means for demodulating the first data and the second data from a QPSK modulated signal on which QPSK modulation is performed by allocating modulation symbols arranged in two quadrants and a fourth quadrant. QPSK demodulating means for performing QPSK demodulation on the QPSK modulated signal; and, if the code obtained by multiplying the demodulated symbol demodulated by the QPSK demodulating means by the in-phase channel component and the quadrature channel component has the first polarity, The phase of the demodulated symbol is rotated by π / 4 and the sign of the result of multiplication is
In the case of the second polarity, the phase of the demodulated symbol is -π / 4
A phase rotating means for rotating; a polarity of the in-phase channel component of the demodulated symbol rotated by the phase rotating means as one polarity; an integrating means for integrating over a unit cycle of the first data; When the integration result has the first polarity, the first data is determined to be the first sign, and when the integration result by the integration means has the second polarity, the first data is determined to be the second sign. A first data demodulating means for outputting the code as demodulated data of the first data; and a period in which the value of the first data is determined to be the first code by the first data demodulating means. The phase of the demodulated symbol output from the demodulation unit is rotated by π / 4, and the first data demodulation means sets the value of the first data to the
The second data demodulation outputs the signal of the in-phase channel after the phase of the demodulated symbol output from the QPSK demodulation section is rotated by -π / 4 as the demodulated data of the second data during the period determined as A spread spectrum communication apparatus, comprising: