JP2858190B2 - Parallel processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing system for dividing a set of data processing into a plurality of processors (hereinafter referred to as "processor elements") for parallel processing.

[0002]

2. Description of the Related Art A parallel processing system is a system for processing an enormous amount of signal processing such as acoustic signal processing and image signal processing at a high speed, and various parallel processing systems have been proposed.

For example, in a parallel data processing apparatus described in Japanese Patent Application Laid-Open No. 63-240667, a plurality of processor elements are arranged in a matrix, and processor elements adjacent in the vertical and horizontal directions are assigned to each processor element. It is connected via a data transfer unit having four sets of input / output lines provided, enabling data transmission / reception with up to four processor elements connected to the data transfer unit, and inputting data. , And can be transferred to another processor element.

Further, according to the data communication system of a parallel computer described in Japanese Patent Application Laid-Open No. 3-127251, four independent communication ports or communication channels are provided for each processor element, and adjacent processor Elements can be connected to each other to enable data transmission / reception to and from the processor element connected to each communication port, and any two communication ports of one processor element can be directly connected. The data transfer between the other two processor elements is directly passed (through) without performing the relay processing.

However, according to the data transfer unit or the communication port of the system described in the above two publications, data transmission and reception and relay (or through relay) cannot be performed at the same time, so that processing efficiency is poor.

In the parallel processing system described in Japanese Patent Laid-Open Publication No. Hei 1-320564, four communication ports are connected to an internal system bus of each processor element, and each communication port is connected to another communication port via an external communication line. There has been proposed a configuration in which processor elements are connected to each other, and external communication lines connected to adjacent communication ports can be connected via a bypass switch. According to this, while transmitting / receiving data via two adjacent communication ports and closing the bypass switch between the remaining two adjacent communication ports, data through relay can be performed at the same time.

[0007]

However, Japanese Patent Application Laid-Open No. Hei.
According to the parallel processing system described in JP-A-205564, when transmission or reception is performed with another processor element connected to two non-adjacent communication ports, the processor is connected to the remaining two non-adjacent communication ports. However, there is a problem that the through relay cannot be performed between the other processor elements. In other words, when trying to relay data through between two non-adjacent communication ports, the data passes through the external communication line of the communication port between them, and three communication ports are used for through relay. Because.

For the same reason, while performing through relay between processor elements connected to two non-adjacent communication ports, communication between other processor elements connected to the remaining two non-adjacent communication ports is performed. Through relay cannot be performed.

Therefore, the configuration of the parallel processing system can be changed within a certain range, but the degree of freedom of the change is not sufficient, and the content of data processing that can be processed in parallel is limited, or the speed of processing is limited. There is.

Further, the prior art does not consider how to deal with a failure of a processor element. Therefore, if even one of the processor elements fails, the operation of the entire system cannot be guaranteed.

Further, since the number of communication ports connecting each processor element is fixed to four, the number of pipeline processing stages that can be processed may be limited.

In general, each processor element executes a processing program by dividing it into several processing units such as steps, but conventionally, the processing time for executing the processing unit and the data transfer time are coordinated. Since this is not taken into account, there is a case where a dead time is generated, and there is a problem that the processing speed is not sufficiently high.

A first object of the present invention is to provide a parallel processing system in which transmission / reception and through relay can be performed at the same time between arbitrary processor elements of a plurality of processor elements connected to the processor element. It is in.

A second object of the present invention is to provide a parallel processing system capable of continuing processing even if a processor element fails, in addition to the first object.

It is a third object of the present invention to provide a parallel processing system capable of performing more multi-stage pipeline processing in addition to the first object.

Further, a fourth object of the present invention is to provide a parallel processing system which can further increase the processing speed in addition to the first object.

[0017]

In order to achieve the above first object, a first aspect of the present invention is to provide a multiprocessor system comprising a processor, a memory and a plurality of communication channels connected by an internal system bus. Parallel processing in which each of the processor elements is mutually connected to a predetermined number of other processor elements via a communication channel, and a group of data processing is shared and executed by each of the processor elements according to a command given from a management processor. In the system, the processor element has a plurality of bypass buses that can commonly connect a plurality of communication channels belonging to the processor element, and each of the communication channels connects another processor element connected to the communication channel to the internal system bus. Or connect to one of the bypass buses Characterized in that it comprises a channel mode switching means for.

In this case, the channel mode switching means can switch according to a channel mode command given from the management processor.

Further, the management processor can switch the channel mode switching means of each communication channel to transmit processing data of the processor element to which the communication channel belongs to a plurality of other processor elements.

Further, the management processor switches channel mode switching means of each communication channel, and external data inputted from an external processor element to one communication channel is transmitted to another communication channel via a bypass bus and another plurality of communication channels. Can be simultaneously passed through a plurality of external processor elements.

The management processor includes a configuration management means for managing a connection state between an interface communication line connecting a plurality of processor elements and a communication channel;
A communication channel mode setting unit that determines a mode of each communication channel based on the processing sharing of each processor element and outputs a channel mode command to each processor element based on the determination.

It is preferable that the management processor outputs a processing start command to all processor elements after setting all communication channel modes by the communication channel mode setting means.

Further, the management processor changes and sets the necessary communication channel mode by the communication channel mode setting means in accordance with the end of the processing unit constituting the data processing or the end of the data transfer, whichever is later. can do.

According to a second aspect of the present invention, in order to achieve the second object, in addition to the first aspect, the management processor has a monitoring means for monitoring the operation state of the processor element, and the monitoring means Reconfiguring means for disconnecting the processor element in which the operation abnormality is detected and reconfiguring the processor element group for performing data processing, wherein the communication channel mode setting means sets the mode of each communication channel in accordance with the determination of the reconfiguration means. And a channel mode command is output to each processor element based on the change.

In the first and second inventions, the channel mode switching means includes a first switching means for connecting another processor element to one of the internal system bus and the through signal line, and a through signal line. And a second switching means for selectively connecting to one of the bypass buses.

In order to achieve the third object, the third invention of the present invention is the invention according to the first or second invention, wherein eight communication channels of the processor element are provided and each communication channel is shared. Eight connectable bypass buses are provided, a plurality of processor elements are arranged in a matrix, and adjacent processor elements in the vertical, horizontal, and diagonal directions of the matrix are connected to each other in a torus shape via a communication channel. It is characterized by.

In order to achieve the fourth object, a fourth invention of the present invention is to form a plurality of processor elements by connecting a processor, a memory, and a plurality of communication channels by an internal system bus. Assigning a plurality of processing programs for performing a group of data processing to each processor element, transferring the processing program to the memory of the corresponding processor element in accordance with the assignment, and managing the processor element group to generate a plurality of processing programs. And a synchronizing signal generator for simultaneously providing all processor elements with a synchronizing signal for controlling the start timing of a processing unit constituting the processing program. Processor element It has a plurality of bypass buses that can commonly connect a plurality of communication channels belonging thereto, and is mutually connected to a predetermined number of other processor elements via communication channels, and each of the communication channels is connected to the communication channel. Channel mode switching means for connecting another processor element to the internal system bus or one of the bypass buses, wherein the management processor transmits / receives data to / from each processor element according to the assignment of the processing program and the transmission route thereof. Is determined, and a channel mode command for each communication channel is output to each channel mode switching means in accordance with the determination, and the channel mode switching means performs a switching operation in accordance with the channel mode command.

In this case, it is preferable that the period of the synchronization signal is set to be longer than the sum of the processing time of the processing unit of the processor element and the time required for the switching operation of the channel mode switching means.

Further, it is preferable that the processing unit amount of the processor element group and the data transfer amount accompanying the processing are unified, and the period of the synchronization signal is set based on the unified amount.

[0030]

According to the present invention, the above object can be achieved by the following operation.

That is, according to the first aspect, since there are a plurality of bypass buses which can connect a plurality of communication channels in common, two communication channels related to one through relay are connected to one bypass path, and 2 to relay through
By connecting one communication channel to another bypass bus, a plurality of through relays between arbitrary processor elements can be performed at the same time. In addition, by connecting the other processor element to the internal system bus, transmission or reception can be performed at the same time without any limitation of another through relay.

According to the configuration in which the management processor issues a command to each processor element to switch the connection state of each communication channel, the parallel system configuration of the processor element group can be freely and promptly changed according to the contents of the processing program. Can be built.

Further, since a plurality of communication channels of one processor element can be connected to the internal system bus and set to the transmission mode by the management processor, the transmission mode can be set and the throughput can be reduced. Similarly, by setting a communication channel, transfer data from one processor element can be transmitted to a plurality of other processor elements at the same time.

According to the configuration in which the management processor is provided with the configuration management means for managing the connection state of the system, the processing allocation of each processor element is determined according to the contents of the data processing, and based on the determination, the communication channel of each communication channel is determined. By setting the mode, a parallel processing system can be automatically constructed according to the contents of data processing. That is, since the connection configuration between the individual processor elements and the processing program in the processor element can be changed at the same time, the contents of the data processing that can be realized in the limited hardware configuration are determined, and the system Can be quickly reconstructed.

In addition, the processing operation of each processor element is synchronized, and the mode of the necessary communication channel is changed by the management processor according to the end of the processing unit constituting the data processing or the end of the data transfer, whichever is later. According to the setting, an optimal parallel processing system can be constructed according to a processing unit for each phase constituting a group of data processing, and an optimal high-speed processing can be performed according to the content of the data processing. Can build a system.

According to the second aspect of the present invention, the processor element in which the operation abnormality is detected by the processor element monitoring means is separated by the reconfiguration means and the processor element group is reconfigured. Even if a failure occurs in a part of the element group, data processing can be continued, and a highly reliable system can be provided.

According to the third aspect of the present invention, according to the parallel processing system in which eight communication channels of processor elements are provided and the processor elements arranged in a matrix are connected vertically, horizontally and diagonally, Since the degree of freedom of the connection configuration is improved, more complicated data processing including multi-stage processing can be performed by the processor element group of a limited scale.

For example, when an acoustic simulation composed of a plurality of sound sources or a complicated image processing is performed at high speed and with high quality, the amount of data for signal processing and the amount of parameters for calculation increase, so that Since it is necessary to improve the throughput, it is necessary to take measures such as increasing the number of stages of parallel processing. In such a case, according to the present invention, a plurality of basic processing programs necessary for signal processing are prepared in advance, and the direction of data transfer between processor elements in accordance with the change of the program is determined. By changing them all at once, it is possible to quickly change the signal processing content of the entire system.

According to the fourth aspect of the present invention, since the processing operation of each processor element is performed in synchronization with the same synchronization signal, the overhead time can be reduced and the throughput can be improved.

In particular, when the period of the synchronization signal is set to be longer than the sum of the processing time of the processing unit of the processor element and the time required for the switching operation of the channel mode switching means, the parallel processing is performed for each processing unit. Since the configuration of the system can be changed, it is possible to construct a system that can further increase the processing speed by using processor elements of a limited scale.

Further, the throughput can be further improved by unifying the processing unit amount of the processor element group and the data transfer amount accompanying the processing and setting the period of the synchronization signal based on the unified amount. .

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the illustrated embodiments.

FIGS. 1 to 5 show configuration diagrams of a parallel processing system according to an embodiment of the present invention. FIG. 1 is a configuration diagram of a communication channel which is one of the main parts of the present invention and a portion related to its control. FIG. 2 is a basic configuration diagram showing the entire parallel processing system. FIG. 3 is a configuration diagram of one processor element configuring the parallel processing system. FIG. 4 is a configuration diagram of a management processor that manages the entire parallel processing system. FIG. 5 is a configuration diagram of a synchronization signal generator that controls the timing of the processing operation of the processor element.

As shown in FIG. 2, the basic configuration of the parallel processing system includes an input device 1, a processor element group 2 including a plurality of processor elements PE, and an output device 3.
, A management processor 4, and a synchronization signal generator 5.

The processor element group 2 stores a plurality of processor elements PE as m (m = 1, 2,..., X)
Arranged in a matrix of rows and n (n = 1, 2,..., Y) columns, the processor elements PEmn adjacent in the horizontal (row) direction, the column (vertical) direction, and the oblique direction are interconnected by an interface communication line 6 for connection. In this embodiment, the processor elements PE arranged on the outer periphery are connected only to the processor elements PE arranged inside the matrix. However, the present invention is not limited to this, and a plurality of processor elements PE (PE11,.
1y, PEx1,..., PExy) as adjacent ones,
They can be connected in the vertical and diagonal directions to form a torus. For example, PEx1 and PEx2 are connected to PE11.

The input device 1 is a device for digitizing data to be processed by the plurality of processor elements PEmn. In this embodiment, the input device 1 is connected to the first row of processor elements PE11 to PEx1 via the input interface 7. ing. The output device 3 is connected to the processor elements PE1y to PExy in the y-th column via the output interface 8. The output device 3 outputs data processed in parallel by the processor element group 2 as digital or analog signals. The management processor 4 manages the entire system including the input device 1 and the processor element group 2, and sequentially outputs the operation conditions as control parameters to the respective processor elements PEmn via the interface 9. . In addition, the synchronization signal generator 5
A synchronization signal 11 for controlling the timing of the processing operation of the processor element group 2 is generated in response to a command given from the management processor 4 via the interface 10.
The synchronization signal 11 is provided to each processor element PEmn via an interface. The processor element group 2 starts processing in response to the synchronization signal 11, ends one phase (processing unit) of data processing within the cycle of the synchronization signal 11, and repeats the processing. Each processor element PEmn is responsible for parallel processing among the data processing of the entire device, and processes and processes data received from the input device 1 to perform communication processing.
Through the next stage or peripheral processor element PE
Transfer to The final processing result is output from the output device 4.

Next, the detailed configuration of each device will be described. Each processor element PEmn is configured identically,
FIG. 3 shows the block configuration, and FIG. 1 shows a detailed configuration diagram focusing on the communication channel. As shown in FIG. 3, the processor element PE is divided into three blocks of a signal processing unit 20, a control unit 30, and a communication unit 40, each of which is surrounded by a broken line, and these are connected by an internal system bus 50. I have. The signal processing unit 20 includes a signal processor 21, an instruction memory 22, and a data storage 23. Control unit 30
Is a control processor 31, a channel mode setting register 32, a channel status register 33,
And an E status register 34.
The communication unit 40 includes up to eight communication channels CH1 to CH8.
And eight sets of bypass buses 42.
Each communication channel CH has the same configuration,
This is a unidirectional communication channel that can be preset for reception or through relay. Therefore, each processor element PE has a maximum of eight communication channels, is capable of performing completely parallel processing by the torus coupling method, and is generally capable of forming various connection states according to the processing contents of the entire system. it can.

The signal processor 21 is responsible for part of data processing performed by the entire processor element group 2, that is, part of pipeline processing. This assignment is performed by the management processor 4.

The control processor 31 includes the management processor 4
Is a processor dedicated to control for receiving instructions from the processor element PE and controlling the entire processor element PE. Therefore, the control processor 31 is connected to the management processor 4 by the interface 9, and receives the synchronization signal 11 from the synchronization signal generator 5. For example, the control processor 31 issues a start / stop command 2 to the signal processor 21 according to a command from the management processor 4.
4 is output to the instruction memory 22 as a storage instruction 25 of a signal processing program for the signal processor 21. Further, it reports the internal status of the processor element PE to the management processor 4. In addition, various settings and the like for the communication channels CH1 to CH8 are performed in the channel mode register 32 according to a command from the management processor 4.

The channel mode setting register 32 stores each communication channel CH1 according to an instruction from the management processor 4.
Operation modes (hereinafter abbreviated as channel modes) of communication channels Nos. To 8 are set. Transmit in channel mode,
There is reception or through relay. The channel status register 33 stores the setting state of the channel mode for transmission, reception, and through relay set for the communication channels CH1 to CH8. In the partner PE status register 34, the setting state of the channel mode of the partner side for each communication channel (the setting state of transmission, reception or through relay) is sequentially recorded. The information stored in the partner PE status register 34 is transferred to the management processor 4 by the control processor 31.

The communication channels CH1 to CH8 have the same configuration, and are configured like the communication channels CH1 and CH2 illustrated in FIG. As shown, each communication channel CH
Are buffer memories 42A, b switched by the switching means 41A, 41B, transfer means 44,
It includes transmission / reception / through switching means 45, partner PE status monitoring means 46, and bypass bus switching means 47. Two buffer memories 42A,
42B is selectively connected to the internal system bus 50 by switching the switching means 41A, and is selectively connected to the transfer means 44 by the switching means 41B. The transfer means 44 is a processor element PE
This is a mechanism for transmitting / receiving data to / from the server. The transmission / reception / through switching unit 45 connects the external communication line 6 to the transfer unit 44 in the transmission / reception mode and switches to the through communication line 48 in the through relay mode according to the setting contents of the channel mode setting register 32. .
The bypass bus switching means 47 supplies the through communication line 4 in accordance with the setting contents of the channel mode setting register 32.
8 can be connected to one of the bypass buses 42a to 42h.

The transfer means 44, the transmission / reception / through switching means 45, and the bypass bus switching means 47 each take in the channel mode set in the channel mode setting register 32 via the signal line 51, and perform their operations or switching. It has become. The operating states of the transfer means 44, the transmission / reception / through switching means 45, and the bypass bus switching means 47 are stored in the channel mode status register 33 via the signal line 52. The setting of the channel mode in the channel mode setting register 32 is set to transmission, reception, or through relay before the processing operation of the signal processor 21 starts. Then, the data transfer is started after the processing is started by activation from the signal processor 21. The buffer memories 42A and 42B are replacement buffer memories. By using these replacement buffer memories 42A and 42B as communication buffers, access to the system bus 50 of the signal processor 21 and data transfer between the partner processor elements PE for each communication channel CH are performed in parallel. I have. Further, as described later, it is set that the processing time of one phase by the signal processor 21 and the data transfer time of the communication channel CH are completed within one cycle of the synchronization signal generated by the synchronization signal generator 3. is there. This eliminates the overhead of the processing time of the signal processor 21 and the data transfer time of the transfer means 44.

The partner PE status monitoring means 46 detects the identification number of the partner PE connected to the communication channel CH via the external communication line 6 and stores it in the partner PE status register 34 via the signal line 53. This stored information is transmitted to the management processor 4 via the control processor 31.

The management processor 4 is configured as shown in FIG. The CPU 61 is a central processing unit that controls processing in the management processor 4. The program download storage device 62 is a storage device for downloading a processing program to each processor element PEmn of the processor element group 2, and stores various programs necessary for data processing. Main memory 63
The PE status monitoring program 63A in the P includes P which is set for all of the processor elements PEmn.
E connection state and each processor element PEmn
And the setting state of the channel mode of the communication channel CH of
The data is fetched from the reception channel 64 via the interface 9 and stored. The CPU 61 grasps the connection state between the PEs and the setting state of the communication channels CH1 to CH8 of each processor element PEmn by using the PE status monitoring program, and can determine a data processing program executable as the whole system. . If a failure occurs in any of the processor elements PE, the abnormality is reflected, and it is determined whether the hardware is normal or abnormal for all the processor elements PEmn. The control command generation program 63C is for generating an instruction for controlling the processor element PEmn. The instructions to be generated are roughly divided into individual processor elements PE.
mn and an instruction for issuing a command to the entire processor element group 2 all at once. The former includes a channel mode setting instruction (a transmission, reception, through relay setting instruction) for a communication channel CH inside the processor element PE, a signal processing program download instruction instruction to the processor element PE, and a synchronization from the synchronization signal generator 3. There is a synchronization signal valid / invalid command for determining whether or not to accept the signal 11. The synchronization signal control unit 66 starts / stops the synchronization signal generator 3 and sets the cycle of the synchronization signal 11. These instructions and the like are transferred to each processor element PEmn via the transmission channel 65. FIG.
3 is an internal block diagram of the synchronization signal generator 3. FIG. The synchronization signal generator 3 operates according to a start / stop command and a cycle setting control command input from the management processor 4 to the programmable timer 72. That is, the clock signal from the oscillator 71 is frequency-divided by the programmable timer 72 to generate and generate a synchronization signal having a set cycle. The synchronization signal 11 actually output to each processor element PEmn is a signal common to all the processor elements and has a large load. Therefore, the power is amplified using the driver 73 and output.

Here, the procedure for setting or changing the connection configuration of each processor element PEmn of the processor element group 2 to construct or reconstruct a parallel processing system according to the type and content of data processing will be described with reference to FIGS. 10
This will be described with reference to FIG.

The construction or reconstruction of the parallel processing system is performed by the function of the management processor 4. First, the management processor 4 has PE array information (information of x rows × y columns), which is the basic configuration of the processor element group 2, and the position or identification number of the processor element PE to which the input device 1 and the output device 3 are connected. Is input.

The CPU 61 of the management processor 4 performs initial processing according to the procedure shown in FIG. 6 when starting up the system.

<Step 101> For all processor elements PEmn, it is checked whether or not they operate normally, and it is confirmed that all are operable.

<Step 102> Signal processing type recognition processing is performed according to the procedure of the signal processing type recognition program 63B shown in FIG. First, a task number is assigned to a plurality of signal processes to be executed, and thereafter, the type of the signal process is recognized based on the task number (step 111). Next, based on the current configuration scale of the processor element group 2, a connection between the processor elements is established to execute a desired signal processing algorithm (for example, contents obtained by dividing a set of signal processing into several processing blocks). Is determined (step 112). If the scale is not appropriate, it is output that a processor element needs to be added, and the process ends. If it is determined that the scale is appropriate, the process returns to the processing in FIG.

<Step 103> Here, according to the processing procedure of FIG. 8, the connection mode is set by setting the channel mode of the communication channel CH between the processor elements. First, processor elements PEmn are sequentially allocated to the above signal processing blocks in accordance with the flow of data (step 121). Next, if there is one that transmits and receives data between adjacent processor elements PE,
The connection mode is set by setting the channel mode of those communication channels CH to transmission or reception (step 122). Next, when it is necessary to transfer data through another processor element for the reason that the processor elements PE which transmit and receive data are not adjacent to each other, a route that can transfer data over a short distance is searched for. The channel mode of the communication channel CH of the processor element PE to be set is set to the through relay mode, and the processor elements PE involved in data transfer are connected (step 12).
3). Next, it is determined whether there is an unconnected processor element PE to which a necessary connection has not been made (step 12).
4). If there is an unconnected one, while changing the route of the through relay of the processor element PE already set,
Unconnected processor elements PE are eliminated (step 125). If there is no unconnected processor element, the process is terminated. If there is no unconnected processor element PE even if the route of the through relay is changed, the process proceeds to step 127, where the processor element PEmn for the signal processing block is The assignment is changed, and the process returns to step 122 to repeat the process (step 126).

By the above steps 101 to 103,
The management processor 4 determines the channel mode of the plurality of communication channels CH of each processor element PE so that the connection of the processor element group 2 can be established in correspondence with the plurality of signal processes executed by the parallel processing system.

<Step 104> According to the channel mode of each communication channel CH determined in step 103,
The control command generation program 63C processes the channel mode control command for setting each communication channel of each processor element PE and stores it in the memory.

<Step 105> A channel mode control command for setting each communication channel is transmitted from the transmission channel 64 to each processor element PE via the interface 9. This channel mode control command is transmitted in correspondence with the task number.

<Step 106> The control processor 31 of each processor element PE determines whether or not the input channel mode control command is for its own processor element PE, and if it is a command for its own processor element PE. The channel mode control command is stored in the memory in correspondence with each task number. Then, the channel mode corresponding to the task number currently being processed is written in the channel mode setting register 32 on the internal system bus 50 for information of a predetermined channel.

As a result, transmission / reception / through switching means 45 for each communication channel CH and bypass switching means 4
7. The setting state of the transfer means 44 is switched.

For example, in the example shown in FIG. 1, the communication channel CH1 in the processor element PE is set in the transmission or reception state in accordance with the contents written in the channel mode setting register 32, and the communication channel CH1 is set in the transmission or reception state.
The switching signal 45 is provided by the interface signal line 6 with E54.
Is connected to the transfer means 44. Also, when passing the data received from the partner PE to another channel,
Like the communication channel CH2 in FIG. 1, the interface signal line 6 with the partner PE 55 is connected to the through signal line 48 by the switching means 45 in accordance with the setting state of the channel mode setting register 32.
Is connected to a predetermined bus of the bypass bus 42 (the bus 42b in this example) by the bypass switch switching means 47 controlled by the control processor 31. Thus, all the processor elements P required for signal processing are
Each of the communication channels CH1 to CH8 in the E
Is set to one of the transmission, reception, and through relay states.

As described above, according to this embodiment, the management processor 4 automatically configures a parallel processing system capable of realizing the processing according to the task number of the data processing.

<Step 107> Next, the management processor 4 transfers the processing program to be executed to each processor element PE and downloads it to the instruction memory 22.

After the parallel processing system is constructed and a predetermined processing program is downloaded to each processor element, the management processor 4 sends the synchronization signal to the synchronization signal generator 5 in accordance with the procedure shown in FIG. And a start command is output to start the parallel processing system.

FIG. 9 shows a procedure of an embodiment of a method of setting the period of the synchronization signal. First, steps 201 and 202
Then, a preset buffer capacity N (word) of the input / output devices 1 and 3 and a target frequency characteristic fm (Hz) are fetched. This buffer capacity N is the same as the capacity of the buffer memory 42 of the communication channel CH. Next, step 20
3, the sampling frequency fs of one word of the transfer data
Is calculated so as to satisfy the condition of fs> 2 × fm. Then, the period T of the synchronization signal required to sample N words is calculated by T = N / fs. Then, in step 205, it is determined whether or not the cycle T is equal to or less than the maximum processing time of the processing time of one phase by each processor element PE. If the period T is equal to or longer than the maximum processing time, the construction of the parallel processing system is changed in step 206 to distribute the load. After determining the cycle T of the synchronization signal in this manner, the synchronization signal is output to the synchronization signal generator 5 and a start command is output.

Thus, a synchronization signal common to each processor element PEmn is output from the synchronization signal generator 5 all at once. Then, each processor element PEm
n performs data processing and data transfer according to the synchronization signal. Therefore, each processor element P
The data transfer amount and data transfer speed of Emn are unified. In addition to unifying the size of one phase (processing unit), high-speed processing can be performed with less processing time required for data processing and transfer processing.

FIG. 10 shows a sampling process of an input signal input from the input device 1 which is executed based on a synchronization signal.
4 shows a timing chart of a process of taking in a processor element PE, performing signal processing, and transferring processing data to a processor element PE of the next stage. In this embodiment, since the buffer memories 42A and 42B are used alternately for each communication channel CH, as shown in the figure, the input signal (c) is generated at a timing corresponding to the speed of the sampling clock (b). Since the data is encoded and constantly written to one of the buffer memories 42A and 42B, no data is lost. For example, the data A of the buffer memory 42A taken in the cycle period S ₀ as shown in (d) is switched to the buffer memory 42B in S ₁ of the cycle (e), the shown (f) As described above, the access is performed at a timing corresponding to the operation speed of the processor element PE. The accessed data A is processed into data A '. Then, is transferred via the buffer memory 42 of another communication channel CH the transfer destination processor element PE is connected during the cycle S ₂ as shown in (g).

Further, one data transfer is set to end in a time shorter than the period T of the synchronization signal, and as shown in FIG. If the time t is provided, the control processor 3
1 to change the channel mode of each communication channel CH. Therefore, even while online, the configuration of the parallel processing system can be changed by changing the communication mode between the processor elements PE. In addition, the system configuration can be changed without affecting sampling of input signals of each processor element PE, signal processing, and data transfer.

Incidentally, the management processor 4 grasps the state of the processor element PEmn constituting the system as described in step 101 of FIG.
The state of each processor element PE and the state of the communication channel CH are constantly monitored by the control processor 31, and the normal / abnormal state is sequentially transmitted to the management processor 4. Then, a change from the initial state is constantly monitored according to the PE status monitoring program 63A of the management processor 4. Therefore, an abnormality of each processor element PEmn can be detected from the monitoring result. When an abnormality is detected, the abnormal processor element is disconnected from the system, and the parallel processing system is reconfigured according to the processing procedure shown in FIG. 6 so that the system can be quickly restarted to perform data processing. Can be.

As described above, according to the present embodiment, the remaining arbitrary communication channels are transmitted or received at the same time between the processor elements PE connected to the eight communication channels CH1 to CH8. Since the through relay can be performed between the channels, the degree of freedom in selecting the route of the through relay can be increased. As a result, since the degree of freedom of the configuration of the parallel processing system can be sufficiently increased, the applicable range of the data processing can be expanded and the processing speed of the data processing can be increased as compared with a parallel processing system having the same number of processor elements PE. Speed can be increased.

Here, the point that the degree of freedom of the route selection of the through relay can be increased is described in the above-mentioned JP-A-Hei 1-3205.
A description will be given in comparison with the system of JP-A-64. FIG.
(A) and (B) are schematic diagrams each showing one operation state of the processor element described in the publication. As shown, the processor element is a CPU / memory 81
Physically, four communication ports 82a to 82d are bus-connected, and adjacent external communication lines a to d connected to each communication port are connected by bypass switches 83a to 83d. By closing the bypass switch 83, data can be relayed through between the two external communication lines. However, as shown in FIG. 3A, in a mode in which data is input from the external communication line b and output from the external communication line d, it is possible to through-relay data from the external communication line a to the external communication line c. Can not. Similarly, as shown in (B), external communication lines a to c
Also, the through relay from the external communication lines c to d cannot be performed at the same time. In this regard, according to the present invention, as shown in FIG. 1, the communication channels CH1 to CH8 can independently form through routes via the bypass buses 42.1 to 8 respectively. At the same time, transmission / reception and through relay can be performed.

According to the present invention, the communication channel CH
1 to 8 are independent of each other and can set a channel mode for each, so that the same data can be transmitted to a plurality of processor elements at the same time, and the transferred data can be relayed through to a plurality of processor elements. .

Next, FIGS. 12 to 16 show an embodiment of a specific device structure of the parallel processing system of the present invention. The management processor 4 shown in FIG. 4 can be realized by a general-purpose computer system, and the synchronization signal generator 3 shown in FIG.
It can be easily composed of C or the like. In the present invention, the most important part in hardware is the configuration inside the processor element PE and the configuration between the processor elements PE.
Therefore, an embodiment of the device structure of the processor element group 2 will be described. FIG. 12 is a physical external view in the case where the processor element group 2 is entirely constituted by discrete components such as a general-purpose signal processor, a microprocessor, and a general-purpose IC. One processor element PE has one unit configuration. The signal processing unit 20 and the control unit 30 indicated by broken lines in FIG. 3 are a signal processor board 413 and a control processor board 412 in FIG. The communication unit 40 in FIG. 3 combines two communication channels into a single printed circuit board due to hardware physical restrictions, and includes a communication channel board a414, a communication channel board b415, a communication channel board c416, and a communication channel board d41.
7 are formed. They are all of the same construction. The control processor board 412 is provided with a connector 419 for connecting an interface signal line 445 to the management processor 4 and a connector 418 for connecting an interface signal line 446 to the synchronization signal generator 3. From the communication channel board a414 to the communication channel board d417, other processor elements PE
And connectors 420 to 427 for connecting the interface signal line group 442 to the interface. These printed circuit boards make connections on the system bus 50 for the signal processor shown in FIG. The connection on the bypass bus 42 is made by the back board 411 shown in FIG. The back board 411 connects the respective boards by a board connection connector group 431. Power supply board 4
Numeral 11 supplies power to all the printed circuit boards via the back board 411.

FIG. 14 shows a part of a custom L for the purpose of increasing the operating speed of the hardware and miniaturizing it.
FIG. 3 shows a block diagram of the inside of the processor element PE when the SI is implemented. The hardware configuration of the processor element PE is the same as that shown in FIG. 3 for the signal processing unit 20 indicated by a broken line, but the control unit 30 is only a control processor (general-purpose microprocessor) 32 and the channel mode of the control unit 30 The setting register 32, the channel status register 33, the partner PE status register 34, and the communication unit 40 are integrated into a control / communication LSI 451 as one chip. Thereby, the hardware amount of the processor element PE can be significantly reduced as compared with the case of FIG. FIGS. 15A and 15B show that one processor element PE is made into one board and the printed circuit board is made up of four boards.
Multi-processor element P when mounting is possible
It is a physical appearance figure of an E unit. Backboard 466
Has an interface signal line 483 with the management processor 4
And a connector 468 for connecting an interface signal line 484 to the synchronization signal generator 3. From the processor element PE board a 462 to the communication channel board d 465, an interface signal line group 491 for connecting to another processor element PE (5 per interface, total 20)
Is provided with a connector group 471 for connecting the.
These printed circuit boards are connected on the internal system bus 50 for the signal processor and the connection on the bypass bus 42 shown in FIG. 1, and the connection between the communication channels of the processor element PE boards a462 to d465 is shown in FIG. ) Is performed by the back board 466 shown in FIG. The back board 466 connects the boards with each other via a board connector group. Power supply board 461
Supplies power to all of these printed circuit boards via the back board 466. With this hardware configuration, the connection between the four processor elements PE can be realized on the backboard in the same unit, so that the data transfer between the processor elements PE inside the unit is performed by the data transfer with the processor element PE outside the unit. Higher speed can be achieved. Also,
Since one processor element PE has a plug-in configuration integrated into one board, the number of units mounted in the unit can be easily set or changed according to the use of the system. FIG. 16 is a basic block diagram showing only the connection between the processor elements PE in the hardware configuration of FIG. The portion surrounded by the broken line 460 is shown in FIG.
4 shows the inside of the unit, and signal lines 480 to 485 are shown in FIG.
4 processor element PE on the backboard 466
The connection outside the unit is indicated by an arrow outside the dashed line, indicating a connection signal line with another processor element PE outside the unit. FIG. 16 shows a part of the processor element group 2 of the vertical and horizontal matrix shown in FIG. 2, and any system can be constructed by combining a plurality of these units.

Next, an embodiment in which the parallel processing system of the present invention is applied to specific signal processing will be described. FIG.
FIG. 1A is an embodiment in which the present invention is applied to an acoustic simulation analysis apparatus, FIG. 1A shows a block configuration of signal processing, and FIG. 1B is a state diagram in which signal processing blocks are assigned to respective processor elements of a parallel processing system. is there. The acoustic simulation analysis is to simulate and analyze an acoustic space, simulate acoustic characteristics of a concert hall or the like, compare with actual indoor acoustic characteristics, and use it for acoustic design.

In FIG. 17A, blocks 201 to 204 are a part of an acoustic simulation, blocks 205 to 208 perform an analysis of an acoustic signal, and a block 209 converts the simulated audio into an actual sound. To play back and output. A method of using the apparatus is to input a test sound signal before designing a room sound, and simulate a target sound characteristic by blocks 201 to 204. At this time, the actual sound is monitored by hearing the ear, and at the same time, the sound simulation signal is frequency-analyzed by the blocks 205 to 208, and is output as a video so that it can be visually analyzed. Then, based on the analyzed contents, the acoustic design of the room is performed, and the information is used as information for manufacturing the acoustic equipment.

The apparatus of this embodiment can be used as an apparatus for testing the acoustic equipment manufactured as described above. That is, an audio signal is collected in an actual indoor space by recording or the like, and the audio signal is collected by the sound source encoding block 2.
01 and encodes it into a signal that is easy to process. Then, without performing the simulation processing of the blocks 202 to 204, the signal is directly bypassed to the frequency conversion unit 205 through the route of the signal line 210, and the acoustic characteristics thereof are analyzed by the blocks 205 to 208, and are output as video. The analysis data thus obtained is compared with the characteristics of the contents of the simulation before the design, and it is confirmed whether the design and manufacture have been performed as required.

The contents of each processing block are as follows.

(1) Acoustic coding block 201 A sound for reproduction in an acoustic space is digitized, and a test signal generated by actual recording or a synthesizer is sampled by an A / D converter.

(2) Sound source reproduction block 202 The digital data of the coded audio signal is stored and sequentially output according to the application.

(3) Reverberation Effect Block 203 Simulates different reverberation effects depending on the structure and room material of the room as a general.

(4) Propagation loss effect block 204 Changes in sound pressure level and frequency characteristics depending on the size of the acoustic space are obtained.

(5) Frequency conversion block 205 In performing frequency analysis of sound, a specific frequency band is enlarged and displayed as video output data, so that the frequency bandwidth is varied.

(6) FFT block 207 In order to analyze an acoustic signal, a power spectrum of a frequency component is generated by Fourier transform.

(7) Smoothing block 207 In displaying the image of the frequency power spectrum obtained by the FFT processing, a smoothing processing is performed to enhance a specific frequency component in order to improve the recognition of an operator.

(8) Video output block 208 The result of frequency analysis of the audio signal is visually displayed by video.

(9) Hearing sound output block 209 In order to monitor the digital sound signal obtained by the reverberation effect and propagation loss effect processing, the sound is output through a D / A conversion process.

FIG. 10B is a configuration diagram at the time of operation when the acoustic simulation analyzer of FIG. 10A is constructed by a parallel processing system to which the present invention is applied.
As shown, the processor elements PE1 to PE6 of the present invention are allocated to the processing blocks of blocks 202 to 207. The number of processor elements PE and the physical connection configuration are the same as the configuration in FIG. PE
The broken lines 1 to 3 indicate that the signal line 210 is formed by the through relay function.

FIG. 18 is an embodiment of an acoustic simulation analysis apparatus similar to that of the embodiment of FIG. 17, except that the number of sound sources to be simulated and analyzed is two, and stereo acoustic characteristics are obtained. . FIG.
(A) and (B) are diagrams in which the processor element PE of the present invention is allocated to the block in FIG. FIG. 1A shows a system configuration in which acoustic simulation and analysis are performed at the same time, and FIG. 1B shows a system in which only a frequency analysis and an image output function for an acoustic characteristic test are operated. As shown in the diagram, the sound reproduction block 202 and the reverberation effect block 20 are used.
3. Propagation loss effect block 204, FFT block 20
The PEs corresponding to 6 are duplicated. This is because the processing load is almost doubled because stereo sound characteristics are obtained.

FIGS. 19 (A) and 19 (B) are schematic diagrams showing a system configuration diagram when the system is configured by a processor element group having a 4-row, 4-column array, respectively, corresponding to FIGS. 20 and 21, respectively. I do. As can be seen from the figure, each processor element PE has eight communication channels, and through relay can be arbitrarily performed independently.
The degree of freedom in the system configuration is high, and the system shown in FIG. 18 can be constructed with a small number of processor elements.
Such a system is disclosed in, for example, Japanese Unexamined Patent Publication No.
This cannot be realized by the system of Japanese Patent No. 564.
For example, a configuration in which the route of the through relay crosses the route of the transmission and the reception like the processor element PE5 in FIG. 20 cannot be realized.

FIG. 22 (A) shows a parallel processing system according to the present invention, which is described in TOS described in “Image Processing Applied Technology” published by the Industrial Research Council.
This is an embodiment in which PIX-U is applied to contour extraction processing of a grayscale image. As an outline of the processing, the image input device 30
The original image digitized by 1 and stored in the memory is differentiated in the X and Y directions for filtering in a filtering block 302, and further binarized by a next filtering block 303. As a result, the obtained contour image is output to the image output device 305, and the feature measurement is performed by the feature measurement block 304. FIG. 22 (B)
FIG. 23 is a block diagram in the case where high-speed computation is performed by the parallel processing system in the processing of FIG. 22A, similarly to the example of the acoustic simulation system. The filtering (X, Y direction differentiation) block 302 in FIG. 22A is processed in parallel by the two processor elements PE1 and PE5. Next-stage filtering (addition / binarization) block 303
Has a configuration in which addition processing and binarization processing are performed in series, and PE
2 and PE3. Then, the binarized data is directly output to the image output device 305 and transferred to the PE 4 corresponding to the feature measurement block 304.

FIG. 23 shows a connection configuration diagram of a parallel processing system corresponding to the configuration of FIG. In this case, the scale of the processor element is 3 × 2. The connection between the image input device 301 and the image output device 305 and the direction of the communication channel between each PE and the direction of the communication channel can be set by a management processor (not shown). The interface signal lines indicated by solid lines and arrows indicate connections and data flows used in actual signal processing, and the connections indicated by broken lines indicate portions where physical connections exist but data transfer does not occur. ing. In the illustrated example, the PE 6 is in an unused state.
As described above, the configuration in FIG. 23 is equivalent to that in FIG. 22B, and realizes connection between PEs according to the content of signal processing.

In addition to the effects of the above-described embodiment, FIG.
According to the embodiment described with reference to FIGS.

(1) If the number of processor elements is grasped in consideration of the load on one processor element, the parallel processing system can be quickly constructed with little awareness of the physical connection between the processor elements. It is possible.

(2) The management processor can immediately recognize the types of signal processing that can be processed by sequentially grasping the connection between the processor elements.

(3) By providing a means for monitoring the transmission / reception state of the destination communication channel for each communication channel, a physical connection error or a setting error on software can be immediately detected.

[0102]

As described above, according to the present invention,
The following effects can be obtained. First, according to the first invention, a plurality of through relays between arbitrary processor elements can be performed at the same time, and transmission or reception is performed at the same time without any limitation of other through relays. be able to.

Further, the parallel system configuration of the processor elements can be freely and promptly constructed according to the contents of the processing program.

Further, a parallel processing system can be automatically constructed according to the contents of data processing. In particular, the processing operation of each processor element is synchronized, and the mode of the necessary communication channel is changed and set by the management processor according to the end of the processing unit constituting the data processing or the end of the data transfer, whichever is later. According to this, an optimal parallel processing system can be constructed according to the processing unit for each phase constituting a group of data processing, and an optimal high-speed processing system is constructed according to the contents of the data processing. it can.

According to the second invention, data processing can be continued even if a failure occurs in a part of the processor element group,
A highly reliable system can be provided.

According to the third aspect, eight communication channels of processor elements are provided, and the processor elements arranged in a matrix are connected vertically, horizontally, and diagonally. Therefore, more complex data processing including multi-stage processing can be performed by a processor element group of a limited scale.

According to the fourth aspect, the processing operation of each processor element is performed in synchronization with the same synchronization signal, so that the overhead time can be reduced and the throughput can be improved.

In particular, according to the configuration in which the time required for the switching operation of the communication channel is included in the period of the synchronization signal, the configuration of the parallel processing system can be changed for each processing unit. It is possible to construct a system that can further increase the processing speed by using the processor element. In this case, the throughput can be further improved by unifying the processing unit amount of the processor element group and the data transfer amount accompanying the processing and setting the period of the synchronization signal based on the unified amount.

[Brief description of the drawings]

FIG. 1 is a configuration diagram around a communication channel according to an embodiment that is a characteristic part of the present invention.

FIG. 2 is an overall configuration diagram of an embodiment of a parallel processing system according to the present invention.

FIG. 3 is an overall configuration diagram of an embodiment of a processor element of the present invention.

FIG. 4 is a functional configuration diagram of an embodiment of a management processor of the present invention.

FIG. 5 is a functional block configuration diagram of an embodiment of a synchronization signal generator according to the present invention.

FIG. 6 is a flowchart of an embodiment of an initial process of the management processor of the present invention.

FIG. 7 is a flowchart of one embodiment of a signal type recognition process of the management processor of the present invention.

FIG. 8 is a flowchart of one embodiment of a connection process between PEs of the management processor of the present invention.

FIG. 9 is a flowchart of one embodiment of a synchronization signal cycle setting process of the management processor of the present invention.

FIG. 10 is a diagram for explaining the operation timing of the data transfer processing of one embodiment in the parallel processing system of the present invention.

11A and 11B are diagrams illustrating a data transfer operation of a comparative example for describing a data transfer operation of the present invention.

FIG. 12 is a hardware configuration diagram of an embodiment of a parallel processing system according to the present invention.

FIG. 13 is a schematic configuration diagram of the inside of the hardware configuration diagram of FIG. 12;

FIG. 14 is a block diagram of an embodiment in which a part of the processor element of the embodiment shown in FIG. 3 is formed into an LSI;

FIGS. 15A and 15B are hardware configuration diagrams of an embodiment of a parallel processing system using the processor elements of the embodiment shown in FIG.

16 is a configuration diagram illustrating an example of interconnection of a parallel processing system using the processor elements illustrated in FIG. 14;

FIG. 17 is a configuration diagram of an embodiment in which the parallel processing system of the present invention is applied to acoustic signal simulation / analysis processing, where (A) is a processing block diagram of acoustic signal simulation / analysis processing, and (B) is (A). 3 is a conceptual configuration diagram in which a processor element of the present invention is assigned to each block.

FIG. 18 is a processing block configuration diagram of another embodiment of the acoustic signal simulation / analysis processing to which the parallel processing system of the present invention can be applied.

FIG. 19 is a conceptual configuration diagram in which a processor element of the present invention is allocated to each processing block of FIG. 18;
FIG. 3A is a system configuration diagram when an acoustic simulation and an analysis process are performed at the same time, and FIG. 2B is a system configuration diagram when an acoustic characteristic designed by the simulation is tested.

FIG. 20 is a system configuration diagram showing a connection switching state of a communication channel corresponding to the system configuration diagram of FIG.

21 is a system configuration diagram showing a communication channel connection switching state corresponding to the system configuration diagram of FIG. 19 (B).

FIGS. 22A and 22B are configuration diagrams of an embodiment in which the parallel processing system of the present invention is applied to image processing, wherein FIG. 22A is a processing block diagram of image processing, and FIG. It is a conceptual block diagram which allocated the processor element of this invention. .

FIG. 23 is a system configuration diagram showing connections in an operation state of each processor element corresponding to the system configuration diagram shown in FIG. 22;

[Explanation of symbols]

 Reference Signs List 1 input device, 2 processor element (PE), 3 output device, 4 management processor, 5 synchronization signal generator, 6 interface communication line, 20 signal processing unit, 21 signal processor, 22 instruction memory, 23 data storage, 30 control unit 31 control processor, 32 channel mode setting register, 33 channel status register, 34 partner status register, 40 communication unit, 41A and B switching means, 42 bypass bus, 43A and B buffer memories A and B, 44 transfer means, 45 transmission and reception / Through mode switching means, 46 partner PE status monitoring means, 47 bypass bus switching means, 48 signal lines for through, 61 CPU, 62 storage for program download, 63 main memory, 63A PE Status monitoring program, 63B signal processing type recognition program, 63C control command generation program, 64 reception channels, 65 transmission channels, 66 synchronization signal control means,

──────────────────────────────────────────────────続 き Continuing on the front page (72) Yoshiaki Matsumoto, Inventor 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture Inside Hitachi Information & Control Systems Co., Ltd. (72) Takuo Unno 5-2-2 Omikacho, Hitachi City, Ibaraki Prefecture No. 1 Hitachi Information Control System Co., Ltd. (72) Inventor Hiroshi Watanabe 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture In-house Omika Plant, Hitachi, Ltd. (56) References JP-A-63-70345 (JP, A) (58) Fields investigated (Int.Cl. ⁶ , DB name) G06F 15/177 G06F 15/16 390 G06F 15/16 470

Claims (5)

(57) [Claims] A plurality of processor elements each comprising a processor, a memory, and a plurality of communication channels connected by an internal system bus, wherein each of the processor elements is connected to a predetermined number of other processor elements via the communication channel. In a parallel processing system connected to each other and sharing and executing a group of data processing to each of the processor elements in accordance with a command given from a management processor, the processor elements share a plurality of the communication channels belonging to the processor elements in common. A plurality of connectable bypass buses, each of the communication channels including a channel mode switching unit for connecting another processor element connected to the communication channel to the internal system bus or one of the bypass buses; In-than, the channel mode
The mode switching means is a key provided by the management processor.
A parallel processing system which is switched according to a channel mode command . 2. The processor according to claim 1 , wherein the management processor transmits processing data of a processor element to which the communication channel belongs to a plurality of other processor elements by switching channel mode switching means of each communication channel. A parallel processing system characterized by the following. 3. The management processor according to claim 1 , wherein the management processor manages a connection state between an interface communication line connecting the plurality of processor elements and a communication channel, and a processing share of the processor elements. A communication channel mode setting means for determining a mode of each communication channel based on the determination and outputting the channel mode command to each processor element based on the determination. 4. The communication channel mode setting means according to claim 3 , wherein said management processor sets a communication channel mode required by said communication channel mode setting means in accordance with whichever of the end of said processing unit of data processing and the end of data transfer. A parallel processing processor characterized in that: 5. In any of claims 1 to 4, wherein the channel mode switching means comprises first switching means for connecting said other processor elements to one of the internal system bus and a through signal lines, the A second switching unit for selectively connecting a through signal line to one of the bypass buses.