JP2856884B2 - Train line wear treatment equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a sliding amount which is a wear amount of a train line on which a pantograph of a train slides, that is, a width of a worn portion of a sliding surface. The present invention relates to a train line abrasion treatment device for calculating a surface width.

(Prior Art) There are two types of optical methods that can be used in this type of train wire abrasion treatment apparatus: a method using an ITV camera and a method using a laser.

In the system using an ITV camera, as shown in FIG. 5 (a), a light is emitted from a projector 50 to a train line 51 on which a pantograph 60 of a train slides, and this light is reflected from the train line 51. The light passes through a glass 52 attached to the roof of the measuring train, is further received by an ITV camera 56 via a first mirror 53, a second mirror 54, and a third mirror 55, and is converted into a video signal. This video signal is supplied to the processing device 57 via the lead wire 78.

By the way, the height of the train line 51 is not constant, 5400mm ~ 42
Since the light fluctuates within the range of 00 mm, the light reflected from the sliding surface of the trolley wire 51 has a different distance until it reaches the ITV camera 56, and is out of focus.
The signal of the potentiometer 61 attached to the axis of the pantograph 60 whose rotation angle changes according to the height of 51 is detected by a height detector.
The calculated height signal is supplied to the follow-up mechanism 63 by calculating the height of the train line 51 by taking it into the track 62. The follow-up mechanism 63 operates the arm 64 according to the height by using the hydraulic pressure of the hydraulic device 65, thereby moving the second and third mirrors 54 and 55 left and right in the figure, and focusing the ITV camera 56. I try to match.

On the other hand, in the method using a laser, as shown in FIG. 5 (b), a laser beam 71 from a laser device 70 is gradually tilted in a direction indicated by an arrow in an irradiation width 74 by a rotating mirror 72 and a mirror 73. Train line shown in cross section while changing and scanning
The sliding surface A of 51 is irradiated, the laser beam reflected by the sliding surface A is reflected by a half mirror 75, taken into a light receiving element 76, converted into a video signal, and the video signal is amplified by an amplifier 77. , To a processing device 80 via a lead wire 79.

As described above, the video signals supplied to the processing devices 57 and 80 are obtained as signal waveforms as shown in FIGS. 6 (a) and 6 (b). In the figure, the horizontal axis represents time, and the vertical axis represents voltage. In addition, as the wear amount of the trolley wire, the width of the slidable surface of the trolley wire on which the pantograph slides, that is, the width B of the slidable surface A as shown in the trolley wire 51 of FIG. 5B is calculated. I do.

In FIG. 6 (a), a fixed slice level is provided for the video signal, a time when the video signal exceeds this slice level is defined as a rise, and a time when the video signal falls below the slice level is defined as a fall. In this method, the distance to the fall is set as the sliding surface width.

In FIG. 6 (b), a peak value at the rising edge of the video signal is obtained, and a half point of this peak value is regarded as a rising point, and at the same time, the waveform of the video signal is delayed so as to pass through a half point. In this method, the point at which the delayed signal reaches the 0 level is regarded as a falling point, and the distance from the rising point to the falling point is used as the sliding surface width.

(Problems to be Solved by the Invention) In both of the conventional methods described above, a video signal is obtained by receiving light reflected on the sliding surface of a train line. Since the waveforms vary variously and are not uniform, there is a problem that the sliding surface width of the train line cannot be accurately obtained.

More specifically, even if the sliding surface width is one train line, the video signal may have a value lower than the slice level in the middle as shown in FIG. The obtained sliding surface width is divided into two. That is, in this case, the actual sliding line width of the train line is from the rising of the left waveform to the falling of the right waveform, but if the sliding surface width is determined only by the slice level, the number of the sliding lines is one. In other words, the number is two, and it is not possible to calculate an accurate sliding surface width. Also, if you try to lower the slice level to avoid such a situation,
The sliding surface width is calculated to be wider than the actual value, and contradicts the demand for increasing the slice level as much as possible, which is not desirable.

Further, as shown in FIG. 7 (b), it is possible to detect a video signal at half the rising peak point, but it is possible to detect a video signal at half the falling peak point. Since it is not possible, since the point where the 0 level is detected is set to fall, there is a problem that the sliding surface width is calculated to be wider than the actual value. By the way, 1/1 of the falling peak point
It can be seen that the sliding surface width is wider than that of the video signal A of No. 2.

The present invention has been made in view of the above, and it is an object of the present invention to be able to simultaneously and accurately calculate the amount of abrasion of a trolley line, that is, the number, the sliding surface width, and the deviation in a single scan. An object of the present invention is to provide a train line wear treatment device.

[Configuration of the invention]

(Means for Solving the Problems) In order to achieve the above object, an electric wire wear processing apparatus according to the present invention is an imaging device for imaging a sliding surface of an electric wire while scanning every address in synchronization with a predetermined clock pulse. Means, a comparing means for comparing the video signal for each address from the imaging means with a predetermined reference value to binarize the image signal, and a combination of three consecutive binarized signals from the comparing means. 000 "
Is detected as the rising start address, and the combination of the binary signals of the three consecutive addresses is changed from "111" to "110" (from "111" to "110" in the inverted logic). (Inverted logic from "000" to "00
1)), a detecting means for detecting the latest address that changes to the falling start address, and a difference between the falling start address detected by the detecting means and the next rising start address detected is compared with a predetermined value. If it is larger than a predetermined value, it is determined that there is another train line from the next detected rising start address, and if it is smaller than the predetermined value, the next detected rising start address is before that. It is determined from the detected rise start address that the same train line exists, and the number, the slide surface width, and the deviation of the train lines are determined based on the rise start address and the fall start address detected by the detection unit. And a calculating means for calculating.

(Operation) In the trolley line wear processing apparatus of the present invention, the sliding surface of the trolley line is imaged while scanning for each address in synchronization with a predetermined clock pulse, and a video signal for each address is compared with a predetermined reference value. The combination of the binarized signals of three consecutive addresses is changed from “000” to “001” (“111” in the inverted logic).
Is detected as the rising start address, and the combination of three consecutive address binary signals is from "111" to "110" (inverted logic is "000" to "001"). ) Is detected as the falling start address, and the difference between the detected falling start address and the next detected rising start address is compared with a predetermined value. Determines that there is another train line from the next detected rising start address, and if it is smaller than the predetermined value, the next detected rising start address is the same as the previously detected rising start address. It is determined that there is a train line, and the number of the train lines, the sliding surface width, and the sliding surface width are determined based on the rising start address and falling start address of each train line. And calculates the deviation.

(Example) Hereinafter, an example of the present invention is described using a drawing.

FIG. 1 (a) is a block diagram showing a configuration of a train line wear treatment apparatus according to one embodiment of the present invention. The trolley line wear processing apparatus shown in the figure is provided with an imaging unit 41 including an image sensor 11 for imaging the sliding surface of the trolley line, and a video signal from the imaging unit 41. And a processing device 12 for calculating the width and the deviation of the distance. The processing device 12 compares a video signal from the imaging unit 41 with a reference value and binarizes the comparison result.
The reference value storage unit 42 stored to be supplied to the storage unit 42 stores a plurality of values from the past to the present of the binarized signal from the comparison unit 43, and matches them through a circuit that has previously formed a rising or falling pattern. A detection unit 44 for determining whether or not there is, a storage unit 45 for temporarily storing the detection result from the detection unit 44, and a number calculation unit 46 for reading out the result stored in the storage unit 45 and calculating the number of train lines. And a deviation sliding surface width calculator for calculating a deviation address and a sliding surface width of each of the train lines.
47, and a timing control unit 48 for generating an entire timing signal. The number calculating section 46 and the eccentric sliding surface width calculating section 47 constitute an arithmetic processing section 121.

FIG. 1 (b) is an explanatory diagram showing the relationship between the image sensor 11 and the electric line 51 constituting the imaging unit 41 of the electric line wear processing device of FIG. 1 (a) embedded in the pantograph boat 13. . As shown in the figure, the image sensor 11 is embedded in the pantograph hull 13 and is configured to slide on the sliding surface of the train line 51, thereby capturing an image of the sliding surface of the train line 51, The signal is supplied from the image sensor 11 to the processing device 12, and the displacement amount and the amount of displacement of the sliding surface width B of the electric line 51 and the distance C from the center C of the pantograph hull 13 to the center of the electric line 51 are supplied to the processing device 12. The sliding surface width B of the line 51 is calculated.

The image sensor 11 scans sequentially from one end to the other end, that is, scans from address 1 to the last address, and supplies a video signal of each address for each scan to the processing device 12. I have. Note that the above-mentioned deviation amount is a deviation amount from the center of the pantograph boat 13, but in this embodiment, it is a deviation amount from the address 1. Further, the timing control unit 48 supplies the imaging unit 41 with a clock pulse for scanning and imaging for each address, and the detection unit 44,
A timing pulse for controlling the storage unit 45 and the arithmetic processing unit 121 is generated.

In the trolley wire abrasion processing device configured as described above, the video signal captured by the imaging unit 41 for each address is supplied to the comparison unit 43, and is compared with the reference value α from the reference value storage unit 42 to obtain a binary signal. Be transformed into The binarized video signal is supplied to the detection unit 44, and the detection unit 44 fetches a plurality of binarized video signals stored from the past to the present for each address and configures the circuit in advance as a circuit. It is determined whether the pattern matches the rising and falling patterns, and the address at the time of the rising or falling and the rising or falling flag indicating the rising or falling are stored in the storage unit 45. Arithmetic processing unit 12
The one number calculation unit 46 reads all the sets of each address and the rising / falling flag data stored in the storage unit 45 from the storage unit 45, and if there are a plurality of sets of data, the train line Is determined to determine whether the number is one or two, and the number of the trolley lines is detected, and the eccentric sliding surface width calculating section 47 calculates the eccentric address and the slid surface width for each one of the trolley lines. ing.

FIG. 2 is a block diagram showing a configuration of a trolley line wear treatment apparatus according to another embodiment of the present invention. The trolley wire abrasion processing apparatus shown in FIG. 1 is configured by an image sensor as shown in FIGS. 1A and 1B and has an imaging unit 100 that captures an image of the trolley wire 51. When the start pulse and the clock pulse are supplied from the timing controller 200, the imaging unit 100 outputs the video signal from the address 1 to the last address (effective pixel signal) in synchronization with the clock pulse for a period effective for imaging. , A / D converter 101. The A / D converter 101 converts the analog video signal from the imaging unit 100 into a digital video signal, and temporarily stores the digital video signal in the save register 102 as numerical data. The video signal stored in the save register 102 is supplied to the comparator 103, and the reference value register 1
It is compared with the reference value α from 19 and output as a signal of 0 or 1. Assuming that the video signal supplied from the save register 102 to the comparator 103 is P, the comparator 103
Is greater than the reference value α, 0 is output, and if the video signal P is less than or equal to the reference value α, 1 is output. The signal of 0 or 1 from the comparator 103 is inverted by the inverter 104, and is sequentially supplied to the shift register 105a, the shift register 105b, and the shift register 105c. This shift register 105
a, shift register 105b and shift register 105c
The current 1,0 data supplied from the inverter 104, the previous 1,0 data one pulse before, and the previous 1,0 data two pulses before are stored. Each of the shift registers 105a, 105b and 105c is constituted by one chip, and is reset to 0 by hardware when power is turned on. The present, previous and previous 1,0 data from the three shift registers 105a, 105b, and 105c are respectively provided with a rising detector 107 and a falling detector 108 which are partially constituted by AND gates having an input inversion function.
Supplied to

The rise detector 107 detects the rise and outputs a high logic level 1 output signal when the current, previous, and previous 1,0 data from the shift registers 105a, 105b, and 105c are "110". In addition, the falling detector 108 detects the falling when the current, previous and previous 1,0 data from the shift registers 105a, 105b, and 105c are "011", and outputs a high logic level output signal. Output. Output signals from the rise detector 107 and the fall detector 108 are supplied to a gate 110 through an OR circuit 109.
The gate 110 opens at the timing of the rising edge of the effective pixel pulse supplied from the timing controller 200, passes the pulse signal from the OR circuit 109, and supplies it to the result RAM counter 111. Result RAM counter 1
11 counts the number of pulse signals and stores this count value. This count value is temporarily stored in the buffer register 112.

In addition, the train line wear treatment device shown in FIG.
The result RAM 115 is for writing and storing the data set in the data gate 114 at the address specified by the address gate 113, and is provided in two sets.
The address gate 113 is a circuit to which a count value is input, decodes the address of the result RAM 115 and opens the gate of the write address, and two sets are provided similarly. The data gate 114 is a circuit that opens a gate corresponding to a corresponding bit of the result RAM 115 when an address count value is input, and two sets of data gates are similarly provided. Selector 118 connected to data gate 114
Is a circuit for connecting the data gate 114 to the selected one of the two result RAMs 115.

By the way, the timing controller 200, in addition to the start pulse and the clock pulse as described above,
An effective pixel pulse and a select pulse are output, and these pulses have a relationship as shown in FIG. 3 (b). The interval of the start pulse is generated by counting a predetermined number of clock pulses, and when the start and end of the effective pixel pulse are advanced by a predetermined count, generation and stop are performed.

The valid pixel pulse is supplied to the address counter 201 connected to the timing controller 200.The address counter 201 counts the valid pixel pulse to form an address. Supplied. The address counter 201 returns to 0 when the valid pixel pulse is counted up to a predetermined count value.

FIG. 2 shows that the train line wear processing device has a CPU 300, which has a buffer register 112 and a reference value register 119.
, Or read out the contents stored in the result RAM 115 to perform an arithmetic process, and supply the result to a processing unit in the next stage. The CPU 300 has a data bus 210
And the RAM / ROM 301 are connected to the RAM / ROM 301 via an address bus 220.The RAM / ROM 301 includes a RAM unit and a ROM unit. The ROM unit stores a program for executing an operation. The contents of the buffer register 112 and the like are temporarily stored, intermediate results calculated by the CPU 300 are temporarily stored, and the calculation results are temporarily stored until output to the outside. The CPU 300 is connected to the RAM / ROM 301 and the address gate 113 via the decoder 305, so that the CPU 300 can select each of them via the decoder 305.

Further, in FIG. 2, reference numeral 302 denotes a digital input module (DIM) which receives a contact signal of the switch 307 and supplies it to the data bus 210. Reference numeral 303 denotes a peripheral interface (PI / F) that outputs an operation result to a processing unit in the next stage. 304
Is a decoder which, when a device number is input, selects a device to be connected, such as the buffer register 112, the digital input module 302, etc., and enables data writing and reading.

 Next, the operation will be described.

When the video signal from the imaging unit 100 is supplied to the A / D converter 101 for the effective pixel transmission period at the clock pulse interval, it is latched at the rising edge of the effective pixel pulse from the timing controller 200, converted to a digital signal, and saved. The data is supplied to the register 102. The save register 102 also takes in the digital signal from the A / D converter 101 during the ON period of the effective pixel pulse, latches it as digital data until the next effective pixel pulse is turned on, and outputs it to the comparator 103. The comparator 103 compares the video signal P from the save register 102 with the reference value α from the reference value register 119, and outputs 0 when the video signal P is larger than the reference value α, and outputs the video signal P with the reference value α. In the following case, 1 is output. This comparator 10
The output signal from 3 is inverted by the inverter 104, and the shift register 105a, the shift register 105b and the shift register
105c.

The shift register 105a, the shift register 105b, and the shift register 105c are shifted by the rising edge of the effective pixel pulse from the timing controller 200.
Is transferred to the shift register 105c, then the contents of the shift register 105a are transferred to the shift register 105b, and the output signal from the inverter 104 is stored in the shift register 105a. The inverted signal of the comparison result of 103 is shifted while sequentially inputting in synchronization with the effective pixel pulse, whereby the data of the current comparison result supplied from the inverter 104,
The previous comparison result data that is one pulse before and the previous comparison result data that is two pulses before are stored, and these comparison result data are supplied to the rise detector 107 and the fall detector 108. The output signal of the shift register 105a is supplied to a flag bit which is 0 bit of the data gate 114.

The rise detector 107 determines that the comparison result data from the shift registers 105a, 105b, and 105c for the current, previous, and previous and previous times is "110" (as shown in FIG.
In the case of inverted data of the data which becomes "001" on the input side of, the rising edge is detected and the output signal of the high logic level 1 is output.
If the comparison result data of the current, previous, and previous times from 05a, 105b, and 105c is “001” (inverted data of “110” on the input side of the inverter 104), the falling is detected and a high logic Output level output signal.

The rise and fall detection output signals from the rise detector 107 and the fall detector 108 are
It is supplied to the gate 110 through 9. The gate 110 opens the gate during the ON period of the valid pixel pulse from the timing controller 200, and supplies the rise and fall detection signal passed through the OR circuit 109 to the result RAM counter 111. The result RAM counter 111 counts the rise and fall detection signals passed through the OR circuit 109, and supplies the count value to the address gate 113 and the buffer register 112. The address gate 113 converts the count value from a binary number to a decimal number and selects an address of the result RAM 115. On the other hand, the data gate of the result RAM 115
An address count value obtained by the address counter 201 counting valid pixel pulses from the timing controller 200 is supplied to the address register 114, and this address count value is transmitted to the address register together with flag data as an output signal of the shift register 105a. The result is stored in the result RAM 115 at the address selected by the gate 113. Note that the flag data, which is the output signal of the shift register 105a, indicates whether the rising or falling signal detected at the address stored in the result RAM 115 at this time is a rising signal or a falling signal. When the output signal of the shift register 105a is 1, it means a rising signal, and when it is 0, it means a falling signal. That is, in the result RAM 115, each time the rising and falling of the video signal of the sliding surface width captured by the imaging unit 100 occurs, the address at that time is stored, and the time of this address is the rising or The information as to whether the edge is falling is also stored as flag data, and this process is performed throughout the effective pixel transmission period in which the effective pixel pulse is generated (see (b) in FIG. 3B). .

The result RAM 115, the address gate 113, and the data gate 114 are two sets of # 0 and # 1, respectively, and the selection pulse from the timing controller 200 selects which one of the result RAMs 115 is to be stored. . That is, when the select pulse is on, the write operation is performed on the # 0 result RAM 115 with the # 0 address gate 113 and the data gate 114 as the write side, and the other # 1 address gate is performed.
Gate control is performed so that the read operation is performed on the # 1 result RAM 115 with the read gate 113 and the data gate 114 serving as the read side.
It is turned on via 6,117 and the address gate 1 of # 1
13 and the data gate 114 on the write side to perform a write operation on the result RAM 115 of # 1 and the other # 0
The read operation is performed on the # 0 result RAM 115 with the address gate 113 and the data gate 114 of FIG.

On the other hand, the CPU 300 operates by program processing,
The operation of the CPU 300 will be described with reference to FIGS. 4 (a) and 4 (b).

When the power is turned on, the CPU 300 receives a reset pulse and executes a program starting from a head address written at a specific address determined by hardware.
The data is read from the ROM area of the M / ROM 301 one step at a time and decrypted and executed.

In this execution, as shown in FIG. 4 (a), first, the contact state of the switch 307 (that is, the reference value α set in the reference value register 119 previously set manually) is transmitted to the digital input module 302. Connected and taken in as digital data of 1,0. That is, the CPU 300 gives the device number of the digital input module 302 to the decoder 304 to read the state of the input data of the digital input module 302 and selects it, and captures the state of the digital input module 302 via the data bus 210. The data is written to the address d1 in the RAM area of the RAM / ROM 301 (step 501). Whether the CPU 300 selects the RAM / ROM 301 or the result RAM 115 is determined by selecting the address number of the RAM / ROM 301 or the address gate 113 to the decoder 305 by the program and reading the data of the result RAM 115 by the address bus 220. The address of the result RAM 115 is selected by giving the read address (the read content (count number) of the buffer register 112) to the address gate 113 through the RD to the RD.

Next, the CPU 300 sets the address d1 of the RAM area of the RAM / ROM 301.
Is specified via the address bus 220, the contents of the address d1 are taken out to the data bus 210, and supplied to the reference value register 119 (step 520). That is, the reference value register 119
Is set to a reference value α. The next step 530 is a switch function provided for ignoring interrupt processing described later, and "1" is set in the address d2 of the RAM area of the RAM / ROM 301.
Is written, thereby ending this processing.

Next, when the select pulse from the timing controller 200 is supplied to the interrupt circuit 306, the interrupt circuit 3
06 detects a change in the select pulse shown in (a) of FIG. 3 (b) and interrupts the CPU 300. As a result, CPU3
00 detects the interrupt destination in a hardware manner, jumps to step 610 shown in FIG. 4B, which is the start address of the interrupt destination, and executes the processing shown in FIG. 4B.

In step 610 shown in FIG.
Indicates the device number of the result RAM counter 111 in the decoder 30
The result is output to 4 and selected, and a reset pulse is supplied to the result RAM counter 111 to clear the counter to zero. Next, the RAM / ROM executed in step 530 of FIG.
It is checked whether the contents of the address d1 in the RAM area 301 are 1 (step 620). If the content of the address d1 is 1, the process proceeds to step 630; otherwise, the process proceeds to step 640. In step 620, since no data has been written to the result RAM 115 at this time, it cannot be read. Therefore, this is a process for ignoring the reading. Step 630 is a process for permitting reading at the next interrupt, resetting the tag, that is, writing 0 to the address d2 of the RAM / ROM 301,
This processing ends.

In step 640, the buffer register 112 is selected, and the count number, which is the content of the buffer
Write to address mo of AM area. In the present embodiment, the description will be made assuming that the count number is “4”.

Next, at step 650, the address gate 113 is selected, and the address read from the address gate 113 is sequentially read from the address 1 to 4 by the program by the count number "4" which is the content of the address mo of the RAM area of the RAM / ROM 301. Is selected from the memory on the reading side of the result RAM 115 through the data gate 114 to select the data gate 114 on the reading side in accordance with the signal level of the select pulse generated by the timing controller 200. RAM area addresses m1, m2, ...
• Write to m4. At the same time, the flag of the 0th bit is checked, and it is checked whether the flag is “1010”, that is, in the order of rising, falling, rising, and falling. Reset all to 0 and proceed to the next step 660. If this is not the case,
This processing ends (step 655).

In step 660, it is determined whether the number of the train lines is one or two. This is the address m2 of the RAM area of the RAM / ROM 301.
Is added to the determination value β and compared with the content of the address m3 in the RAM area of the RAM / ROM 301. If the content of the address m3 is large, it is regarded as two, and the process proceeds to step 690. Is regarded as one, and the process proceeds to step 670. In step 670, the contents (address a4) of the address m4 in the RAM area of the RAM / ROM 301 are moved to the same address m2. Then, 2 is subtracted from the contents of the address mo in the RAM area of the RAM / ROM 301 (step 680). That is, assuming that the train line rises at the address a1 and falls at the address a4, ignoring the addresses a2 and a3 in the middle, the addresses a1 to a4
Up to one.

In step 690, to determine the deviation of the line 1,
Calculate the center address of the sliding surface width. That is, RAM / ROM3
The contents of the addresses m1 and m2 in the RAM area 01 are shifted by one bit to the right, respectively, to halve the value. Then, when each is added, the center address is obtained.
Write to address m11 in RAM area of M301. Next, a value obtained by subtracting the content of the address m1 from the content of the address m2 is written to the address m21 in order to obtain the sliding surface width of the train line 1 (step 700).

Next, the contents of the address mo are examined to check whether the count number is 4, that is, whether there are two train lines. If the count number is 4, proceed to the next step 720, otherwise. If so, proceed to step 740 (step 71
0). If the count number is 4, in step 720, the contents of the addresses m3 and m4 are shifted to the right by one bit, and added to each other, and written to the address m12 in order to obtain the deviation address of the train line 2. . Then, in order to obtain the sliding surface width of the train line 2, the address m3 is obtained from the content of the address m4.
And writes the value to the address m22 (step 730).

As described above, the data of the number of trolley lines, the deviation address, and the width of the sliding surface are obtained. In the case of two trolley lines, the data are stored at addresses mo, m11, m21, m12, and m22, respectively. In the case of one line, it is stored at addresses mo, m11, and m12, respectively. These data are read out from the RAM area of the RAM / ROM 301 via the peripheral interface 303, output to the next processing unit, and the processing is terminated (step 740).

As described above, the writing to one of the two result RAMs 115 and the reading from the other result RAM 115 are performed at the same time, the program processing is executed, and the result is output to the outside in parallel. Note that the detection width is slightly widened so that the width of the train line sliding surface can be detected within the last effective pixel pulse, so that the fall detection is always performed and no error occurs. In addition, since only the rising and falling detection data of the sliding surface width is narrowed down from about 4000 pixel data in one cycle and the detection data can be temporarily stored, the already written detection data is read in parallel with writing. Software processing becomes possible, and the processing capacity is remarkably improved as compared with the conventional analog processing.As a result, invalid data is eliminated from the rising and falling detection data, and only the data appropriate for the train line is removed. In addition, the number of train lines, the sliding surface width, and the deviation address can be calculated.

〔The invention's effect〕

As described above, according to the present invention, a video signal for each address obtained by imaging the sliding surface of a train line while scanning for each address in synchronization with a clock pulse is binarized by comparing with a predetermined reference value. , The latest address in which the combination of the binarized signals of the three consecutive addresses changes from “000” to “001” (“111” to “110” in the inverted logic) is detected as the rising start address, and is detected again. The latest address in which the combination of the binary signals of the three addresses changes from "111" to "110"("000" to "001" in the inverted logic) is detected as the fall start address, and further detected. The difference between the falling start address and the next detected rising start address is compared with a predetermined value.If the difference is larger than the predetermined value, it is determined that another train line exists from the next detected rising start address. If the value is smaller than the predetermined value, the next detected rising start address determines that the same train line exists from the previously detected rising start address. Since the number of train lines, the sliding surface width, and the deviation are calculated based on the start address, the rising and falling of the sliding line width of the train line can be reliably detected, and noise and video signal levels can be detected. The decrease can be relieved, and stable measurement can be performed. In addition, not only the sliding surface width of the train lines but also the number of train lines or the deviation of each train line can be obtained at the same time in one scan, so there is another means for obtaining deviation data and the number of lines as in the past. It becomes unnecessary and the equipment becomes simple.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a trolley wire wear treatment apparatus according to one embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a trolley wire wear treatment apparatus according to another embodiment of the present invention,
3 (a) and 3 (b) are waveform diagrams for explaining rising and falling of a train line and timing charts showing various output signals from a timing controller, respectively, and FIG. 4 is a train line wear processing apparatus of FIG. FIG. 5 is an explanatory view of the conventional electric wire wear processing device, and FIG. 6 is a waveform showing the relationship between the video signal and the sliding surface width of the conventional electric wire wear processing device shown in FIG. FIG. 7 is an explanatory view showing an error in a video signal of the conventional train line wear processing device. 11 image sensor, 41 imaging unit, 43 comparison unit, 44 detection unit, 45 storage unit, 46 number calculation unit, 47 deviating sliding surface width calculation unit. 51 ... Train line

Continuation of front page (72) Inventor Hideaki Aiba 1-1-1, Shibaura, Minato-ku, Tokyo Inside the Toshiba head office (56) References JP-A-54-138466 (JP, A) JP-A-52- 73055 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) B60L 5/00-5/42

Claims (1)

(57) [Claims] 1. An image pickup means for picking up an image of a sliding surface of a train line while scanning for each address in synchronization with a predetermined clock pulse, and comparing a video signal for each address from the image pickup means with a predetermined reference value. The combination of the comparing means for binarizing the data and the binarized signals of three consecutive addresses from the comparing means is changed from "000" to "001"("111" in the inverted logic).
Is detected as the rising start address, and the combination of the binary signals of three consecutive addresses is changed from "111" to "110" (in the inverted logic, from "000" to "001"). Detecting means for detecting the latest address changing to the falling start address, and comparing a difference between the falling start address detected by the detecting means and the next rising start address with a predetermined value. If the value is larger than the value, it is determined that another train line exists from the next detected rising start address, and if smaller than the predetermined value, the next detected rising start address is detected before that. It is determined from the rising start address that the same train line exists, and the rising start address detected by the detection means and the falling start are detected. Calculating means for calculating the number, the sliding surface width, and the deviation of the lines based on the address.