JP2856877B2 - Semiconductor nonvolatile storage device - Google Patents

Description

Description: Object of the Invention (Field of Industrial Application) The present invention relates to a semiconductor non-volatile memory device, and more particularly to a write-in peripheral of a semiconductor non-volatile memory device in which a high voltage is applied to an external terminal. Circuit.

(Prior art) Read-only storage device (EP
ROM), or, in the nonvolatile semiconductor memory device, such as electrically erasable and re-writable read only memory (EEPROM), a high potential V _PP and the potential for reading for writing within the semiconductor chip (normal supply voltage V _CC ) must be selectively generated, and a V _PP / V _CC potential switching circuit is provided.

FIG. 2 shows a conventional V _PP / V _CC potential switching circuit. Reference numeral 1 denotes a V _PP potential (for example, 12
V) is applied, and at the time of reading, 0 to V _CC potential (for example, 5 V)
There altering position input nodes applied, V _CC input node V _CC potential is applied 2, the switching power level output nodes 3, 5 and input the write enable signal ▲ ▼, higher predetermined potential than V _PP potential A boosting circuit 6 having a drain-source connected between the switching potential input node 1 and the switching potential output node 3 and having an output A of the boosting circuit 5 applied to its gate; transistor, 7 which is connected the drain-source between the V _CC input node 2 and the switching power level output node 3, an N-channel transistor of the depletion type write enable signal ▲ ▼ is applied to the gate.

In the V _PP / V _CC potential switching circuit, when the write enable signal ▼ is activated (0 V in this example) at the time of writing, the output A of the booster circuit 5 becomes a potential higher than the V _PP potential (for example, 16 V). . Therefore, enhancement mode transistor 6 is turned on, the switching power level output node 3, (without loss due to the threshold voltage) directly through the applied potential V _PP is an enhancement type transistor 6 of the switching power level input node 1 appears. At this time, 0 V is applied to the gate of the depletion type transistor 7.

On the other hand, when the write enable signal ▼ is inactive (5 V in this example) except at the time of writing, the output A of the booster circuit 5 becomes 0 V, and the enhancement transistor 6 is turned off. At this time, the depletion type transistor 7 is turned on by applying 5 V to the gate, and the applied potential V _CC of the V _CC input node 2 appears at the switching potential output node 3. At this time, the enhancement transistor 6 is completely turned off irrespective of the applied potential of the switching potential input node 1, so that the external terminal connected to the switching potential input node 1 is replaced with a terminal of another function (during normal read operation). (For example, output enable input terminal)
And the external terminals can be shared.

By the way, the conventional V _PP / V _CC potential switching circuit described above
The booster circuit 5 is used. The booster circuit 5 generates a voltage higher than a supply voltage from the outside of the chip by using the charge accumulated in the capacitance inside the chip using the principle of a charge pump. In a general ordinary booster circuit, the boosting speed is relatively slow, about 5 μs (approximately equal to the writing speed of recent miniaturized EPROM cells).

However, when the boosting speed of the boosting circuit 5 of the V _PP / V _CC potential switching circuit is slow, there is a problem that the speeding up of the writing operation, which is particularly important in a large-capacity nonvolatile semiconductor memory device, is hindered. .

(Problems to be Solved by the Invention) As described above, the conventional semiconductor nonvolatile memory device
_Since the boosting speed of the booster circuit of the _PP / V _CC potential switching circuit is slow,
In particular, there is a problem in that a high-speed writing operation, which is important in a large-capacity nonvolatile semiconductor memory device, is hindered.

The present invention has been made to solve the above problems,
The purpose is to select the write potential using the boosted output of the booster circuit that generates a voltage higher than the write potential and to extract the write potential for the inside of the chip. An object of the present invention is to provide a semiconductor nonvolatile memory device which can sufficiently cope with high speed operation.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor nonvolatile memory device according to the present invention is provided for selectively extracting a write potential input node to which a write potential is applied at the time of writing and a write potential for the inside of a chip. An enhancement type transistor and a depletion type transistor connected in series between a write potential output node and the enhancement type transistor which generate a boosted output which is boosted to a predetermined potential higher than the write potential during writing; And a switch circuit that uses the write potential as a power supply, performs a switch operation in response to a write enable signal, and applies a switch output to the gate of the depletion type transistor. I do.

(Operation) At the time of writing, a boosted output having a higher potential than the write potential is applied to the gate from the booster circuit to turn on the enhancement-type transistor, and in this state, the output of the write potential is applied to the gate from the switch circuit. When the depletion type transistor is turned on, the write potential of the write potential input node appears at the write potential output node at high speed. Accordingly, it is possible to sufficiently cope with a high-speed writing operation, which is particularly important in a large-capacity nonvolatile semiconductor memory device.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a V _PP / V _CC potential switching circuit in a semiconductor non-volatile memory device, for example, an EPROM, and 1 is applied with a V _PP potential (for example, 12 V) at the time of writing from outside the chip.
0 to V _CC potential (e.g. 5V) altering position input node to be applied within the time of reading, V _CC input node V _CC potential is applied 2, the switching power level output node 3, 6 and 8 the switching power level input node 1 and the switching power position connected enhancement type N-channel transistors and N-channel transistors of the first depletion type in the order between the output node 3, 7 between the V _CC input node 2 and the switching power level output node 3 a is connected between the drain and the source, a second depletion-type N-channel transistor having a gate to the write enable signal ▲ ▼ is applied, the above switching power level potential of the input node 1 is 0 to V _CC write from the potential potential 9 detection circuit for detecting that the transition to the V _PP, 5 is boosted to the boosted high predetermined potential than the write potential V _PP receives the detection output of the detection circuit 9 Booster circuit generates a force A1 is applied to the gate of the enhancement type transistors 6, 10 the write potential V _PP as a power source, and switching operation in response to the write enable signal ▲ ▼, switch output A2 (signal ▲ ▼ is Write potential V when active
_PP , 0V when signal ▲ ▼ is inactive. ) Is applied to the gate of the first depletion type transistor.

The switch circuit 10 includes, for example, an inverter circuit 20 to which a write enable signal
And a level conversion circuit 21 connected to the subsequent stage of the inverter circuit 20. This level conversion circuit 21 is for level-shifting the Vcc system signal to the Vpp system,
As shown in the figure, an inverter circuit 22 in the input stage, enhancement-type N-channel transistors 23 and 24, and enhancement-type P-channel transistors 25 and 26 are connected. Now, when the output of the inverter circuit 22 becomes “L” level (0 V), a current flows from the high potential Vpp via the transistors 26 and 23. Due to this current, the gate potential of the transistor 25 rises, which is Vpp−Vthp (Vthp
, The threshold voltage of the P-channel transistor). When the transistor 25 is on, the output node is charged by the high potential Vpp, and the switch output A2 becomes the write potential Vpp. When the potential of the output node reaches Vpp-Vthp, the transistor 26 is turned off. At this time, transistor 25
Is also turned off, and there is no current outflow path from the high potential Vpp. On the other hand, when the output of the inverter circuit 22 becomes “H” level (5 V), the transistor 24 turns on,
The output node is discharged and switch output A2 goes to 0V.

In the V _PP / V _CC potential switching circuit, when the potential of the switching potential input node 1 transitions from 0 to V _CC potential to the writing potential V _PP , this change is detected by the detection circuit 9, and the booster circuit 5 detects the change in the detection circuit. 9, a boosted output A boosted to a predetermined potential (for example, 16 V) higher than the write potential _VPP in response to the detected output 9
1 is generated and applied to the gate of the enhancement transistor 6. Therefore, when the write potential V _PP is applied to the switching potential input node 1, the enhancement type transistor 6 is turned on, and the enhancement type transistor 6 and the first depletion type transistor 8 are turned on.
The series connection nodes, (without loss due to the threshold voltage) as applied potential V _PP for altering position input node 1 through enhancement transistor 6 appears.

At this time, assuming that the write enable signal ▼ is inactive (5V in this example), the switch output A2 of the switch circuit 10 becomes 0V, and the first depletion type transistor 8 is turned off. At this time, the second depletion-type transistor 7 is turned on by 5V is applied to the gate, the switching power level output node 3, V _CC
The applied potential V _CC of the input node 2 appears.

Contrary to the above, when the write enable signal ▲ ▼ is (0V in this embodiment) activated state switch output A2 of the switch circuit 10 becomes V _PP potential, a first depletion type transistor 8 is turned on . At this time, the second depletion type transistor 7 is turned off by applying 0V to the gate. Therefore, the switching power level output node 3, the applied potential V _PP for altering position input node 1 appears through enhancement type transistor 6 and the first depletion type transistor 8.

At the time of reading, the booster circuit 5 does not perform the boosting operation, since the boosted output A1 is to 0V, and enhancement type transistor 6 is turned off, the current path from V _CC input node 2 to the switching power level input node 1 It is cut off regardless of the potential of the switching potential input node 1.

According to the V _PP / V _CC potential switching circuit, the boosting speed of the boosting circuit 5 is low, and the inverter circuit 20 and the level conversion circuit
The switch circuit 10 composed of 21 operates at high speed. And
The boosting operation of the booster circuit 5 is completed when the write potential _VPP transitions to the high potential, and the subsequent non-write and write operations are controlled by the high-speed switch circuit 10. Therefore, at the time of writing, the enhancement-type transistor 6 boosted output A1 of higher potential than the write voltage V _PP is applied to the gate from the booster circuit 5 are turned on, the switch circuit in this state
The output of the write potential V _PP from 10 is applied to the gate.
When the depletion type transistor 8 is turned on,
Write potential V _PP for altering position input node 1 is to appear in the altering position output node 3 at a high speed.

In the above embodiment, the case where the enhancement type transistor 6 and the depletion type transistor 8 are connected between the switching potential input node 1 and the switching potential output node 3 in this order is shown. In short, they may be connected in series.

Further, in the embodiment, although the case of applying the V _PP potential altering position input node 1 when directly writing from the outside of the chip, the step-down to the altering position input a write voltage applied from the outside of the chip in the chip You may make it apply to node 1.

Further, in the above embodiment, the V _PP / V _CC potential switching circuit is shown. However, the present invention is not limited to this, and the write potential of the write potential input node to which the write potential is applied at the time of writing in the semiconductor nonvolatile memory device. Can be selectively output to a write potential output node for selectively extracting a write potential for the inside of the chip.

[Effects of the Invention] As described above, according to the present invention, when the write potential is selected using the boosted output of the booster circuit that generates a voltage higher than the write potential to extract the write potential for the inside of the chip, for example, By applying the present invention to a V _PP / V _CC potential switching circuit in an EPROM or an EEPROM, a write potential can be selected at a high speed, and a semiconductor nonvolatile memory device which can sufficiently cope with a high-speed write operation can be realized.

[Brief description of the drawings]

FIG. 1 shows V _PP / V in a semiconductor nonvolatile memory device of the present invention.
FIG. 2 is a circuit diagram showing an embodiment of a V _CC potential switching circuit, and FIG. 2 is a circuit diagram showing a V _PP / V _CC potential switching circuit in a conventional EPROM. 1 ... Switching potential input node, 2 ... V _CC input node, 3
... Switching potential output node, 5 ... Boost circuit, 6 ... Enhancement type N-channel transistor, 7 ... Second
Depletion-type N-channel transistors, 8 ...
... First depletion type N-channel transistor, 9 ... Detection circuit, 10 ... Switch circuit, 20, 22 ...
Inverter circuit, 21 Level conversion circuit, 23, 24 Enhancement type N-channel transistor, 25, 26 ...
... An enhancement type P-channel transistor.

Claims (2)

(57) [Claims] An enhancement type transistor and a dip connected in series between a write potential input node to which a write potential is applied at the time of writing and a write potential output node for selectively extracting a write potential for the inside of a chip. A writing transistor, a booster circuit for generating a boosted output boosted to a predetermined potential higher than the write potential and applying the boosted output to the gate of the enhancement transistor at the time of writing, A switch circuit that performs a switch operation in response to a signal and applies a switch output to the gate of the depletion type transistor. 2. A switching potential input node to which a writing potential / reading potential is applied corresponding to a writing / reading operation and a switching potential output node for selectively taking out the writing potential or the reading potential are connected in series. The enhancement-type transistor and the first depletion-type transistor, connected between a read power supply input node to which a normal read power supply potential is applied and the switching potential output node,
A second depletion-type transistor having a gate to which a write enable signal is applied; and a write-up output which is boosted to a predetermined potential higher than the write potential during writing and applied to the gate of the enhancement-type transistor. A booster circuit; and a switch circuit that uses the write potential as a power supply, performs a switch operation in response to the write enable signal, and applies a switch output to the gate of the first depletion type transistor. The nonvolatile semiconductor memory device according to claim 1.