JP2856120B2 - Differential amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit comprising a pair of differential amplifiers for generating four-phase signals, and more particularly to correcting a phase difference between respective differential amplifiers. The present invention relates to a differential amplifier circuit capable of performing the following.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a conventional differential amplifier circuit of this kind. It has a first differential amplifier 1 and a second differential amplifier 2. Each of the differential amplifiers 1 and 2 is connected to a common input bias circuit 3, and has a common input signal terminal IN and a common reference signal terminal. It is connected to RS and to power supply E. In this differential amplifier circuit, output signals having phases different from each other by 180 degrees are output from the differential amplifiers 1 and 2. That is, the first differential amplifier 1 is configured as an emitter resistance feedback differential amplifier, and includes the transistors Q11 and Q12 and the resistor R1.
1, R12, constant current sources I11 and I12, and a resistor R13 connected between both emitters. Also, the second
Is configured as an emitter capacitance feedback type differential amplifier, and includes transistors Q21 and Q22 and a resistor R2.
1, R22, constant current sources I21 and I22, and a capacitor C21 connected between both emitters. The input bias circuit 3 includes a constant current source I31 and resistors R31 and R3.
2, R33.

In this differential amplifier circuit, the first differential amplifier 1
And the second differential amplifier 2 are all the same except for the resistance R13 and the capacitance C21, so that the respective outputs OUT11, OUT12
And OUT21 and OUT22 have a phase difference of 90 degrees of the phase difference generated by the resistor R13 and the capacitor C21. That is, when the outputs OUT11 and OUT12 of the first differential amplifier 1 are set to 180 ° and 0 °, the outputs OUT21 and OUT22 of the second differential amplifier 2 become 9 °.
0 ° and 270 °. At this time, the input frequency at which the phase difference becomes 90 degrees is determined by the time constant of the resistor R13 and the capacitor C21.

[0004]

In such a conventional differential amplifier circuit, the phase difference (90 °) between the outputs of the differential amplifiers 1 and 2 is determined by the time constant determined by the resistor R13 and the capacitor C21. Therefore, when a manufacturing error occurs in the resistance value of the resistor R13 or the capacitance value of the capacitor C21, the time constant is changed to a phase difference other than 90 °, and the phase difference becomes 90 °.
However, there is a problem that four phase signals having different phases cannot be output.

For this reason, a technique for correcting the phase has been conventionally proposed. For example, JP-A-3-26014
In Japanese Unexamined Patent Publication (Kokai) No. 61-232709, a variable capacitance element (junction capacitance) is connected in place of the capacitance C21 provided in the differential amplifier, and a bias applied to the variable capacitance element is adjusted to reduce the capacitance. A technique is described in which the time constant is changed by making it variable, and the phase is adjusted as a result. Therefore, this technique is applied to the capacitor C2 shown in FIG.
If used instead of 1, phase adjustment is possible.

In the techniques described in these publications, the bias of the variable capacitance element is controlled by an external control, and there is no mention of how to perform the control. Will be. However, the capacitance sensitivity of the variable capacitance element is usually sensitive to the bias voltage, and the capacitance value is greatly changed by a very slight change in the bias voltage. It is almost impossible to apply the described technique to this type of differential amplifier circuit. SUMMARY OF THE INVENTION An object of the present invention is to provide a differential amplifier circuit capable of automatically performing phase adjustment and always ensuring phase correction without performing any adjustment work.

[0007]

SUMMARY OF THE INVENTION A differential amplifier circuit according to the present invention has a first differential amplifier of an emitter resistance feedback type and a second differential amplifier of an emitter capacitance feedback type. An input bias circuit of the amplifier and an input signal are commonly used to output a signal having a required phase difference from each differential amplifier, and the second differential amplifier has a pair of variable capacitors connected in opposite directions. And a voltage divided by a resistor having the same characteristic as the emitter resistance of the first differential amplifier is supplied to a connection terminal of the variable capacitance element as a bias voltage.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. A first differential amplifier 1 and a second differential amplifier 2
And a common input bias circuit 3 and a junction capacitance bias circuit 4 provided in the second differential amplifier 2 for adjusting a junction capacitance, which will be described later, and connected to the power supply E.
It is configured as a differential amplifier circuit that outputs four-phase difference signals. The configuration of the first differential amplifier 1 is the same as the conventional configuration shown in FIG.
, Resistors R11 and R12, and constant current sources I11 and I12
And a resistor R13 connected between the emitters.

The second differential amplifier 2 has the same configuration as the conventional one, and includes transistors Q21 and Q22 and a resistor R2.
1 and R22, and constant current sources I21 and I22.
Here, the junction capacitance Cx is used. This junction capacitance Cx
Is configured such that the bases of a pair of transistors Q23 and Q24 are common, the respective collectors are connected to the respective emitters of the transistors Q21 and Q22, and the emitters are open. A bias is supplied from the junction capacitance bias circuit 4 to the commonly connected bases.

The input bias circuit 3 comprises a constant current source I31 and resistors R31, R32, and R33 as in the conventional configuration. The junction capacitance bias circuit 4 includes transistors Q41 and Q42, a constant current source I41, and a resistor R42. In particular, the transistor Q41 has a collector connected to the power supply E and an emitter connected to a common connection base of the transistor pair Q23 and Q24 forming the junction capacitance Cx of the second differential amplifier 2. The base is a resistor R4
1, a common input signal terminal IN of each of the differential amplifiers 1 and 2
And the collector of the transistor Q42 is connected at the same time. The transistor Q42 has a base grounded and an emitter open. Here, the resistor R41 is connected to the transistor Q1 of the first differential amplifier 1.
A resistor having the same standard as the resistor R13 connected between the emitters of the transistors Q1 and Q12 is used. That is, when the differential amplifier circuit of the present embodiment is formed as an integrated circuit, resistors formed by the same process on the same semiconductor substrate are used as the resistors.

According to this circuit configuration, the first differential amplifier 1
And each output OUT11,12 of the second differential amplifier 2 and OUT
21 and 22 are the same as before in that a phase difference of the phase difference generated by the resistor R13 and the junction capacitance Cx occurs. When the phase difference caused by the time constant of the resistor R13 and the junction capacitance Cx is 90 °, the first differential amplifier 1
Are set to 180 ° and 0 °, the outputs OUT21 and OUT22 of the second differential amplifier 2 are 90 ° and 27 °, respectively.
0 °. When a manufacturing error occurs in the resistance value of the resistor R13, the time constant is changed, resulting in a phase difference other than 90 °, and it becomes impossible to output four phase signals having phases different from each other by 90 °. There is a risk.

However, when an error occurs in the resistance value of the resistor R13, almost the same error occurs in the resistance value of the resistor R41 of the same standard of the junction capacitance bias circuit 4. Here, in the junction capacitance bias circuit 4, as shown in FIG. 2, assuming that the DC amplification factor of the transistor Q41 is hFE, the base potential VB of the transistor Q41 is
In equation (1), the emitter voltage VA is represented by equation (2). VB = Vcc-R31 (I1 + I2 / hFE)-(R33 + R41) I2 / hFE (1) The voltage between the base and the emitter of Q41 is VBE. VA = Vcc-R31 (I1 + I2 / hFE)-(R33 + R41) I2 / hFE-VBE (2) This emitter voltage VA becomes the bias voltage of the junction capacitance CX.

Therefore, if an error occurs in the direction where the resistance value of the resistor R13 is larger, the resistance value of the resistor R41 also becomes larger. Therefore, according to the equations (1) and (2), the emitter voltage VA becomes And the bias voltage of the junction capacitance Cx is reduced. A transistor Q23 forming a junction capacitance,
Since the collector potential of Q24 is fixed, when the bias voltage is lowered, the reverse bias of the junction capacitance is increased.

On the other hand, the junction capacitance Cx is, as shown in FIG.
Since the characteristics are negative with respect to the reverse bias voltage, the capacitance value decreases as the reverse bias voltage increases. Accordingly, as the resistance value of the resistor R13 of the first differential amplifier 1 decreases, the junction capacitance Cx of the second differential amplifier 2 also decreases, so that the capacitance change characteristics of the junction capacitance Cx with respect to the reverse bias voltage can be appropriately adjusted. If set, the resistance R13 and the junction capacitance Cx
Will be kept constant. That is, the phase difference can always be kept constant irrespective of the error of the resistance, and the automatic correction of the phase is realized.

FIG. 4 is a circuit diagram of a second embodiment of the present invention. Here, a multiplication type phase comparator 5 and a junction capacitance bias compensation circuit 6 are added to the circuit of the first embodiment. The multiplication type phase comparator 5 is a known circuit composed of a differential amplifier composed of a pair of transistors. Here, each corresponding output from the first and second differential amplifiers 1 and 2, namely, Each output having a phase difference of 90 ° is compared, and a phase error in which the phase difference deviates from 90 ° is detected as an error voltage VC. The junction capacitance bias compensating circuit 6 includes an operational amplifier OP and resistors R61 and R62. The bias voltage VA from the junction capacitance bias circuit 4 and the error voltage VC from the multiplication type phase comparator 5 are used.
To output a compensation bias voltage VA ′ obtained by adding and subtracting the error voltage VC from the bias voltage VA.
Then, the compensation bias voltage VA 'is supplied to the junction capacitance Cx as a reverse bias voltage.

Accordingly, in this embodiment, the bias voltage VA 'generated by the error of the resistance is compensated by the error voltage VC actually generated by the phase error to obtain the bias voltage VA'. The phase error can be corrected automatically and with high accuracy.

[0017]

As described above, according to the present invention, the variable capacitance element provided in one differential amplifier for adjusting the phase between the differential amplifiers forming a pair is connected to the variable capacitance element provided in the other differential amplifier. A junction capacitance bias circuit that outputs the voltage divided by a resistor having the same characteristics as the emitter resistance as the bias voltage of the variable capacitance element is provided. The resistance value of the pressure resistor is also varied, so that the bias voltage can be automatically corrected, and the phase error can be automatically compensated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining an operation of generating a bias voltage.

FIG. 3 is a diagram showing a reverse bias characteristic of a junction capacitance.

FIG. 4 is a circuit diagram according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional differential amplifier circuit.

[Explanation of symbols]

 Reference Signs List 1 first differential amplifier 1 second differential amplifier 3 input bias circuit 4 junction capacitance bias circuit 5 multiplication type phase comparator 6 junction capacitance bias compensation circuit Cx junction capacitance

Claims (5)

(57) [Claims] A first transistor comprising a pair of transistors;
An emitter resistance feedback type first differential amplifier having an emitter resistance connected between the emitters of the transistors , and a pair of transistors
And connect a capacitor between the emitters of each transistor.
And a second differential amplifier of the emitter capacitive feedback was, before
In a differential amplifier circuit that outputs a signal having a required phase difference from each differential amplifier while sharing an input signal with an input bias circuit of each differential amplifier, the capacitances of the second differential amplifiers are connected in opposite directions. Composed of a pair of variable capacitance elements,
A differential amplifier circuit, wherein a voltage divided by a resistor having the same characteristic as the emitter resistance of the first differential amplifier is supplied as a bias voltage to a connection terminal of the variable capacitance element. Wherein said variable capacitance element, the base of the two transistors of the capacitor which is open emitter - is composed of the collector, the Kore <br/> Kuta said second differential transistors for these capacities It is connected to the emitters of said pair of transistors constituting the dynamic amplifier, Trang for the capacity
2. The differential amplifier circuit according to claim 1 , wherein the bases of the transistors are connected to each other and supplied with the bias voltage. 3. A error equal resistance of the emitter resistor and the resistance value of said first differential amplifier, the base relative to the resistance - emitter the input signal terminal and a transistor for bias connected in series with the ground Connect between and for the bias
The differential amplifier circuit according to claim 1 or 2 to be supplied to the variable capacitance element emitter voltage as the bias voltage of the transistor. 4. A first transistor and a second transistor, wherein the first differential amplifier and the second differential amplifier are respectively a first transistor and a second transistor.
In constructed, each base of the first transistor is connected to the input signal terminal, the base of each second transistor is connected to the input bias circuit, first及 of the first differential amplifier
And each emitter of the second transistor is connected to the emitter resistor.
And the respective emitters of the first and second transistors of the second differential amplifier are connected by the variable capacitance element.
The first and second transformers of the first and second differential amplifiers, respectively.
Extracting output from the collector of the transistor
The differential amplifier circuit according to claim 1 . 5. A phase comparator for detecting a phase error between outputs of said first and second differential amplifiers, and a compensation circuit for compensating said bias voltage by an error voltage output from said phase comparator. The differential amplifier circuit according to claim 4, comprising: