JP2852170B2 - Policing circuit by scheduling reset - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an ATM (Asynch).
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a policing circuit system based on scheduling reset for policing control in a roaming transfer mode (asynchronous transfer mode) network.

[0002]

2. Description of the Related Art Referring to FIG. 4, in a conventional policing circuit system based on the TX system, it is determined whether or not a VP to be monitored is determined from a VPI number of an input cell a, and if the VP is a VP to be monitored, a counter is incremented by +1. A counter 31 for updating and outputting a counter value X of the current number of input cells as a counter output signal n;
Register 33 for outputting the threshold value as threshold signal p
And a threshold signal p from the threshold register 33 and a counter output signal n from the counter 31 to compare the threshold value Y with the counter value X and output a discard instruction signal b. And a T time timer 3 that measures the T time (unit: one cell time) and outputs a reset signal q every T time
4 and a discard processing unit 35 that discards the input cell and outputs an output cell c according to the discard instruction signal b from the comparison unit 32.

More specifically, referring to FIG. 5 and FIG. 4, the counter 31 determines whether or not the VP is the monitoring target VP from the VPI number of the input cell a, and if the VP is the monitoring target VP, updates the counter by +1. At the same time, the counter value X is output as a counter output signal n. The comparator 32 receives the threshold signal p from the threshold register 33 as the threshold Y of the allowable number of input cells in the T time of the VP, and uses the counter output signal n from the counter 31 as the current number of input cells. The threshold value Y is input as the counter value X, and the threshold value Y is compared with the counter value X. When the counter value X is larger than the threshold value Y, the discard processing unit 35 instructs the discard processing unit 35 to discard the input cell a. An instruction signal b is output. The discard processing unit 35 discards the input cell a according to the discard instruction signal b from the comparison unit 32 and outputs the output cell c. The T time timer 34 measures the T time (unit: one cell time), outputs a reset signal q every T time, and instructs the counter 31 to reset. The counter 31 resets the counter value X to “0” by the reset signal q.

As described above, in the conventional policing circuit system based on the TX system, the number of input cells X of the VP in a certain period T for each VP is counted and counted as a counter value X. Is a predetermined threshold Y
If the input cell a is exceeded, the input cell a is discarded. Also,
In this conventional system, since there is no correlation between reset intervals such as T1 and T2, there is a case where a plurality of VPs are reset within one cell time.

[0005]

In the conventional policing circuit system based on the TX system, when this circuit system is provided for each VP, the overall hardware scale becomes extremely large. In the case of the multiplex processing method used, it is difficult to simultaneously reset the number of input cells of a plurality of VPs every T periods.

[0006]

A policing circuit system by scheduling reset according to the present invention is a policing circuit system based on a TX method for controlling the number X of input cells in a monitoring period T time. A memory for storing and holding the number of input cells of the VP X value, and defining the T time of each item to be an integral multiple of "the total number of VPs to be monitored" x "one cell time", and the VPI number of the input cell From the respective VPs stored in the memory from
The first control signal indicating the reset target VPI number and the second control signal indicating the presence or absence of the reset are input, and the reset in the memory is performed in response to the second control signal. Memory access means for resetting the X value of the target VP; scheduling reset means for supplying the first control signal and the second control signal to the memory access means; Threshold table storing means for holding a threshold value, and the input cell number X value of the input cell number of each VP from the memory and the threshold value from the threshold table storing means, Comparing means for comparing and determining the X value with the threshold value and outputting a third control signal; and discarding the input cell in response to the third control signal from the comparing means to output the third control signal. And a cell discard processing means for outputting.

In the policing circuit system based on scheduling reset according to the present invention, the scheduling reset unit counts up to a value of "the number of all VPs to be monitored" by a cell clock, and then sets "0".
And a cell counter that outputs the count value as the reset target VPI number again, and outputs the reset target VP from the cell counter.
An item selection table storing means for receiving an I number d, determining an item to which the VP belongs, and outputting a select signal for selecting a timer of the item, and counting by counting all VP number count signals from the cell counter as a trigger A plurality of timers each outputting a first reset presence / absence signal with an attribute of “reset present” only when counting up to a predetermined count value, and a first timer input from each of the plurality of timers. A reset presence / absence signal is input, selects one of the corresponding first reset presence / absence signals in response to the select signal from the item selection table storage means, and outputs it as a second reset presence / absence signal to the memory access means. And a selector for supplying.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. Referring to FIG. 1 showing an embodiment of the present invention, a policing circuit scheme based on scheduling reset is a VP circuit.
A memory 12 for storing and holding the input cell number X value of each VP corresponding to the I number, and setting the T time of each item to an integral multiple of “the total number of VPs to be monitored” × “1 cell time” From the VPI number of the specified input cell a, the input cell number X value of each VP stored and held in the memory 12 is counted up in the first half timing section 103 within one cell time, and the VPI number d to be reset and the presence or absence of reset are set. The memory access unit 1 that receives the signal m and resets the X value of the VP of the reset target VPI number to “0” in the memory 12 when the attribute of the reset presence / absence signal m is “with reset”.
1, a scheduling reset unit 15 that outputs a reset target VPI number d and a reset presence / absence signal m to reset each VP at a T period defined for each VP and supplies them to the memory access unit 11, Threshold value table storage unit 13 for holding threshold value Y of input cell number X value
And the input cell number X value of each VP is input from the memory 12 as the cell numerical signal e, and the threshold value Y of the input cell number X value is input as the threshold signal f from the threshold table storage unit 13. A comparison unit 14 for comparing and judging the number X of input cells with a threshold Y to output a discard instruction signal b;
And a discard processing unit 16 that outputs the output cell c.

Referring to FIG. 2 in conjunction with FIG.
The memory access unit 11 counts up the input cell number X value of the VP stored in the memory 12 from the VPI number of the input cell a in the first half timing section 103 within one cell time. The comparison unit 14 stores the V
The input cell number X value of P is input as a cell numerical signal e,
The threshold value Y of the input cell number X value of the VP is input as a threshold signal f from the threshold table storage unit 13, and the input cell number X value and the threshold value Y are compared and determined. If the number X of input cells is larger than Y, a discard instruction signal b for discarding the input cell a is output to the discard processing unit 16. The discard processing unit 16 discards the input cell a in response to the discard instruction signal b from the comparison unit 14 and outputs the output cell c. The memory access unit 11 sends the reset target VPI number d from the scheduling reset unit 15
When the attribute of the reset presence / absence signal m is “with reset” in the second half timing section 104 within one cell time, the X value of the VP of the reset target VPI number in the memory 12 is set to “0”. Reset to "."

Further, the processing timing of the policing circuit system by the scheduling reset according to the present invention will be described with reference to FIG. The T time of each item is defined as an integral multiple of “the total number of VPs to be monitored” × “one cell time”.
101 is “the number of all VPs to be monitored” × “1 cell time”
Indicates the time in minutes. Reference numeral 102 denotes one cell time, which is divided into a first half timing section 103 and a second half timing section 104. Here, the count of the input cell number X value of the VP of the input cell is counted up at the timing of 103, and the X value is reset at the timing of 104 in the T cycle specified for each item in each VP. Now, the number of all VPs to be monitored is 1
000. The monitoring sections T1 and T3 of VP = 1, 3
000, VP = 2, the monitoring section T2 is 2000 and VP
= 4, the monitoring section T4 is set to 3,000 at time 0.
= 1 is reset to 0, and at time 1 VP = 2 X
The value is reset. At time 2, the X value of VP = 3 is reset, and at time 3, the X value of VP = 4 is reset. Hereinafter, at time 1000, the X value of VP = 1 is reset, but at time 1001, the X value of VP = 2 is not reset.
Thus, only one VP needs to be reset in one cell time.

Next, referring to FIG. 3 showing an embodiment of the scheduling reset unit 15 of the policing circuit system by the scheduling reset according to the present invention, the scheduling reset unit 15 determines the number of all VPs to be monitored by the cell clock g. , And then repeat the same count-up again from "0" and supply the count value to the memory access unit 11 as the reset target VPI number d. Item selection table storage unit 22 which receives d, determines the item to which the VP belongs, and outputs a select signal j for selecting a timer of the item, and counts all the VP count signals h from cell counter 21 as a trigger. Up to a predetermined count value And a timer 23-1~23-N to each each output in the attribute of "Reset Yes" to reset only the presence or absence signal k-1~k-N at the time of the count, timer 23-1～2
Each of the reset presence / absence signals k-1 to k-N is input from 3-N, and one of the corresponding presence / absence signals k-1 to k-N is selected according to the control signal j from the item selection table storage unit 22. And a selector 24 which outputs the reset presence / absence signal m and supplies it to the memory access unit 15.

More specifically, the cell counter 21 counts up to the value of "the number of all VPs to be monitored" by the cell clock (period = 1 cell unit time) g, and then starts counting up again from "0". repeat. The count value of the cell counter 21 is the reset target VPI number d.
Is supplied to the memory access unit 11. The item selection table storage unit 22 receives the reset target VPI number d from the cell counter 21, determines the item to which the VP belongs, outputs a select signal j for selecting a timer of the item, and supplies it to the selector unit 24. . The selector unit 24 outputs a timer output corresponding to the control signal j from the item selection table storage unit 22 from among the reset presence / absence signals k-1 to kN input from the timers 23-1 to 23-N of each item. Is output as the reset presence signal m and supplied to the memory access unit 11. When the cell counter 21 counts up to the value of “the number of all VPs to be monitored”, the cell counter 21 outputs the total VP number count signal h to the timers 23-1 to 23-23.
-N. The timers 23-1 to 23-N count up using the total VP count signal h input from the cell counter 21 as a trigger, and only when the count reaches a predetermined count value, the reset presence / absence signals k-1 to k-k
−N is supplied to the selector unit 24 with the attribute of “with reset”.

By this processing, it is determined whether or not the X value should be reset for each VP within "the total number of VPs to be monitored" x "one cell time" which is the unit of the T time of each item. A reset function can be realized.

[0014]

As described above, according to the present invention, the T time of each item is defined as an integral multiple of "the total number of VPs to be monitored" x "one cell time". Within 1VP
By scheduling and resetting each V
By enabling the reset of the T cycle of the number X of input cells of P, a policing circuit having a circuit configuration of a multiplexing process using a memory can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a policing circuit system by scheduling reset according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining processing timing of a policing circuit method by scheduling reset according to the embodiment, and FIG. 2A is a diagram illustrating an example of a cyclic reset timing; FIG. 4B is a diagram showing a cell row in (“the total number of VPs to be monitored” × “one cell time”) 101. (C)
FIG. 4 is a diagram showing an example of the timing of time division processing within one cell time.

FIG. 3 is a block diagram showing an embodiment of a scheduling reset unit of the policing circuit system by scheduling reset according to the embodiment;

FIG. 4 is a block diagram showing a conventional policing circuit method by scheduling reset.

FIG. 5 is a diagram showing an example of processing timing in a conventional policing circuit system by scheduling reset.

[Explanation of symbols]

 Reference Signs List 11 memory access unit 12 memory 13 threshold table storage unit 14 comparison unit 15 scheduling reset unit 16 discard processing unit 21 cell counter 22 item selection table storage unit 23-1 to 23-N timer 24 selector unit a input cell b discard instruction Signal c Output cell d Reset target VPI number e Cell numerical signal f Threshold signal g Cell clock h All VP count signal j Selector signal k-1 to k-N Reset presence signal m Reset presence signal

Continuing on the front page (72) Inventor Naoaki Yamanaka 1-6-1, Uchisaiwaicho, Chiyoda-ku, Tokyo Inside the Telegraph and Telephone Corporation (72) Inventor Yoichi Sato 1-6-1, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Telephone Co., Ltd. (56) References JP-A-5-268239 (JP, A) IEICE Technical Report CS 91-89 (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 12 / 28 H04L 12/56 JICST file (JOIS)

Claims (2)

(57) [Claims] 1. A policing circuit system based on a TX method for controlling the number X of input cells during a monitoring period T, a memory for storing and holding the number X of input cells of each VP corresponding to a VPI number; The T time of an item is defined as an integral multiple of “the total number of VPs to be monitored” × “one cell time”, and the VPI of the input cell is defined.
The number of input cells X of each VP stored and held in the memory is counted up from the number, and a first control signal indicating a reset target VPI number and a second control signal indicating whether or not to reset are counted. Memory access means for resetting the X value of the reset target VP in the memory in response to the input second control signal; and supplying the first control signal and the second control signal to the memory access means. Scheduling reset means; threshold table storage means for holding a threshold value of the input cell number X value of each VP; input cell number X value of each VP from the memory and the threshold table storage means Comparing means for receiving the threshold value from the input device and comparing the input cell number X value with the threshold value and outputting a third control signal; And a cell discarding means for discarding the input cell and outputting an output cell in response to a third control signal from the control circuit. 2. The scheduling reset section counts up to a value of "the number of all VPs to be monitored" by a cell clock, repeats the same count-up from "0" again, and resets the count value to the VPI number to be reset. A cell counter which outputs the reset target VPI number d from the cell counter, determines an item to which the VP belongs, and outputs a select signal for selecting a timer of the item; A plurality of timers each outputting a first reset presence / absence signal with an attribute of “reset present” only when counting up to a predetermined count value using a total VP number count signal from the cell counter as a trigger; A first reset presence / absence signal input from each of the plurality of timers; A selector which selects one of the first reset presence / absence signals corresponding to the selected reset presence / absence signal in response to the select signal from the item selection table storage means and outputs the second reset presence / absence signal as a second reset presence / absence signal; 2. The policing circuit system according to claim 1, further comprising: