JP2846536B2 - Multiprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor including a plurality of CPU cores, and more particularly, to a multiprocessor having a plurality of CPU cores having different instruction processing systems.

[0002]

2. Description of the Related Art Generally, a microprocessor includes an instruction processing unit including a register, a decimal operation unit,
It comprises a data and instruction cache unit and a floating point operation unit. The microprocessor prepares various variations of instructions in order to cope with detailed processing in terms of the computer architecture, and a processor system for executing complicated processing using a plurality of cycles with one instruction, and a minimum required number of instructions. It can be classified into a processor system in which only instructions are prepared and each of these instructions can be issued in one cycle.

[0003] The former is generally called a CISC processor, which corresponds to a 370 architecture processor of IBM Corporation, an X86 architecture processor series of Intel Corporation, and the like. Also, the latter is generally R
Called the ISC processor, SUN SPARC
The architecture processor, the PA-RISC architecture processor of HP, and the S-3800 vector processor of HITACHI, which exclusively performs vector operation processing, correspond to this.

[0004] The 370 and X86 architectures described above have achieved great commercial success. Therefore, the application program assets owned by the user are enormous. On the other hand, some of the latter types of RISC processors have made it possible to store the main part of the processor on a single LSI chip due to the advancement of semiconductor technology, and to use an excellent compiler technology specialized in processor architecture. And the machine cycle is number 1
It is possible to increase to the order of 00 MHz. For this reason, RISC processors have made great strides in terms of data processing performance and are becoming commercially successful.

A processor including a plurality of CPU cores is generally a multiprocessor constituted by connecting only a plurality of CISC processors in the case of a CISC processor and a plurality of RISC processors in the case of a RISC processor. Is performed to perform a parallel operation, thereby improving the performance.

As a conventional technique relating to this type of multiprocessor, for example, a technique described in Japanese Patent Application Laid-Open No. 2-264352 is known.

[0007]

In recent years, with the advancement of excellent compiler technology and semiconductor technology, the performance of RISC processors has been dramatically improved, and there has been a demand for CISC processor users to use RISC processors. Is growing. However, for CISC processor users, the vast amount of CISC
Discard processor application program assets and R
Moving to an ISC processor is not easy.

In the prior art described above, the processor is configured under one type of architecture, so that the CISC
There is a problem that a processor user cannot migrate to a RISC processor by using a previous CISC processor application program asset.

On the other hand, a RISC processor can efficiently execute a register operation instruction, a floating point operation instruction, etc., but has low performance in processing such as frequent occurrence of memory access and branch instructions. In addition, because of the complicated data processing performed by combining the above, there is a problem that the object of the instruction generated by the compiler becomes large and the memory use efficiency is deteriorated.

An object of the present invention is to provide the above-mentioned prior art and RIS.
It solves the problems of the C processor, makes use of the CISC processor application program resources, and provides RIS for RR-type operations and floating-point operations.
An object of the present invention is to provide a multiprocessor that performs more efficient data processing using a C processor.

[0011]

According to the present invention, the object is to connect processors having different architectures,
This is achieved by switching both processors by a microprogram, that is, by integrating a CPU core of a CISC processor and a CPU core of a RISC processor to form a multiprocessor.

A processor for achieving the above object of the present invention comprises: a means for incorporating a CPU core of a CISC processor and a CPU core of a RISC processor in a multiprocessor configuration;
Means for activating a CPU core of an SC processor;
The C processor includes means for reporting the completion of processing from the C processor to the CISC processor, and a RISC processor enable bit indicating whether or not the RISC processor operation is valid. The processing can be switched.

[0013]

In a normal operation, the CPU core of the CISC processor configured in the multiprocessor fetches an instruction from a cache, and performs instruction decoding and execution control. At this time, at the same time, the RI
The CPU core of the SC processor also fetches instructions in the same manner, but the RISC processor Enabie bit indicating whether the operation of the RISC processor is valid is set to devolt O.
Since it is set to FF, the register update and resource control processing of the CPU core of the RISC processor are not effective.

The above-mentioned register is a general-purpose register,
Floating point registers, and resources are an arithmetic unit and a memory control unit.

By the way, the CISC processor can execute all the conventional instruction sequences (object codes), and the CPU core of the RISC processor can execute an RR type operation instruction and a floating point operation. It is possible.

When the multiprocessor according to the present invention is used, a processing instruction sequence that the RISC processor excels in, such as a register operation instruction and a floating point operation instruction, is represented by R
Generated so that ISC processor processing is continuous,
By causing the RISC processor to process these instruction strings, the processing performance of the entire multiprocessor can be improved.

For this reason, a register operation instruction, a floating point operation instruction, and the like in a source list of a program created to be processed by a conventional CISC processor.
The processing instruction sequence that the ISC processor is good at is RISC
It is necessary to compile so that processor processing is continuous. The generation of the instruction sequence by the compilation can be performed by a conventionally known compiler. Such compiler technology is, for example, a vector type supercomputer S-810 and S-810 manufactured by HITACHI.
820, S-3800 and the like.

In the present invention, when compiling the source list of the above-mentioned program by a compiler, a start instruction for starting the CPU core of the RISC processor from a CPU core of the CISC processor and an instruction for operating the CPU core of the RISC processor Columns and RISC
CIS when the operation of the CPU core of the processor is completed
A return instruction for handling processing is generated in the CPU core of the C processor.

The start instruction starts a microprogram, and by this microprogram start, a RISC processor Enable bit indicating whether or not the RISC processor operation is valid is turned ON. Thus, the RISC processor executes an instruction sequence following the activation instruction to operate the CPU core of the RISC processor.

The return instruction at the end of the sequence of instructions for operating the CPU core of the RISC processor is CI
A microprogram which is decoded by the SC processor and executes the processing completion report is started. With this, RI
RISC indicating whether SC processor operation is valid
The processor enable bit is turned off, and the RISC
The data processing of the processor is invalidated as described above, and the processing is handled by the CISC processor.

According to the present invention, as described above, the processing can be switched between the CISC processor and the RISC processor, the conventional application program can be effectively used, and the efficient processing utilizing the features of the RISC processor can be achieved. Can be executed.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a multiprocessor according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of one embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of an instruction execution control unit, and FIG. 3 is an instruction for explaining an example of the operation of the present invention. FIG. 4 is a flowchart illustrating an example of a column, and FIG. 4 is a flowchart illustrating processing of a start instruction and a return instruction. 1 and 2, 10 and 15 are flags, 20 and 120 are instruction execution control units (I-Contrl), and 25 and 125 are branch control units (Branch-Contrl).
rol), 26 and 126 are adders (Add), 30 and 130 are control registers (C-Registr), 40 and 140 are general-purpose registers (G-Registr), and 50 and 150 are floating-point registers (F-Registr). Register), 60, 160 are cache control (Cache-Control), 70 is cache memory (Cache),
80 is a control memory (CS), 90 is an address counter (IA),
100 is a CISC processor and 200 is a RISC processor.

One embodiment of the present invention shown in FIG.
CPU core (hereinafter, referred to as CISC processor) 100 of the processor, CPU core (hereinafter, referred to as RISC processor) 200 of the RISC processor, and 1-bit RISC-ENABLE for controlling all operations shared by both of these processors It comprises a flag 10 and a cache memory 70. The flag 10
May have a multi-bit configuration, but a 1-bit configuration is the most efficient.

The CISC processor 100 includes an instruction execution control unit 20, a control register group 30, a general-purpose register group 40,
Floating point register group 50, cache control 6
0 and a control memory 80 in which a microprogram is stored. The RISC processor 200 includes an instruction execution control unit 120, a control register group 130, a general-purpose register group 140, a floating-point register group 150, a cache control 160, and the like.

In the embodiment of the present invention configured as described above, both processors are connected to one CHIP LSI.
Or a plurality of LSIs. When the present invention is configured by a plurality of LSIs, the present invention provides a
00 and 00 can be configured by one LSI, respectively, and the cache memory 70 can be configured to be shared outside the LSI.

When the RISC-ENABLE flag 10 is "0", the multiprocessor of the present invention configured as described above activates the register access 121 from the instruction execution control unit 120 in the RISC processor 200 and the cache control 160 Of the RIS even if the cache access activation 161 of the
An operation is performed so that these processes in the C processor 100 are not validated. That is, in this case, the AND gate in the RISC processor 200 is inhibited,
Since the output of the AND gate does not become “1”, the register access activation 121 and the cache access activation 161 are not valid, the processing in the RISC processor 200 is ignored, and the processing in the CISC processor 100 is valid.

Conversely, RISC-ENABLE flag 10
Is "1", the AND gate in the RISC processor 200 outputs a valid access activation,
When this flag is “1”, the AND gate in the processor 100 does not validate the outputs of the register access activation 21 and the cache access activation 61. That is, in this case, the RISC processor 200 is enabled, and the processing in the CISC processor 100 is
As will be described later, the Return provided by the present invention.
Invalid except for the CISC instruction.

Flag 15 in CISC processor 100
Is set to “1” by means not shown when a Return CISC instruction which is a return instruction is issued,
CISC regardless of the value of the C-ENABLE flag 10
This makes the processing in the processor 100 effective.

Although not shown, the cache memory 70 includes an instruction cache and a data cache, and the cache control 60 or 160 of each of the processors 100 and 200, the instruction execution control unit 120 or 1
Under the control of 20. Similarly, the microprogram stored in the control memory 80 is stored in the CISC processor 10.
It is involved in part or all of the control of each unit within 0.

Next, with reference to FIG. 2, the execution control units 20 and 120 of the programs of the CISC processor 100 and the RISC processor 200 will be described.

The CISC processor 100 and the RISC processor 200 use the same address counter 90 as a program address counter. The update of the address counter 90 is performed by RISC-ENABLE.
It is switched by the flag 10. That is, CISC
During the operation of the processor 100 (when the RISC-ENABLE flag 10 is “0”), the address counter 90
The address is updated by the value obtained by adding the address counter 90 and the instruction length L27 decoded in the CISC processor 100 by the adder 26 or the value calculated by the branch control unit 25, and when the RISC processor 200 operates (RISC-ENABLE). When the flag 10 is "1"), the address counter 90 and the RISC processor 20
It has been updated with the value obtained by adding the instruction length “4” in 0 by the adder 126 or the value calculated by the branch control unit 125.

Other resources such as general-purpose registers are as follows.
Each processor is provided individually. And, of course, these contents may be copied, but in one embodiment of the present invention, the program is
It is assumed that when switching with the ISC processor 200, the centralized management is performed through the main memory.

Next, with reference to FIG. 3 and FIG. 4, an operation when the multiprocessor according to the above-described embodiment of the present invention processes the CISC processor application program owned by the user will be described.

In FIG. 3, reference numeral 300 denotes an instruction sequence of the CISC processor application program held by the user.
Is a sequence of instructions that can be executed efficiently by the RISC processor. This C
The user having the ISC processor application program 300 can use a known compilation technique in advance.
The above-described instruction sequence 302 is compiled into an instruction sequence 401 capable of operating a RISC processor.

At this time, at the beginning of the instruction sequence 401, an Execute RISC instruction 400 which is a start instruction for shifting the processing to the RISC processor provided by the present invention.
Also, at the end thereof, Return which returns processing to the CISC processor provided by the present invention and serving as a return instruction
A CISC instruction 450 is added.

As a result, the instruction sequence to be processed by the multiprocessor according to the embodiment of the present invention includes an instruction sequence 301 to be processed by the CISC processor, an Execute RISC instruction 400, and an instruction sequence 40 to be processed by the RISC processor.
1, a Return CISC instruction 450 and an instruction sequence 303 to be processed by the CISC processor are arranged in this order.

When the instruction sequence as described above is processed by the multiprocessor of one embodiment of the present invention, the flags 10 and 15 in the embodiment shown in FIG. Is set.

When the execution of the processing of the instruction sequence is started, the processing of the CISC processor 100 becomes effective because the flag 10 is set to "0" as described above, and the instruction execution in the processor is executed. The control unit 20 sequentially executes the processing of the instruction sequence 301 described above. At this time, RI
The same instruction sequence is given to the instruction execution control unit 120 of the SC processor 200, but this control is invalidated as described above.

When the processing of the CISC processor 100 proceeds and the Execute RISC instruction 400 is executed, the microprogram is executed as shown in FIG.
After execution of the serialization process 410, the RISC-
A process 420 for setting the ENABLE flag 10 to "1" is executed.

By this processing, the processing of the RISC processor 200 becomes effective thereafter, and the CISC processor 10
0 is invalidated, and control is switched from the CISC processor 100 to the RISC processor 200. Thereafter, the above-described processing of the instruction sequence 401 is performed. In this processing, the processing of the RISC processor 200 is validated and the RISC processor 200 executes the processing.

The processing of the RISC processor 200 proceeds,
When the Return CISC instruction 450 is issued, the control of the instruction execution control unit 20 of the CISC processor 100 is enabled only for this instruction, and the microprogram executes the serialization processing 460 as shown in FIG. Is executed, the RISC-ENABLE flag 1
A process 470 for setting 0 to “0” is executed.

This processing can be performed by providing the flag 15 which is set to "1" by the return CISC instruction 450 in the CISC processor 100. Despite the ENABLE flag 10 being "1", decoding is exceptionally enabled, and the microprogram can set the RISC-ENABLE flag 10 to "0".

As a result of this processing, the processing of the CISC processor 100 is enabled again, the processing of the RISC processor 200 is disabled, and control is switched from the RISC processor 200 to the CISC processor 100. Thereafter, the above-described processing of the instruction sequence 303 is performed.
Is validated and executed by the CISC processor 100.

As shown in the above-mentioned processes 410 and 460, the execution of both instructions is performed before and after the serialization operation and the checkpoint synchronization function, so that all preceding accesses to the storage device are completed. Until the operation is performed, the CPU operation is kept waiting.

The operation of the above-described embodiment of the present invention has been described on the assumption that a part of the CISC processor application program owned by the user is efficient when the RISC processor executes the program. If all of the programs are efficient to let the RISC processor do, compile all of them and
It is also possible to have the SC processor do this.

In one embodiment of the present invention described above, Re
The turn CISC instruction 450 may be an instruction exception within the RISC processor 200, thereby causing the RIS
An increase in the decoding logic on the C processor 200 side can be suppressed. In addition, the present invention can increase the operating frequency of the RISC processor 200 to twice that of the CISC processor 100 by combining generally known clock techniques, thereby achieving a multiprocessor with higher performance. The operation technique using such a double frequency is as follows.
For example, supercomputer S8 of HITACHI
20, the vector register of S3800.

As described above, with a single processor,
With a CISC processor alone, the number of executed instructions per main cycle cannot be reduced to one or less. Also, RI
With only an SC processor, it is difficult to increase the commercial processing performance required of a general-purpose computer, even if the performance of a program such as scientific calculation is improved.

However, in the processor according to the present invention, it is possible to reduce the average number of executed instructions per machine cycle to 1 or less by utilizing the RISC processor.
In addition, since it is not inferior to general-purpose computers, it is possible to smoothly transition to a new processor architecture without maximizing the processing performance as a single processor, and the conventional user can easily obtain the high performance of the RISC processor. Can be done. Further, by using a microprogram, it is possible to reduce the increase in hardware by comparing it with the hardware decode logic.

As described above, according to one embodiment of the present invention,
In the case of only a CISC processor, the number of executed instructions per machine cycle cannot be reduced to 1 or less.
To solve the problem of the prior art that it is difficult to increase the commercial processing performance required for a general-purpose computer even if the performance of a program such as scientific calculation is improved when only an SC processor is used. Can be.

[0051]

As described above, according to the present invention, C
The ISC processor application program resources can be utilized, and more efficient data processing can be performed using a RISC processor for RR-type operations and floating-point operations.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an instruction execution control unit.

FIG. 3 is a diagram showing an example of an instruction sequence for explaining an example of the operation of the present invention.

FIG. 4 is a flowchart illustrating processing of a start instruction and a return instruction.

[Explanation of symbols]

10, 15 Flag 20, 120 Instruction execution control unit (I-Contrl) 25, 125 Branch control unit (Branch-Control) 26, 126 Adder (Add) 30, 130 Control register group (C-Registr) 40, 140 General purpose Register group (G-Registr) 50, 150 Floating point register group (F-Register) 60, 160 Cache control (Cache-Control)
l), 70 Cache memory (Cache) 80 Control memory (CS) 90 Address counter (IA) 100 CISC processor 200 RISC processor

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-227177 (JP, A) JP-A-4-195226 (JP, A) JP-A-54-52942 (JP, A) INSPEC Abstract Number: C9350-5220P-024 'Hybrid pyramid mul tiprocessor system for image processing' Chen, I.C. Jagad eesh, J .; M. Proceeding of the ISMM International Conference. See Parallel and Distributed Computing, and Systems p. 34-7 1990 (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 15/16 410 G06F 9/28 320 G06F 9/38 370 EPAT (QUESTEL) INSPEC (DIALOG) JICST file (JOIS) WPI ( DIALOG)

Claims (5)

(57) [Claims] 1. A multiprocessor having at least two CPU cores, wherein at least one of the CPU cores is a processor of a microprogram control method, and another CPU core is a processor having a different instruction control method from the CPU core. And the microprogram
Control processor, CPU core and instruction control system
Processor fetches the same instruction sequence
Cormorants multi-processor, characterized in that. 2. A means for causing the microprogram control type processor to start a processor having a different instruction control method from the CPU core, a flag means for enabling a processing operation of the started processor, 2. The multiprocessor according to claim 1, further comprising: means for instructing termination of the operation of the processor that has been operated by activation. Relative wherein said micro-program-controlled processor, a processor, wherein the CPU core and instruction control method are different, the multi-processor of claim 1 or 2, wherein the operating at twice the machine cycle. Wherein said processor of the microprogram control is CISC processor, multiprocessor of claim 1, 2 or 3, wherein said CPU core and the instruction control scheme is different processors RISC processor. 5. A processor of the microprogram control, circuit including said processor CPU core and instruction control method are different, one of claims 1 to 4, characterized in that it is formed in the chip LSI 2. The multiprocessor according to 1.