JP2844725B2 - Mask ROM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a mask RO configured by cascading memory cells and writing data by ion implantation into a channel portion.
About M.

[Prior Art] Conventionally, this type of mask ROM is a read-only memory in which data is written during a manufacturing process, and the data writing process differs depending on the ROM structure. This data writing is generally performed in an ion implantation step or a contact formation step.

In recent years, as the capacity and density of a mask ROM have been increased, the connection of memory cells has generally become a vertically stacked structure (NAND), and data writing has been realized by ion implantation into a channel portion of the memory cell.

 FIG. 3 is a circuit diagram showing a conventional mask ROM.

Third, as shown in FIG, between the digit line V _digit and the ground potential memory cell M ₀ to M ₃ are connected sequentially in series to the element an insulated gate field effect transistor, vertical stack memory 4 stage Forming a cell. The memory cells M ₀ through
In the manufacturing process, M ₃ is a specific memory cell, for example, M ₁
For example, phosphorus is ion-implanted into the channel portion, so that each threshold voltage corresponds to data of 1, −5, 1, 1V. These gates of the memory cells M ₀ to M ₃ are, are respectively connected to the X-decoder input terminal X ₀ to X _3.

Next, the read operation of the mask ROM will be described.

Selection of the memory cells M ₀ to M ₃ are, X-decoder input terminal X ₀
To the decode signal input via the X _3, and "H" to the gate of the non-selected cell is performed as "L" of the gate of the selected cell.

For example, the case of reading the memory cell M _0, the X-decoder input terminal X ₀ input to 0V, thereby inputting respectively 5V to the X-decoder input terminals X ₁ to X _3. Thus, although the memory cell M ₁ to M ₃ are being forced to the ON state, since the memory cells M ₀ threshold voltage is 1V becomes OFF state, the digit line V _digit
Can maintains the high level, reading the data "1" written in the memory cells M _0.

Also, the case of reading the memory cells M _1, type a 0V to the X-decoder input terminals X _1, X-decoder input terminal X _0, X ₂ and X ₃
Input 5V to each. Thereby, the memory cells M ₀ , M ₂ , M ₃
With but forced into the ON state, since the memory cell M ₁ threshold voltage is -5V also turned ON, the digit line V
_digit becomes the low level, the data "0" written in the memory cells M ₁ can be read.

In this way, the mask ROM in which data has been written to each memory cell in the manufacturing process can be read.

[Problems to be Solved by the Invention] However, since the above-described conventional mask ROM writes data in a manufacturing process, it does not have a function of writing data after manufacturing. For this reason, mask RO after production
If there is a defective cell in M, it is not possible to replace the defective cell with a non-defective redundant element such as a RAM and a PROM to rescue the product. That is, when a defective cell exists, not only the replacement of the defective cell but also the writing of data must be performed, so it is extremely difficult to apply a redundant element to a conventional mask ROM.

Therefore, as the density of the mask ROM is increased and the capacity thereof is increased, the conventional mask ROM has a problem that the number of products having a partially defective portion increases, and the production yield decreases.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a mask ROM that can easily replace a defective cell portion with a redundant cell and has a high manufacturing yield.

[Means for Solving the Problems] A mask ROM according to the present invention is connected in series between a digit line and a common terminal, and sets respective threshold voltages corresponding to data by selective ion implantation. In the mask ROM having a plurality of memory cells, the memory cells are connected in series between the digit line and the common terminal in one-to-one correspondence with the memory cells, and each of the threshold voltages has a common value. , And a plurality of redundant memory cells connected in parallel to each other, and a fuse which is connected in parallel and which can be cut after manufacturing.

[Operation] In the present invention, the threshold voltages of all the redundant memory cells are set to, for example, the same threshold voltage as the higher one of the two threshold voltages of the memory cells. When a failure occurs in a memory cell, the vertical memory cell including the memory cell is replaced with a redundant vertical memory cell corresponding to the vertical memory cell. Then, only the fuses connected in parallel to the redundant memory cells corresponding to the memory cells having the high threshold voltage are cut. As a result, both ends of the redundant memory cell where the fuse is blown are conductive only when it is activated,
Since both ends of the redundant memory cell where the fuse is not blown are always short-circuited by the fuse regardless of the state of the redundant memory cell, the redundant column memory cell functions in the same manner as the column memory cell. I do.

Therefore, according to the present invention, a defective memory cell in a manufactured mask ROM can be easily replaced with a redundant circuit, so that a partially defective mask ROM can be relieved and a mask ROM can be manufactured. The yield can be improved.

Example Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a mask ROM according to a first embodiment of the present invention.

As shown in Figure 1, it is connected to a sequential series of memory cell memory cell M ₀ to M _3, to form a vertical stack memory cells of four-stage (broken line) between the digit line V _digit and the ground potential ing. The memory cells M ₀ to M ₃ are, in the manufacturing process,
Particular memory cell, for example, by ion implantation in the channel region of the M _1, each threshold voltage 1 it has become those corresponding to the -5,1,1V and data. These memory cells M _{0 to}
Each gate of M ₃ are respectively connected to the X-decoder input terminal X ₀ to X _3. This vertical memory cell and the digit line V
Between the _digit, the transistor M _y0 is connected, the gate thereof is connected to the Y decoder input Y _0.

On the other hand, between the digit line V _digit and the ground potential, the redundant memory cell in correspondence to each memory cell M ₀ to M ₃
M _{d0 to} M _d3 are sequentially connected in series to form a four-stage redundant memory cell stack. The redundant memory cells M _{d0 to} M _d3
Are set to, for example, 1V. X decoder input terminal X ₀ through X ₃ are respectively connected to the gates of the redundancy memory cell M _d0 to M _d3. Between the drain and source of each redundant memory cell M _d0 to M _d3, the fuse F ₀ to F
₃ are connected in parallel. These fuses F _{0 to} F
₃ is made of, for example, a polycrystalline silicon fuse, and can be cut after manufacturing. Between the redundant vertical stack memory cells and a digit line V _digit, the transistor M _yd is connected, the gate thereof is connected to the Y decoder input Y _d.

 Next, the operation of the mask ROM will be described.

For example, the case of reading the memory cell M _0, with Type 5V to Y decoder input Y ₀ the transistor M _y0 to ON state, enter the 0V to the X-decoder input terminal X _0, X-decoder input terminal to enter the respective 5V to X ₁ to X _3. Thus, although the memory cell M ₁ to M ₃ are is forced to the ON state, since the memory cells M ₀ threshold voltage is 1V becomes OFF state, the digit line V _digit maintains high level , can be read out data "1" written in the memory cells M _0.

Also, the case of reading the memory cells M _1, along with enter 5V to Y decoder input Y ₀ the transistor M _y0 to ON state, enter the 0V to the X-decoder input terminals X _1, X-decoder input terminal 5V is input to each of X ₀ , X ₂ and X ₃ . As a result, the memory cells M ₀ , M ₂ , and M ₃ are forcibly turned on, and the memory cell M ₁ having a threshold voltage of −5 V is also turned on, so that the digit line V _digit becomes low level. a state, the written data "0" to the memory cell M ₁ can be read.

Then, due to contamination or the like of dust in the manufacturing process, for example, memory cells M ₁ to defect occurs in the memory cell M ₁ is always OPEN
Ready, if the entire vertical stack memory cells including the memory cell M ₁ becomes defective, the fuse F ₀ to F ₃ appropriately cut by laser. In this case, since the threshold voltages of the memory cells M ₀ , M ₂ , and M ₃ are each 1 V, the fuses F ₀ , F ₂ , and F ₃ are cut. Further, the threshold voltage of the memory cell M ₁ is at -5V, at the fuse F ₁ is not cut, the redundancy memory cells M _d1
Is short-circuited.

Next, normally, a 5 V decode signal input to the Y decoder input terminal Y ₀ is input to a predetermined circuit unit (not shown), and ₀ V is input from the circuit unit to the Y decoder input terminal Y ₀ , so as to enter a 5V to the decoder input terminal Y _d. As a result, the transistor M _y0 and OFF, ON the transistor M _yd
To replace a defective column memory cell and a redundant column memory cell.

After replacing the defective vertical stack memory cells and redundant vertical stack memory cells, when reading is for example redundant memory cell M _d1,
Type a 0V to the X-decoder input terminals X _1, inputs respectively 5V to the X-decoder input terminal X _0, X ₂ and X _3. As a result, the redundant memory cells M _d0 , M _d2 , and M _d3 having a threshold value of 1 V are forcibly turned on, and the fuse F is connected to both ends of the redundant memory cell M _d1.
Since it is short-circuited by ₁ , the digit line _Vdigit is in the low level state, and the data "0" written in the redundant memory cell _Md1 can be read.

Moreover, the redundant case of reading the memory cell M _d0 inputs of 0V to the X-decoder input terminal X _0, X-decoder input terminals X ₁ to
To enter the respective 5V to X _3. Thereby, the redundant memory cell M
with _d1 to M _d3 is forced ON state, since the redundant memory cell M _d0 threshold voltage is 1V becomes OFF state,
Digit line _Vdigit maintains the high level state, and can read data "1" written in redundant memory cell _Md0 .

Thus, in this embodiment, the fuse
By selectively cutting F _{0 to} F ₃ , the defective column memory cell and the redundant column memory cell are replaced, and the mask ROM is replaced.
Can be remedied.

FIG. 2 is a circuit diagram showing a mask ROM according to a second embodiment of the present invention. This embodiment is an embodiment in which a resistor is connected in series with a fuse between the drain and the source of each redundant memory cell of the first embodiment. Therefore, in FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 2, between the drain and source of the redundant memory cell M _d0 to M _d3, the fuse F ₀ to F ₃ in series with resistor R ₀ to R ₃ are respectively connected.

Therefore, in this embodiment, the redundant memory cell after replacing the defective vertical memory cell and the redundant vertical memory cell is
Since the current between the drain and the source of M _{d0 to} M _d3 can be easily controlled, there is an advantage that a current value substantially equivalent to the case where the memory cells M _{0 to} M ₃ are read can be realized.

[Effects of the Invention] As described above, according to the present invention, when a defective column memory cell occurs after manufacturing, a fuse connected between a drain and a source of each redundant memory cell is selectively selected. By cutting, the defective vertical memory cell and the redundant vertical memory cell can be easily replaced. Therefore, a partially defective mask ROM can be relieved,
Thereby, the manufacturing yield of the mask ROM can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a mask ROM according to a first embodiment of the present invention, and FIG. 2 is a mask RO according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram showing a conventional mask ROM. M ₀ ~M _3; memory cells, M _d0 ~M _d3; redundant memory cells, M _y0, M
_yd; transistors, F ₀ ~F _3; fuse, R ₀ ~R _3; resistance, X ₀
~ X ₃ : X decoder input terminal, Y ₀ , Y _d ; Y decoder input terminal

Claims (1)

(57) [Claims] 1. A mask ROM having a plurality of memory cells connected in series between a digit line and a common terminal and having respective threshold voltages set corresponding to data by selective ion implantation. A plurality of redundant memory cells connected in series between the digit line and the common terminal in one-to-one correspondence with the respective memory cells and having respective threshold voltages set to a common value; And a fuse which is connected in parallel to each of the redundant memory cells and which can be cut after production.