JP2842501B2 - Interrupt processing method, multiprocessor system, and interrupt processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, interrupt processing of an information processing apparatus having a multiprocessor configuration, and more particularly to floating interrupt processing.

[0002]

2. Description of the Related Art FIGS. 7 and 8 show a conventional multiprocessor system configuration and a floating interrupt processing system in the system. FIG. 7 shows, for example, IEEE standard P89
6 is an example of a multiprocessor system configuration realized using Futurebust specified in 6.1.

In FIG. 1, reference numeral 1 denotes a processor for executing data processing and interrupt processing. Reference numeral 2 denotes a main storage device for storing instructions and data. This main storage device 2 is shared by all processors 1 in the configuration. Reference numeral 3 denotes an external interrupt control unit (hereinafter referred to as ITC). The ITC 3 issues a floating interrupt request to all processors 1. The ITC 3 issues detailed information accompanying the floating interrupt request in response to a floating interrupt acceptance notification from a certain processor. The ITC 3 also performs a process for canceling the received floating interrupt request.

[0004] Reference numeral 4 denotes a plurality of control common signal lines (hereinafter, referred to as control buses) for transferring control information. The control bus 4 controls an information transfer operation between each processor 1 and the main storage device 2. The control bus 4 transfers a signal for controlling the operation of issuing a floating interrupt request between the processor 1 and the ITC 3. Further, the control bus 4 transfers a signal for controlling the interrupt acceptance notification operation.

[0005] Reference numeral 5 denotes a plurality of data common signal lines (hereinafter referred to as data buses) for transferring information. The data bus 5 transfers information between each processor 1 and the main storage device 2. The data bus 5 transfers floating interrupt accompanying information between the processor 1 and the ITC 3.

FIG. 8 shows a multiprocessor system configuration having individual floating interrupt request signal lines between each processor and an external interrupt control unit. In the figure, 1 to 5 are all the same as those shown in FIG.

Next, the operation will be described. A method called a floating interrupt method is generally known as a method for equalizing load distribution between processors and improving system throughput. The floating interrupt method refers to, for example, in a symmetric multiprocessor system, requesting one interrupt such as an input / output interrupt to a plurality of processors,
In this method, only the processor which has accepted the interrupt first performs the interrupt accepting process in the system.

In FIG. 7, it is assumed that the ITC 3 first detects a floating interrupt factor. The ITC 3 that has detected the floating interrupt factor performs bus arbitration with the processor 1 and acquires the right to use the control bus 4 and the data bus 5. Since the operation of the bus arbitration is not the essence of the floating interrupt processing described here, the description is omitted here. The ITC 3 that has acquired the right to use the bus as a result of the bus arbitration broadcasts a floating interrupt request to all the processors 1 in the system configuration using the control bus 4 and the data bus 5. Each processor 1 recognizes that the floating interrupt has been broadcast from the ITC 3 based on the signal value of the control bus 4.

Subsequently, inside each processor 1, acceptance permission conditions such as an interrupt mask are internally determined independently of each other. If the floating interrupt request broadcasted by a certain processor 1 is not accepted, the processor 1 keeps activating the floating interrupt acceptance notifying process until the processor 1 transits to the interrupt accepting permitted state. If a certain processor 1 is in a reception permitting state for receiving a floating interrupt request broadcast, the processor 1 activates a floating interrupt reception process.

[0010] Here, there must be only one processor in the system that accepts one floating interrupt request and performs interrupt processing. The processor 1 that has started the floating interrupt accepting process performs the following operation to perform the floating interrupt accepting process only by itself. The processor 1 that has started the floating interrupt accepting process first broadcasts a declaration of the start of the floating interrupt accepting process to all the processors 1 other than itself using the control bus 4. The processor 1 releases the floating interrupt acceptance processing of the other processor 1 by the broadcast. Here, since a floating interrupt request is simultaneously broadcast from the ITC 3 to all the processors 1, there is a case where a plurality of processors 1 start the floating interrupt accepting process at the same time. In this case, there is a possibility that a plurality of processors 1 compete for issuing a declaration of the start of the floating interrupt acceptance process using the control bus 4 at the same time. However, the solution of this race condition is achieved by using bus arbitration. In other words, one processor 1 that has first acquired the bus use right by the bus arbitration can use the control bus 4. Only the processor 1 that has acquired the usage right broadcasts a declaration of the start of the floating interrupt acceptance process. All the other processors 1 that have received this cancel all the operations that are pending or that are in the process of starting the floating interrupt accepting process.

The one processor 1 which has completed the operation of declaring the start of the floating interrupt acceptance process on the control bus 4 transmits a floating interrupt acceptance notice to the ITC 3 via the control bus 4. After receiving the accompanying information of the floating interrupt from the ITC 3 via the data bus 5, the processor 1 completes the floating interrupt processing.

On the other hand, when the response to the floating interrupt acceptance notification via the control bus 4 and the data bus 5 is completed, the ITC 3 clears the relevant floating interrupt factor and proceeds to the next floating interrupt request operation.

Next, a conventional floating interrupt request issuance control operation will be described with reference to FIG. In the figure, each processor 1 outputs a wait state from each processor to the ITC 3 using wait state signal lines WAIT_0 and WAIT_1. Then, the ITC 3 refers to the wait state of each processor 1 and determines which processor 1
Issue a floating interrupt request. And I
The TC3 sends a floating interrupt request detected by itself to the floating interrupt request signal line FINT_0 to each processor 1.
Or, it is issued using FINT_1.

The method of determining the output of the floating interrupt request is as follows, for example. (1) When one or more processors 1 are in the wait state, the floating interrupt request is issued only to all the processors 1 in the wait state. (2) If all the processors 1 are not in the wait state, a floating interrupt request is issued to all the processors 1. The declaration operation of the start of the floating interrupt accepting process and the interrupt accepting process in each processor 1 in response to the floating interrupt request are executed by using the control bus 4 and the data bus 5 as in FIG.

[0015]

Since the conventional interrupt processing system is configured as described above, in the system configuration shown in FIG. Information is frequently transferred using the bus 5. In addition, in the system configuration shown in FIG. 7, the broadcast of the floating interrupt request from the ITC 3 to all the processors 1 uses the control bus 4 and the data bus 5. In addition, the control bus 4 and the data bus 5 are used to broadcast a declaration of the start of acceptance processing of a floating interrupt request issued from one processor 1 to all other processors 1. In addition, one processor 1 that executes a floating interrupt acceptance process
Also uses the control bus 4 and the data bus 5 for a floating interrupt acceptance notification issued to the ITC 3 from. For this reason, there has been a problem that the bus utilization rate is increased, and the transfer capability of the control bus 4 and the data bus 5 becomes a bottleneck in the system performance and the floating interrupt processing performance.

In addition, in the system configuration shown in FIG.
The control bus 4 and the data bus 5 commonly handle data stored in the main storage device 2 and floating interrupt request information. Therefore, a floating interrupt request is issued to all processors 1
, All processors must receive the broadcast interrupt information regardless of the internal state of each processor 1.
If the processor 1 cannot receive the broadcast interrupt information, it is necessary to execute the broadcast operation again. Re-executing the broadcast operation on the bus will increasingly increase bus utilization. In order for the processor 1 to receive the broadcast information at any time, there is a problem that additional hardware resources are required.

Further, in the interrupt processing system configured as shown in FIG. 8, the wait state of each processor 1 can be determined. Therefore, it is possible to reduce the cost of using the bus required for issuing the floating interrupt request broadcast. In addition, it is possible to reduce the cost of using the bus required to determine the processor that performs the floating interrupt acceptance processing. In the interrupt processing method configured as shown in FIG. 8, it is possible to reduce the total cost of floating interrupt processing in the entire system. However, on the other hand, a wait state signal line uniquely connecting each processor 1 and the ITC 3 and a unique floating interrupt request signal line from the ITC 3 to each processor 1 are required. When the processor 1 and the ITC 3 are each configured by one LSI, or when the number of processors 1 increases, there is a problem that the number of signal pins of the LSI increases.

The present invention has been made to solve the above problems, and provides an interrupt processing method and the like that minimizes the influence on the system performance by minimizing the use of the memory bus by the floating interrupt processing. The purpose is to do. In addition, the number of signal lines between each processor 1 and the ITC 3 is minimized, and the internal state of each processor 1 is individually used to control the start of the process of accepting a floating interrupt request. It is an object of the present invention to provide an interrupt processing method or the like that further reduces the total cost of the processing.

[0019]

An interrupt processing method according to the present invention includes, for example, a floating interrupt common signal line (an example of an interrupt line) for transmitting a floating interrupt request from the ITC to all processors, and a communication between the ITC and all processors. And a plurality of control common signal lines (an example of control lines) for controlling a signal transfer operation between the processor and the ITC and for notifying each processor of a floating interrupt to the ITC; A common signal line (an example of a data line) of data for transferring floating interrupt accompanying information from the ITC in response to a floating interrupt acceptance notification issued from one processor via a control common signal line with a control common signal line. And has the following elements. (A) an interrupt line for transmitting an interrupt request, (b) a control line for transmitting control information, (c) a data line for transmitting data information, and (d) connected to the interrupt line, the control line, and the data line. The interrupt request is sent to the control line, an interrupt is received based on data information from the data line, an interrupt process is performed, the control line is monitored, and another processor unit receives the interrupt information. A plurality of processor means for canceling the processing related to the interrupt request of the own processor in the case; (e) connected to the interrupt line, the control line and the data line, and transmitting an interrupt request to the plurality of processor means via the interrupt line And the processor that first issued the interrupt acceptance notification among the processor means that accepted the interrupt request. The interrupt controller for delivering using the data line data information necessary to interrupt processing on the processor means.

Furthermore, in each of the processors in the interrupt processing method according to the second invention, after recognizing the interrupt request, the processor is in a wait state in which the processor is ready to accept an interrupt and is not executing an instruction but is waiting for an interrupt. Immediately starts the interrupt acceptance notification process,
Also provided is an interrupt acceptance control means for activating an interrupt acceptance notifying process when the processor is in the interrupt acceptable state after delaying by the number of cycles independently determined for each processor when not in the wait state.

A multiprocessor system according to the present invention
Has multiple processors and has the following elements
It is characterized by. (A) for a plurality of processors sends a common interrupt request, receive interrupt acceptance notification from one processor, the additional information related to the common split <br/> interrupt request to the one processor reportedly external interrupt control device to end the common interrupt request received confirmation accepted the interrupt request, (b) the external interrupt control unit and by connecting a plurality of processors, the external interrupt control device of a plurality of processors a common interrupt line for transmitting the common interrupt request to the external interrupt control device; and (c) connecting the external interrupt control device to a plurality of processors. and control signals between a plurality of processors, the interrupt acceptance convey notification control line from one of the plurality of processors to the external interrupt controller, (d) Connect Kigaibu interrupt control device and a plurality of processors, in response to the interrupt acceptance notification of the control line, the data line for transmitting additional information relating to the common interrupt request, provided on each of the (e) said plurality of processors, the above
Monitor the common interrupt line and use the common interrupt line
The above common interrupt request is accepted and assigned to the control line.
Sends a data transfer notification and adds data from the data line.
Perform interrupt processing based on the information
Monitors the control line and another processor accepts an interrupt request
Processing for the interrupt request of the own processor
Processor means to cancel.

The interrupt processing method according to the present invention has one
Connected by common interrupt, control and data lines
Equipped with multiple processors and an interrupt control unit.
It is characterized by comprising steps. (A) the interrupt request sending step in which the interrupt control unit for the delivery of one common interrupt request to a plurality of processors via the shared interrupt line, the common interrupt via (b) the common interrupt line A recognition step of recognizing the request by a plurality of processors ; (c) a receiving step of receiving the common interrupt request by at least one processor; and (d) a receiving step of receiving the common interrupt request. By one , a control line is provided to the interrupt control unit.
(E) sending an interrupt acceptance notification from the interrupt control unit
A transmitting step of transmitting information relating to the interrupt request to the issuing processor via the data line; (f) first receiving an interrupt among the plurality of processors
When another processor detects an interrupt acceptance notification on the control line from the processor that sent the notification ,
Clearing step in which the processor of (1) clears acceptance of the common interrupt request.

In the receiving step, the processor waits.
The processor is waiting for an interrupt and the processor
When the predetermined delay time has been used up
Notification of acceptance of the interrupt request
It is characterized by doing.

[0024]

The interrupt line according to the present invention makes it possible to issue an interrupt request to all processors independently of the memory bus, suppress the influence on the system performance, and minimize the number of signal lines between each processor and the interrupt control unit. Limit the number of signal pins.

Further, the control line is constantly monitored by all the processors, and when one processor issues an interrupt acceptance notification to the interrupt control unit, all other processors look at the floating interrupt acceptance notice, and By automatically canceling the internal interrupt request and the pre-acknowledgement process, the processor executing the interrupt acknowledgment process does not need to cancel the interrupt acknowledgment process for all other processors.

Further, by transmitting the interrupt request and recognizing the interrupt request via the interrupt line, it is possible to avoid a decrease in the efficiency of the system due to the excess use of the control line and the data line.

Further, as an interrupt acceptance control provided inside each processor, when an interrupt request is recognized, an interrupt waiting state or a processor having the shortest interrupt delay time set is preferentially accepted based on the state of each processor. By taking charge of the processing, the processing efficiency of the entire multiprocessor system is improved.

[0028]

【Example】

Embodiment 1 FIG. FIG. 1 is a configuration diagram of a multiprocessor system for explaining an embodiment of the present invention. In the figure, 1, 2,
3, 4 and 5 show the same parts as in the conventional example of FIGS. 6 connects between the ITC 3 and all processors 1 and
A floating interrupt line (hereinafter referred to as FINT) for transmitting a floating interrupt request from TC3 to all processors 1.

FIG. 2 is an internal block diagram of one processor for explaining one embodiment of the present invention. In the figure,
7 is an interrupt processing unit for controlling floating interrupt processing transmitted from the floating interrupt common signal line, 8 is a data processing unit for executing instructions and interrupt processing in the processor 1,
Reference numeral 9 denotes a bus request unit that interfaces with the control bus 4 and the data bus 5 based on a request from the data processing unit.

FIG. 3 is a circuit diagram showing the internal configuration of the interrupt processing unit 7. In the figure, 10, 13, and 2
3 is a latch. 11, 12, 14, 18, 26, 2
7, and 29 are AND gates. 15, 19 and 28 are OR gates. 16 is a flip-flop. The flip-flop 16 holds that the floating interrupt request is recognized in the processor 1. Reference numeral 17 denotes a floating interrupt acceptance mask latch. The floating interrupt reception mask latch 17 holds floating interrupt reception mask information in the processor 1. 20 is a priority circuit. The priority circuit 20 takes priority between interrupt types in the processor 1. After taking priority, the priority circuit 20 issues a request for interrupt acceptance notification processing to the data processing unit 8. 21 is a floating interrupt delay cycle register for holding the number of cycles. The number of cycles held in the floating interrupt delay cycle register 21 is used to delay the activation of the floating interrupt acceptance notification process after recognizing the floating interrupt request. 22 is a selector.
24 is a decrementer. The decrementer 24 subtracts the value of the flip-flop 16 from the value of the latch 23 and outputs a result of the subtraction. The decrementer 24 also outputs a flag indicating that the subtraction result is zero. Reference numeral 25 denotes a flop flop indicating that the time has elapsed by the number of cycles set in the latch 21 since the floating interrupt request was set in the flip-flop 16.

The operation will be described below based on one embodiment of the present invention. The following description is roughly divided into three parts.
The first part is called a floating interrupt request recognition process, and mainly corresponds to the operation of the interrupt processing unit 7 of the processor 1. The operation relates to an operation of recognizing a floating interrupt request before the floating interrupt request reaches the data processing unit 8. The second part is called an acceptance notification process, and mainly corresponds to the operation of the data processing unit 8 in the processor. The operation relates to the operation of receiving a floating interrupt. The last part is called an interrupt request acceptance notification process and mainly relates to the operation between one processor and another processor and the ITC 3. This operation relates to a floating interrupt request acceptance notification operation including the inside and outside of the processor 1, that is, the ITC 3, the control bus 4 and the data bus 5.

First, a process of recognizing a floating interrupt request in each processor 1 will be described. In FIG. 3, it is assumed that the floating interrupt delay cycle register 21 in the interrupt processing unit 7 of each processor 1 is set to an independent non-zero value for each processor 1 in advance. It is also assumed that the value has been set in the latch 23 through the selector 22.

In FIG. 1, it is assumed that the ITC 3 has detected the presence of a floating interrupt. ITC3 outputs a floating interrupt request to FINT6. Then, all the processors 1 that input the FINT 6 take the rising differential of the FINT 6 by the latch 10 and the AND gate 11 in the interrupt processing unit 7. Then, based on the result of the differentiation, a floating interrupt request passes through an OR gate 15 and a flip-flop 16
Is set to The floating interrupt request once set in the flip-flop 16 is output from the flip-flop 16. And floating interrupt acceptance mask latch 1
When the data processing unit 8 is set to the reception permission state and the signal line WAIT indicating that the processor 1 is in the wait state is output from the data processing unit 8, the AND gate 18 is opened. When the AND gate 18 is opened, the floating interrupt request set in the flip-flop 16 is input to the priority circuit 20 through the OR gate 19.

The floating interrupt request set in the flip-flop 16 is input to the decrementer 24 as a decrement value. When the floating interrupt request is set in the flip-flop 16, the result of subtracting 1 from the value set in the latch 23 and the zero flag of the subtraction result are output from the decrementer 24. The subtraction result output from the decrementer 24 is set in the latch 23 through the selector 22 in the next cycle, and then input to the decrementer 24. The value set in the latch 23 in advance in this manner continues to be subtracted one by one while the floating interrupt request is output from the flip-flop 16. When the subtraction result becomes zero, a zero flag is output from the decrementer 24 and the flip-flop 2
Set 5 If the latch 17 is in the accepting state of the floating interrupt mask in the cycle in which the flip-flop 25 is set or thereafter until the reset condition occurs, the AND gate 26 is opened and the floating interrupt request is sent to the OR gate 19. Through the priority circuit 20
Is input to

The priority circuit 20 takes priority between another interrupt request and the floating interrupt request transmitted from the OR gate 19 in accordance with a predetermined priority order definition. If there is no interrupt factor having a higher priority than the floating interrupt, the floating interrupt request is sent to the data processing unit 8 by the floating interrupt activation request signal FIN.
T_RQ is issued.

Conditions for setting a floating interrupt request to the flip-flop 16 include the following conditions in addition to the conditions detected by the differentiating circuit described above. The process of recognizing, accepting, and notifying a floating interrupt request includes a bus operation using a control bus 4 and a data bus 5 between one processor and the ITC 3. The ITC 3 may detect another floating interrupt for the next operation before the bus operation for the notification process of the acceptance of the floating interrupt ends. In this case, the ITC 3 does not negate the FINT signal on the FINT line 6 even after the end of the bus operation, and outputs "O".
N ".

However, in this case, each processor cannot recognize another floating interrupt request. This is because the differentiating circuit cannot detect the rising differential from the FINT signal which remains "ON". Therefore, if the FINT signal continues to be asserted in the ITC 3 at the end of the bus operation, it is necessary to enable all processors to recognize that a new floating interrupt request has occurred.

In order to solve such a problem, the BEND signal and the FACK signal are used to notify the end of the bus operation for the floating interrupt acceptance notification process. One of the processors recognizes the notification of the acceptance of the floating interrupt to the ITC 3 and,
Outputs an ACK signal. Thereafter, the ITC 3 outputs a BEND signal via the control bus 4 at the end of the bus operation. The BEND signal indicates the end of information transmission on the data bus 5 for bus operation. When recognizing the BEND signal on the control bus 4, the control device that outputs the FACK signal negates the FACK signal.

For the above reason, the end of the bus operation for the notification process of the acceptance of the floating interrupt is determined by the FAC
It is detected by checking both the K signal and the BEND signal. The AND gate 12 detects the FACK signal and the BEND signal, and sets the flip-flop 13. Flip-flop 13 indicates the end of the bus operation. If the FINT signal is "ON" at that time, A
The ND gate 14 opens, and the flip-flop 16
3. Set another floating interrupt request output from 3.

It should be noted that in one processor 1,
The condition for setting the recognized floating interrupt request in the flip-flop 16 and then issuing a floating interrupt activation request by the signal FINT_RQ to the data processing unit 8 is such that the floating interrupt mask set in the floating interrupt reception mask latch 17 is in a reception permission state. It is not determined solely on the basis of something. The floating interrupt activation request is issued immediately when the processor 1 is in the wait state for the interrupt or enters the wait state. When the processor 1 is not in the wait state, the floating interrupt activation request is issued after the time has elapsed by the number of cycles unique to the processor 1 set in the floating interrupt delay cycle register 21. If the floating interrupt accepting mask latch 17 is set to the non-accepting state, the AND gates 18 and 26 are closed, and the floating interrupt request is not transmitted to the priority circuit 20. Therefore, a floating interrupt activation request by the signal FINT_RQ is not output to the data processing unit 8. The floating interrupt request recognition process 100 will be summarized based on FIGS. In order for the floating interrupt activation request signal FINT_RQ to be issued to the data processing unit 8, a condition for issuing the FINT_RQ to the logic circuit shown in FIG. 3 must be set. As shown, the output of flip-flop 16 causes AND gates 18 and 26 to open. As shown in FIG. 3, the flip-flop 1 is connected to the AND gate 18.
6, a latch 17, and a WAIT signal of the data processing unit 8. The AND gate 26 has a latch 1
7. There are two inputs of flip-flop 26. AND
The gate opens only when all elements affecting the AND gate are satisfied.

FIG. 4 shows this condition. First, there is a WAIT signal sent from the data processing unit 8 as an element for opening the AND gate 18. The WAIT signal indicates that the processor is in a waiting state and can accept an interrupt. Regarding the WAIT state of the processor, there are the following three conditions. (1) When the processor is in the WAIT state (that is, the signal WA indicating that interruption is possible)
Open (when IT is output). (2) The AND gate 18 terminates the execution of the processor
When the AIT signal is received, it is opened immediately. (3) If the processor is not in the WAIT state, the AND gate 18 does not open, but the processor is BUSY and W
If not in the AIT state, the AND gate 26 is opened after a lapse of time equal to the number of unique cycles set in the floating interrupt delay cycle register 21.

The AND gate 26 is opened when the output from the decrementer 24 becomes zero and the floating interrupt acceptance mask latch 17 becomes ready to accept. Finally,
In order for the AND gates 18 and 26 to open and allow the floating interrupt to be accepted, the floating interrupt acceptance mask latch 17 must be in the acceptance permitted state. If the floating interrupt reception mask latch 17 is set to the reception non-permission state, the AND gate 1
8 and 26 are closed, and the floating interrupt request is not transmitted to the priority circuit 20. When the above conditions shown in FIG. 4 are satisfied, the signal FINT_RQ is sent to the data processing unit 8.
A floating interrupt activation request is output.

Next, the signal FINT_
The receiving process 200 when the floating interrupt activation request issued by the RQ is received by the data processing unit 8 will be described with reference to FIG. When the floating interrupt start request signal FINT_RQ is issued, the data processing unit 8 receives an interrupt start request as a internal state in a cycle in which interrupt processing can be started. The data processing unit 8 sets an IACK signal indicating that the floating interrupt request has been accepted. Even if the interrupt processing unit 7 issues an interrupt activation request by the FINT_RQ signal, depending on the state of the data processing unit 8,
The ACK signal may not be returned immediately. In this case, the interrupt processing unit 7 keeps outputting the interrupt activation request by the FINT_RQ signal by holding the floating interrupt request set in the flip prop 16 or 25. When an interrupt activation is reported to the interrupt processing unit 7 by the IACK signal from the data processing unit 8, the AND gate 27 is opened in the interrupt processing unit 7, and the floating interrupt request held in the flip-flop 16 is passed through the OR gate 28. clear. And the floating interrupt request after the delay held in the flip-flop 25 is cleared. In addition, the selector 22 resets the value set in the floating interrupt delay cycle register 21 to the register 23 through the selector 22. Thus, I
In preparation for the next floating interrupt request transmitted from TC3 by signal FINT6.

Next, a floating interrupt acceptance process in the processor 1 and a floating interrupt acceptance notification process performed between the processor 1 and the ITC 3 via the control bus 4 and the data bus 5, that is, an interrupt request shown in FIG. Will be described. The data processing unit 8 that has received the floating interrupt activation request starts floating interrupt processing. The data processing unit 8 uses the ITC3
To the bus request unit 9 for notifying the acceptance of the floating interrupt and receiving detailed information of the interrupt. Then, the bus request unit 9 performs a bus arbitration operation for using the control bus 4 and the data bus 5, and tries to acquire the right to use the control bus 4 and the data bus 5. Since the bus arbitration operation is not an essential part of the present invention, a detailed description of the operation is omitted here.

If the right to use the control bus 4 and the data bus 5 can be acquired, the bus request unit 9 sets a FACK signal indicating a floating interrupt acceptance notification as a signal in the control bus 4. The NA indicating to the interrupt processing unit 7 that the own processor 1 is not using the bus
Negate the CK signal. Further, the BSTA signal indicating the start of the bus transfer operation is asserted. The BSTA signal and the FACK signal are transmitted to all other processors 1, the main storage device 2, and the ITC 3, and are simultaneously evaluated. By this evaluation, it is determined which of the other processor 1, the main storage device 2, and the ITC 3 performs a response operation to the bus transfer operation started by the processor 1. In this case F
Since the ACK signal is asserted, the ITC 3 responds, and the other processors 1 and the main storage device 2 do not respond.

Here, all other processors 1 which have not activated the bus transfer operation of the floating interrupt acceptance notification do not directly respond to the bus transfer operation. But,
In the interrupt processing unit 7 of each of the other processors, BS
The TA and FACK signals are asserted. NAC indicating that the control bus 4 and the data bus 5 are being used by other than the user.
The K signal is standing inside the processor. Therefore, AN
The D gate 29 opens to clear the flip-flops 16 and 25, which are floating interrupt information set internally through the OR gate 28. Further, the value held by the floating interrupt delay cycle register 21 is reset in the latch 23 through the selector 22. In this way, the floating interrupt request clearing operation is performed inside all the processors 1 except the bus transfer operation being started. By this clear operation, all the processors 1 other than the processor 1 that has obtained the bus use right and output the floating interrupt acceptance notification on the control bus 4 at the earliest start of the accepting process for the same single floating interrupt request. Can be deterred. The data processing unit 8 inside one processor 1
After the _RQ has already been received, there is a case where the other processor 1 starts the bus transfer operation of the floating interrupt acceptance notification. In this case, CANCEL cancels the floating interrupt accepting process from the interrupt processing unit 7.
The L signal is output to the data processing unit 8 and the bus request unit 9. Data processing unit 8 by CANCEL signal
Cancels the floating interrupt acceptance notification bus request. Further, the data processing unit 8 cancels the interrupt acceptance processing and returns to the continuation of the operation before the interruption.

The ITC 3 recognizes the bus transfer operation of the floating interrupt acceptance notification from the processor 1 based on the BSTA and FACK signals. The ITC 3 outputs the signal F to the data bus 5.
It outputs detailed interrupt information associated with the floating interrupt request that is asserting INT6. When ITC3 does not have a new floating interrupt factor, ITC3 outputs signal FIN.
Negate T6. If ITC3 has a new floating interrupt factor, ITC3 will continue to assert the FINT3 signal. Then, the ITC 3 asserts a BEND signal indicating completion of the bus transfer operation. The processor 1 that has issued the bus request receives B from the ITC 3
The floating interrupt detailed information is received from the data bus 5 upon seeing the assertion of the END signal, and the bus transfer operation of the floating interrupt acceptance notification ends. Further, the processor 1 transfers the floating interrupt detailed information from the bus request unit 9 to the data processing unit 8. Then, the processor 1 completes the floating interrupt acceptance notification bus request, and completes the floating interrupt acceptance processing.

As described above, this embodiment is a multiprocessor system composed of two or more processors. (1) The same interrupt is simultaneously requested to a plurality of processors and the earliest interrupt is accepted. Issue a floating interrupt request in which only the interrupted processor performs interrupt acceptance processing, issue detailed information associated with the floating interrupt request based on a floating interrupt acceptance notification from one processor, and perform processing for canceling the accepted floating interrupt request. An external interrupt controller, (2) a floating interrupt common signal line for connecting the external interrupt controller to all processors, and transmitting a floating interrupt request from the external interrupt controller to all processors, and (3) an external interrupt common signal line. Connected between the interrupt controller and all processors, and the processor and external interrupt A control common signal line composed of a plurality of signal lines used for controlling a signal transfer operation between the control units and notifying the floating interrupt acceptance from each processor to the external interrupt control unit; The external interrupt control unit is connected between the external interrupt control unit and all the processors, and transfers the floating interrupt accompanying information from the external interrupt control unit in response to the floating interrupt acceptance notification issued from one processor using the control common signal line. Each processor includes a common signal line composed of one or more signal lines, and each processor constantly monitors the floating interrupt common signal line and the control common signal line, and when a floating interrupt request is started, The floating interrupt request is not issued after completion of the floating interrupt acceptance notification operation between any one of them and the external interrupt control unit on the control common signal line. Characterized in that it recognizes the floating interrupt request with a one when is still held asserted by the interrupt common signal line.

Also, in this embodiment, after each processor recognizes a floating interrupt request, if it is in a wait state in which an interrupt can be accepted and an instruction is not being executed and an interrupt is waiting, the processor is not in a wait state. In such a case, a floating interrupt acceptance control means for activating the floating interrupt acceptance notification processing under any condition when an interrupt can be accepted after a point in time when a delay is independently inserted for each processor is provided. It is characterized by.

Further, the setting of the time for delaying the activation of the floating interrupt acceptance notification process after each processor recognizes the floating interrupt request is variable.

Further, after the floating interrupt request is recognized in each processor, the recognition is canceled when it is confirmed that the floating interrupt acceptance notification processing has been started by itself within the processor, or when a processor other than itself controls the common signal line. Is used to confirm that the notification of the acceptance of the floating interrupt request has been issued to the external interrupt control unit.

As described above, according to this embodiment, since the floating interrupt request signal is broadcast from the ITC to all the processors in the system configuration, the floating interrupt request signal line is provided. Independently, the effect on the system performance is suppressed, and the number of signal lines between each processor 1 and the ITC 3 is minimized, thereby suppressing the increase in the number of signal pins.

Further, a plurality of control common signal lines for transmitting a floating interrupt acceptance notification to an external interrupt control unit are provided, and the value on the control common signal line is constantly monitored by all processors, so that one processor can accept a floating interrupt. When the notification is issued to the ITC3, all other processors recognize the floating interrupt request notice on the control common signal line, recognize the floating interrupt request inside the processor, and control the communication of the already started floating interrupt request. By internally canceling the internal state before outputting to the line, the processor executing the floating interrupt accepting process controls the canceling operation of the floating interrupt accepting process for all other processors using a common signal line or the like. One processor that eliminates the need to perform There is an effect that the time required for the determination is shortened.

Further, the floating interrupt acceptance control means provided inside each processor, when recognizing the floating interrupt request, gives priority to the interrupt waiting state or the processor with the shortest interrupt delay time based on the state of each processor. By taking charge of the floating interrupt accepting process, the work load between the processors can be adjusted, and the processing efficiency can be improved as a whole multiprocessor system.

Embodiment 2 FIG. In the above embodiment, the control bus 4
In addition, the data bus 5 is shared with the memory bus for transferring data between the main storage device 2 and the processor 1, but the data bus 5 may be configured separately to achieve the same effect.

Embodiment 3 FIG. Further, in the above embodiment, an example of a multiprocessor system including two processors 1 is shown as shown in FIG. 1, but a similar effect can be obtained in a multiprocessor system configuration including three or more processors.

Embodiment 4 FIG. In the above embodiment, one interrupt processing unit 7 and one data processing unit 8 are provided for one processor connected to the control bus 4 and the data bus 5 as shown in FIG. As shown in FIG. 6, a configuration having two or more interrupt processing units 7a and 7b and two or more data processing units 8a and 8b may be provided, and the same effect can be obtained.

Embodiment 5 FIG. In the above embodiment, although not particularly described, one or a plurality of processors may be formed on the same semiconductor.

Embodiment 6 FIG. In the above embodiment, an example is shown in which the floating interrupt delay cycle register 21 in the interrupt processing unit 7 of each processor 1 is set to an independent value for each processor 1 in advance. May be set and shared by two or more processors. In this case, all the processors sharing the value start the interrupt acceptance notification all at once, but the collision between the processors can be avoided by the bus arbitration system.

[0060]

As described above, according to the present invention, the floating interrupt processing method in a multiprocessor system can be performed at a high speed, and the number of signal pins can be increased in response to the VLSI of a processor accompanying the progress of semiconductor technology. Can be minimized.

The control line is constantly monitored by all the processors, and the processors other than the processors that have notified the interruption acceptance voluntarily cancel the interrupt request and the pre-acquisition notice processing inside the processors on the basis of the floating interruption acceptance notice. This eliminates the need for the processor executing the interrupt accepting process to cancel the interrupt accepting process for all other processors.

Further, by transmitting the interrupt request and recognizing the interrupt request via the interrupt line, it is possible to avoid a reduction in the efficiency of the system due to an excess of the usage rate of the control line and the data line.

Further, the interrupt acceptance control provided inside each processor is based on the state of each processor when an interrupt request is recognized. Since it is in charge of processing, the processing efficiency of the entire multiprocessor system is improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the inside of one processor according to an embodiment of the present invention;

FIG. 3 is a logic diagram showing a configuration of an interrupt processing unit in a processor according to one embodiment of the present invention.

FIG. 4 is a processing flowchart showing a procedure of an interrupt processing unit inside the processor according to one embodiment of the present invention;

FIG. 5 is a processing flowchart showing a procedure of an interrupt processing unit in the processor according to one embodiment of the present invention.

FIG. 6 is an internal block diagram of a processor according to another embodiment of the present invention.

FIG. 7 is a configuration diagram showing a conventional multiprocessor system.

FIG. 8 is a configuration diagram showing another conventional multiprocessor system.

[Description of Signs] 1 Processor 3 External interrupt control unit 4 Control common signal line 5 Common signal line 6 Floating interrupt common signal line 7 Interrupt processing unit 8 Data processing unit 9 Bus request unit 100 Recognition process 200 Accepting process 300 Notification process

Claims (5)

(57) [Claims] An interrupt processing method having the following elements: (a) an interrupt line for transmitting an interrupt request; (b) a control line for transmitting control information; (c) a data line for transmitting data information; Connected to a control line and a data line, receives an interrupt request from the interrupt line, sends an interrupt acceptance notification to the control line, performs interrupt processing based on data information from the data line, and A plurality of processor means for monitoring and canceling the processing related to the interrupt request of the own processor when the other processor means receives the interrupt information; (e) connected to the interrupt line, the control line, and the data line; An interrupt line interrupt request is sent to the The interrupt controller for delivering using the data line data information necessary for interrupt processing to the processor unit which issued the interrupt acceptance notification to. 2. The processor means, after recognizing an interrupt request, waits for an interrupt in a state where an interrupt can be accepted and is not executing an instruction and is waiting for an interrupt. Claims characterized in that there is provided an interrupt acceptance control means for activating an interrupt acceptance notification process under any condition when an interrupt can be accepted after a point of time when an delay is inserted for an independently determined time. 2. The interrupt processing method according to item 1. 3. A comprising a plurality of processors, for the multiprocessor system (a) a plurality of processors having the following elements sends one common interrupt request, receive interrupt acceptance notification from one processor, the An external interrupt control device for transmitting additional information relating to the common interrupt request to one processor, receiving an acknowledgment of accepting the interrupt request, and terminating the common interrupt request, (b) the external interrupt controller and connecting a plurality of processors, the external interrupt control device transmitting the common interrupt request to a plurality of processors <br/> service from one common split <br/> interrupt line, (c) The external interrupt control device is connected to a plurality of processors, and a control signal between the external interrupt control device and the plurality of processors is connected to the plurality of processors. From one control line for transmitting an interrupt acceptance notification to the external interrupt controller, and connect (d) is the external interrupt control device and a plurality of processors, in response to the interrupt acceptance notification of the control line, the common interrupt A data line for transmitting additional information relating to the request, (e) provided in each of the plurality of processors,
Monitor the common interrupt line and use the common interrupt line
The above common interrupt request is accepted and assigned to the control line.
Sends a data transfer notification and adds data from the data line.
Perform interrupt processing based on the information
Monitors the control line and another processor accepts an interrupt request
Processing for the interrupt request of the own processor
Processor means to cancel. 4. A includes a plurality of processors connected by one common interrupt line and control lines and data lines an interrupt control unit, the common from the following interrupt processing method comprising the steps of (a) the interrupt control unit interrupt request sending step through the interrupt line to the delivery of one common interrupt request to a plurality of processors, the recognition that recognizes a plurality of processors common interrupt requests over (b) the common interrupt line (C) an accepting step of accepting the common interrupt request by at least one processor; and (d) an interrupt control unit by one of the processors accepting the common interrupt request. Control line
(E) sending an interrupt acceptance notification from the interrupt control unit
A transmitting step of transmitting information relating to the interrupt request to the issuing processor via the data line; (f) first receiving an interrupt among the plurality of processors
When another processor detects an interrupt acceptance notification on the control line from the processor that sent the notification ,
Clearing step in which the processor of (1) clears acceptance of the common interrupt request. Wherein said accepting step, the processor and the time of the interrupt waiting state waiting, the processor is predetermined for each processor delays
Above interrupt when either time runs out
5. A notice of acceptance of a request for a request.
The described interrupt handling method.