JP2842002B2 - Frame synchronizer for PCM broadcast receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to frame synchronization or frame synchronization cancellation in demodulation of PCM broadcast signals, and can be used for demodulation of PCM audio signals of direct satellite broadcast.

[0002]

2. Description of the Related Art In recent years, there has been a movement in various countries around the world to convert audio signals to PCM for high-quality audio broadcasting. In Japan, television broadcasting using broadcasting satellites has already been carried out. In the future, the use of the PCM method for audio in high-definition broadcasting, clear vision broadcasting, audio-only broadcasting, and the like will be implemented, studied, and planned.

[0003] In the transmission of such a PCM signal, a frame structure composed of a fixed number of bits is used. In order to synchronize the frame on the receiver side,
A frame synchronization pattern is set in this frame.
On the receiver side, in order to detect the position of this frame synchronization pattern, pattern matching with the true frame synchronization pattern is performed, and if all bits match or a bit error is allowed, a pattern matching signal is generated. Output. If this frame synchronization is not accurate and stable,
Demodulation of the PCM signal becomes completely impossible.

Therefore, the frame synchronizer must not: (a) erroneously synchronize at a location other than the synchronization pattern; (B) Once synchronization has been achieved, synchronization can be maintained even if there are slight bit errors. is important.

[0005] An example of a conventional frame synchronizer will be described below with reference to the drawings. FIG. 6 shows a conventional frame synchronizer (see Japanese Patent Application No. 58-200328).
It shows. In FIG. 6, a pattern detection means 51 capable of switching a threshold value X of the number of coincident bits by a synchronous state signal outputs a coincidence signal a and a non-coincidence signal b and counts the coincidence signal a N times consecutively. Circuit 5
2 outputs a synchronization signal c, and outputs an asynchronous signal d from an asynchronous detection circuit 53 that counts the mismatch signal b consecutive M times. The flip-flop 4 is set by the synchronization signal c, the flip-flop 4 is reset by the asynchronous signal d, and the synchronization detection circuit and the asynchronous detection circuit are reset via the OR circuit 5. If the synchronous state signal output from the flip-flop 4 is at a low level and is assumed to be in an asynchronous state, the threshold X of the pattern detecting means 51 is set to A1 at this time, and the threshold is set when the synchronous state signal is at a high level, that is, in the synchronous state. The value X is switched to A2. Usually, A1 ≧ A2 is set.

FIG. 7 is a block diagram showing an example of the internal configuration of the pattern detecting means 51 in NTSC direct satellite broadcasting or HDTV broadcasting. The 16 bits “0” of the frame synchronization pattern included in the digital data signal
"00100110101110" is read into the shift registers 61 of the same number of stages as the code length. The output of the shift register 61 is taken out in parallel from Q1 to Q16 and inputted to the pattern matching circuit 62. Q4, Q7, Q8, Q
The inverting circuit inserted between the outputs of 10, Q12, Q13, Q14, and Q15 and the pattern matching circuit 62 has a configuration in which 1 (high level) is input to the pattern matching circuit 62 when the frame synchronization pattern does not match. ing. The pattern matching circuit 62 counts the number of 1 to detect the number of matching bits with the true frame synchronization pattern, and the value is A1
It has two systems of outputs indicating whether or not it is greater than or equal to A2. Next, in the selection circuit 63, a signal indicating whether or not the synchronization state signal is equal to or higher than A1 when the synchronization level signal is low, and whether or not equal to or higher than A2 when the synchronization state signal is high level is selected and output as a coincidence signal. The non-coincidence signal can be obtained by inverting the coincidence signal by the inversion circuit 64. As described above, by enabling the threshold value of the number of coincident bits to be independently set according to the synchronous state and the asynchronous state, a frame synchronizer extremely resistant to bit errors is realized.

[0007]

In such a conventional example, the frame synchronizer needs at least M frames to transition from the synchronous state to the asynchronous state, and at least N frames to transition from the asynchronous state to the synchronous state. Frame time is required.

[0008] Therefore, the digital data signal is transmitted when the channel of the satellite broadcast receiver is switched, when the broadcast station is switched, when the MUSE broadcast and the NTSC broadcast are switched, or when the MUSE laser disk is specially reproduced. May be interrupted. At this time, the frame synchronizer needs at least M frames of time to transition from the synchronous state to the asynchronous state. There has been a problem that non-data information is output during the time until the transition to the asynchronous state, and a shock noise is generated.

On the other hand, if the number of consecutive detections M of the asynchronous detection is reduced, it is possible to shorten the transition time to the asynchronous state and prevent the occurrence of shock noise. There has been a new problem that a stable system operation cannot be obtained by repeating the operation.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a relatively simple circuit that can maintain a strong frame synchronization protection at a low C / N, and that can quickly transition to an asynchronous state when a digital data signal is interrupted or switched. It is intended to provide a synchronization device.

[0011]

SUMMARY OF THE INVENTION In order to solve the above problem, a frame synchronizer for a PCM broadcast receiver according to the present invention comprises: a pattern detecting means for detecting a frame synchronization pattern and outputting a mismatch signal and a match signal; An asynchronous detection circuit that outputs an asynchronous signal when a signal is continuously detected M times in a frame period; a synchronization detection circuit that outputs a synchronization signal when the coincidence signal is detected N times in a frame period; and a majority decision of the control bits A control bit detector for detecting the non-broadcasting information when the control bit detector detects any bit indicating non-broadcasting information. The number of continuous detections M of the circuit is changed, or the number of continuous detections N of the synchronous detection circuit is changed, or the threshold X of the pattern detection means is increased. And it has a structure of changing all the continuous detection number N of consecutive detection count M and the sync detection circuit of the asynchronous detection circuit.

According to a second aspect of the present invention, an error correction detection circuit changes the threshold value X of the pattern detection means of the first aspect of the invention or changes the number of continuous detections M of the asynchronous detection circuit. Alternatively, the number of continuous detections N of the synchronous detection circuit is changed, or the threshold value X of the pattern detection means, the number of continuous detections M of the asynchronous detection circuit, and the number of continuous detections N of the synchronous detection circuit are all changed. It has a configuration.

According to a third aspect of the present invention, in addition to the first aspect of the present invention, a horizontal synchronizing signal detector for detecting a horizontal synchronizing signal and a video asynchronous when a horizontal synchronizing signal is not detected continuously Y times in a horizontal cycle. A video asynchronous detection circuit that outputs a signal, and has a configuration in which a synchronous state is released by a video asynchronous signal of the video asynchronous detection circuit and an asynchronous signal of the asynchronous detection circuit.

According to a fourth aspect of the present invention, in addition to the second aspect, a horizontal synchronizing signal detector for detecting a horizontal synchronizing signal and a video asynchronous when a horizontal synchronizing signal is not detected continuously Y times in a horizontal cycle. A video asynchronous detection circuit that outputs a signal, and has a configuration in which a synchronous state is released by a video asynchronous signal of the video asynchronous detection circuit and an asynchronous signal of the asynchronous detection circuit.

[0015]

According to the present invention, when the channel of the satellite broadcast receiver is switched, when the broadcast station is switched, M is used.
Shock noise is not generated even when the digital data signal is interrupted at the time of switching between the broadcast of the USE system and the broadcast of the NTSC system, or during the special reproduction of the MUSE laser disk. In other words, by controlling the conventional frame synchronizer using various kinds of information such as control bit information, the number of errors in digital data, and the synchronization state of the horizontal synchronization signal, it is possible to prevent interruption or switching of the digital data signal. High-speed transition to asynchronous state and low C
/ N, stable operation can be achieved, and it can be realized with a relatively easy circuit configuration.

[0016]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. 1, 2, 3, 4, 5, and 6, the same numbers and the same reference numerals indicate the same items.

The digital data signal is inputted to a pattern detecting means 1 capable of switching a threshold value X of the number of coincident bits of the frame synchronization pattern, and a coincidence signal a and a non-coincidence signal b are outputted. The configuration of the pattern detecting means 1 is basically the same as the configuration of FIG. Then, a synchronization signal c is output from the synchronization detection circuit 2 which counts the coincidence signal a N times consecutively, and an asynchronous detection circuit 3 which counts the non-coincidence signal b continuously M times.
Asynchronous signal d is output from the sets the flip-flop 4 by the synchronization signal c, and resets the flip-flop 4 in the asynchronous signal d. Also, the O of the synchronous signal c and the asynchronous signal d
The synchronous detection circuit 2 is activated by a reset signal e output from the R circuit 5.
And the asynchronous detection circuit 3 is reset. If the synchronous state signal output from the flip-flop 4 is at a low level and is assumed to be in an asynchronous state, the threshold value X of the pattern detecting means 1 at this time is A1, and when the synchronous state signal is at a high level, that is, when the synchronous state signal is in a synchronous state. The threshold value X is switched to A2.
Usually, A1 ≧ A2 is set. On the other hand, the digital data signal is also input to the control bit detector 6, and a majority decision is made for each bit.

In the case of the MUSE signal, the 18th to 22nd control bits are assigned as non-broadcast control bits. In the case of the non-broadcast system, the C / N is hardly degraded and the digital data signal is interrupted. What is necessary is just to consider the measures against. Therefore, the value of the number M of continuous counts of the asynchronous detection circuit 3 is set to M = 5 in the normal system, but the signal is interrupted by setting M = 2 when a non-broadcasting control bit is detected. In this case, a transition from a synchronous state to an asynchronous state is made within two frames, thereby preventing the occurrence of shock noise in a non-broadcast system.

Next, a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. In FIG. 2, the difference from the configuration of FIG. 1 is that there is no block of the control bit detector 6, and instead the digital data signal is input to the deinterleave processing 7 and the output after the processing is output to the error correction detection circuit 8 in the error correction block unit 8. Is corrected or detected. The error correction pulse f is output at the timing of the bit position to be corrected in the correction block, and the error detection pulse g is output at the end of the correction block by detecting that it is uncorrectable but incorrect in the correction block. Is output. Error correction pulse f
Is counted by the counter 9 and the error detection pulse g is counted by the counter 1
The counter value is counted as 0, and each counter value is set in the error determination circuit 1
1 is calculated as the number of errors. Basically, one error correction 2
If an error is detected, the number of errors is calculated as the counter value of the counter 9 × 1 and the counter value of the counter 10 × 2. In the error determination circuit 11, when there is a sudden change in the number of errors, each of the threshold value X of the pattern detection circuit 1, the number N of continuous counts of the synchronous detection circuit 2, and the number M of continuous counts of the asynchronous detection circuit 3 Control the value.

[0021]

[Table 1]

The operation of the frame synchronizer configured as described above will be described with reference to FIGS. 8 and 9 (Table 1). In FIG. 8, an error correction detection circuit 8 is provided for each correction block.
Works. One frame is composed of L blocks = 63 bits and K blocks = 32 blocks in the direct satellite broadcasting NTSC system, and one frame is composed of L blocks = 82 bits and K blocks = 16 blocks in the MUSE system. . Since 1 error correction and 2 error detection are performed in the broadcast, the error correction pulse f and the error detection pulse g are 1 per block.
It is output only once. The error determination circuit 11 determines the error by calculating the number of errors in one frame period. Table 1 shows an example of an error determination criterion based on the number of errors. The range of ◎ for error determination is almost the entire number of errors that can be corrected, and the range of ○ for error determination is the number of errors that can be corrected for almost all but requires interpolation of some data. The range of Δ is the number of errors that can be partially corrected, but almost requires data interpolation processing, and the range of × for error determination is almost all the number of errors that require interpolation processing. In FIG. 9, the symbols N0 to N12 are assigned to frames, and will be described in detail. Period R of N0 to N2 and period R 'of N9 to N12
Is a digital data signal input, but the signal is interrupted from the middle of N3 and continues to be interrupted in the period from N4 to N7 to N8.
Shows a state where a digital data signal is input from the middle of the process. The coincidence signal a is output during R and R ', and the non-coincidence signal b is output during S. At this time, in the error determination, the error determinations of the frames one frame apart, for example, N2 and N4, change greatly from ◎ to ×, while N7 and N
The error judgment of No. 9 also greatly changes from × to ◎. The error determination circuit 11 changes the output signal when detecting such a state.

Due to this change in the output, for example, the value of the number M of continuous counts of the asynchronous detection circuit 3 is set to M = 5 in a normal system, but when the output of the error determination circuit 11 is at a high level, M = 2. Therefore, when the signal is interrupted, the state changes from the synchronous state to the asynchronous state within two frames, and when the channel switching operation of the satellite broadcast receiver, the switching of the broadcasting station, the broadcasting of the MUSE system and the broadcasting of the NTSC system are performed. In any case, such as at the time of switching, or in any case such as special reproduction of a MUSE laser disk, the occurrence of shock noise is prevented.

Next, a third embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. 3 differs from the configuration of FIG. 1 in that a MUSE signal is converted into a digital signal by an A / D converter 12 to separate a video signal and an audio signal. The value conversion, the time axis expansion, and the deinterleaving process are performed, and the same detection as in FIG. 1 is performed as the MUSE digital data signal h. On the other hand, for the video signal, the horizontal synchronization signal detector 13 detects the horizontal synchronization signal in the horizontal cycle, and the video asynchronous detection circuit 14 outputs the video asynchronous signal i if the horizontal synchronization signal is not detected continuously Y times. The logical product of the state signal and the AND circuit 16 is obtained. AN
The output of the D circuit is logically ORed with the asynchronous signal d by the OR circuit 17 and connected to the reset input R of the flip-flop 4 to reset the flip-flop 4. That is, it is set to the asynchronous state. Here, an example of a basic circuit diagram of the horizontal synchronization signal detector 13 and the video asynchronous detection circuit 14 is shown in FIG.
Shown in A horizontal synchronizing signal is detected by using the most significant bit (MSB) of the MUSE signal as an input signal. As shown in FIG. 10, four samples before and after the sixth sample at level 128/256 are leveled up and down. 6
It has a difference of 4/256 and is detected by this level change. The polarity of the horizontal synchronizing signal is different between the even-numbered line and the odd-numbered line, and the polarity of the horizontal synchronizing signal input by the EXOR 30 is matched using a line inversion signal that is inverted for each line. The output of the EXOR 30 is input to the delay circuit 26 and the inverting circuit 31. Inverting circuit 3
1 is the seventh sample in FIG. 10, the delay circuit 2
6 is configured to coincide with the second sample in FIG. 1 by the output of the delay circuit 26
There are a counter 27 that counts with a 6.2 MHz clock and a counter 28 that counts with a 16.2 MHz clock based on the output of the inverting circuit 31. Each of the counters 27 and 28 receives the second and seventh samples of FIG. Immediately before, the count value is reset by the reset signal of the horizontal cycle. Then, the counters 27 and 28 set a threshold value ( for example,
4 ), the counters 27 and 28 output a high level and are ANDed by the AND circuit 40. The output of the AND circuit 40 is input to the data latch 41 with a clock having a horizontal period. .., 4 (Y-1), 4Y are sequentially input each time a horizontal cycle clock is input. Whether the horizontal synchronizing signal is detected continuously Y times by this data latch or not is output to the NOR circuit 3
5, the video asynchronous signal i is obtained.

According to the third embodiment configured as described above, the horizontal synchronizing signal always exists in each line from FIG. 11 showing the transmission signal format of the MUSE signal.
Since the detection is performed as soon as the USE signal is interrupted, the frame synchronizer can be brought into the asynchronous state before detecting the interruption of the audio digital data signal.
In other words, in the case of non-broadcasting, the interruption of the signal can be reliably detected and the signal can be put into an asynchronous state. Further, by changing the threshold value of the counters 27 and 28 or the Y value of the number of times that the horizontal synchronizing signal is not detected continuously. Even when the C / N is low, the synchronization can be stably ensured, and the asynchronous state can be accurately and quickly set only when the signal is interrupted.

Next, a fourth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. 4 is different from the configuration of FIG. 3 in that the control bit detector 6 does not have a block, and instead, the frame synchronization device is controlled by error correction detection information.

According to this configuration, when the channel of the satellite broadcast receiver is switched, when the broadcast station is switched, when the MUSE broadcast and the NTSC broadcast are switched, or when the MSC broadcast is switched.
In all cases, such as in special reproduction of a USE laser disk, a transition to an asynchronous state is performed at high speed to prevent the occurrence of shock noise, and a stable synchronous state is reliably maintained at low C / N.

Next, a fifth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. The configuration is a combination of the techniques of FIGS.

According to this configuration, at the time of a channel switching operation of a satellite broadcast receiver, at the time of switching of a broadcasting station, at the time of switching between MUSE broadcast and NTSC broadcast, or
In any case, such as special reproduction of a USE laser disk, the asynchronous state is accurately and quickly transited to the asynchronous state to prevent the occurrence of shock noise, and to stably maintain the synchronous state at low C / N.

[0030]

As described above, according to the present invention, not only the synchronous / asynchronous control is performed by detecting the frame synchronization pattern,
Information on control bits, information on error correction detection, information on horizontal synchronization signals, etc., when switching the channel of a satellite broadcast receiver, when switching between broadcast stations, when switching between MUSE broadcast and NTSC broadcast Or MUSE
Optimal information in all cases, such as laser disk special playback, accurately and quickly controls the synchronization characteristics to prevent the occurrence of shock noise and low C / N
At times, the synchronization state is reliably maintained. Furthermore, by setting various parameters finely, an optimal system design is possible, and it can be realized with a relatively simple circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of a frame synchronizer of a PCM broadcast receiver according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a frame synchronizer of a PCM broadcast receiver according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a frame synchronizer of a PCM broadcast receiver according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a frame synchronizer of a PCM broadcast receiver according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram of a frame synchronizer of a PCM broadcast receiver according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram of a conventional frame synchronizer of a PCM broadcast receiver.

FIG. 7 is a block diagram of a pattern detection unit.

FIG. 8 is an operation explanatory diagram of an error correction detection circuit.

FIG. 9 is an explanatory diagram of an operation in the second embodiment of the present invention.

FIG. 10 is a diagram showing a horizontal synchronization signal waveform.

FIG. 11 is a diagram showing a transmission signal format of the MUSE system.

FIG. 12 is a basic circuit diagram of a horizontal synchronization signal detector and a video asynchronous detection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pattern detection means 2 Synchronous detection circuit 3 Asynchronous detection circuit 4 Flip-flop 6 Control bit detector 8 Error correction detection circuit 11 Error judgment circuit 13 Horizontal synchronization signal detector 14 Video asynchronous detection circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 7/08 H04J 3/06 H04N 5/60 H04N 7/20

Claims (5)

(57) [Claims] 1. A frame synchronization apparatus for a PCM broadcast receiver for receiving a digital data signal transmitted while having a frame structure including a frame synchronization pattern including a plurality of bits and a control bit, and detecting the frame synchronization pattern. Therefore, a pattern detecting means for outputting a mismatch signal when the number of matching bits with the true frame synchronization pattern is less than the threshold value X and outputting a matching signal when matching is detected, and detecting the mismatch signal continuously M times in a frame cycle An asynchronous detection circuit that outputs an asynchronous signal, a synchronous detection circuit that outputs a synchronous signal when the coincidence signal is continuously detected N times in a frame cycle, and a control bit detector that makes a majority decision on the control bits. When any of bits indicating non-broadcast information is detected by the control bit detector, The threshold value X is changed, or the number of continuous detections M of the asynchronous detection circuit is changed, or the number of continuous detections N of the synchronous detection circuit is changed, or the threshold value X of the pattern detection means and the asynchronous detection are changed. The number of continuous detections M of the circuit and the number of continuous detections N of the synchronous detection circuit
A frame synchronizer for a PCM broadcast receiver, characterized in that: 2. A frame synchronization apparatus for a PCM broadcast receiver for receiving a digital data signal transmitted while having a frame structure including a frame synchronization pattern including a plurality of bits and a control bit, and detecting the frame synchronization pattern. Therefore, a pattern detecting means for outputting a mismatch signal when the number of matching bits with the true frame synchronization pattern is less than the threshold value X and outputting a matching signal when matching is detected, and detecting the mismatch signal continuously M times in a frame cycle An asynchronous detection circuit that outputs an asynchronous signal at the time, a synchronization detection circuit that outputs a synchronization signal when the coincidence signal is continuously detected N times in a frame cycle, and an error detection pulse when an error of the digital data signal is detected. An error correction detection circuit that corrects an error in the digital data signal and outputs an error correction pulse; A first counter for counting the number of corrections in the frame by the correction pulse, a second counter for counting the number of detections in the frame by the error detection pulse, and an error count by the count value of the first and second counters An error judgment circuit for judging whether the threshold value X of the pattern detection means is changed or the number of continuous detections M of the asynchronous detection circuit is changed according to the judgment result of the error judgment circuit. Or the number of continuous detections N of the asynchronous detection circuit and the number of continuous detections N of the synchronous detection circuit are all changed. Frame synchronizer for broadcast receiver. 3. A horizontal synchronizing signal detector for detecting a horizontal synchronizing signal from the A / D-converted MUSE signal, and a video asynchronous signal when the horizontal synchronizing signal is not detected by the horizontal synchronizing signal detector continuously Y times in a horizontal cycle. 2. A frame synchronization apparatus for a PCM broadcast receiver according to claim 1, further comprising: a video asynchronous detection circuit for outputting a video signal, wherein a synchronous state is released by a video asynchronous signal of the video asynchronous detection circuit and an asynchronous signal of the asynchronous detection circuit. . 4. A horizontal synchronizing signal detector for detecting a horizontal synchronizing signal from the A / D converted MUSE signal, and a video asynchronous signal when the horizontal synchronizing signal is not detected by the horizontal synchronizing signal detector continuously Y times in a horizontal cycle. 3. A frame synchronization device for a PCM broadcast receiver according to claim 2, further comprising a video asynchronous detection circuit for outputting a video signal, wherein the synchronous state is released by a video asynchronous signal of the video asynchronous detection circuit and an asynchronous signal of the asynchronous detection circuit. . 5. A horizontal synchronizing signal detector for detecting a horizontal synchronizing signal from the A / D-converted MUSE signal, and a video asynchronous signal when the horizontal synchronizing signal is not detected by the horizontal synchronizing signal detector continuously Y times in a horizontal cycle. A non-coincidence signal is output when the number of coincidence bits with a true frame synchronization pattern for detecting a frame synchronization pattern of an audio digital data signal is less than a threshold value X, and a coincidence signal is output when a match is detected. , A non-synchronous detection circuit that outputs an asynchronous signal when the non-coincidence signal is detected consecutively M times in a frame period, and outputs a synchronous signal when the all coincidence signal is detected N consecutive times in a frame period. A synchronization detection circuit; a control bit detector for determining a majority of control bits of the audio digital data signal; And an error correction detection circuit that corrects the error and outputs an error correction pulse when an error of the data signal is detected, a first counter that counts the number of corrections in a frame by the error correction pulse, A second counter for counting the number of detections in a frame by an error detection pulse; and an error determination circuit for determining the number of errors based on the count values of the first and second counters. The threshold value X of the pattern detection means is changed when any bit indicating the system information is detected or according to the determination result of the error determination circuit, or the number of continuous detections M of the asynchronous detection circuit is changed, or The number of continuous detections N of the synchronous detection circuit is changed, or the threshold X of the pattern detection means, the number of continuous detections M of the asynchronous detection circuit, and the synchronization detection Frame synchronization device for PCM broadcast receiver and cancels the synchronization state by an asynchronous signal of the video asynchronous signal and the asynchronous detection circuit of the video asynchronous detection circuit with changing all of the continuous detection number N of the road.