JP2840368B2 - Facsimile machine - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a facsimile apparatus, and more particularly, to a facsimile apparatus that performs smoothing processing on binary image data received from a partner communication apparatus, converts the data into high-resolution data, and records the converted data.

[Conventional technology]

2. Description of the Related Art It has been known that binary image data received by a facsimile apparatus is subjected to pixel density conversion, subdivided, and recorded.

[Problems to be solved by the invention]

However, conventionally, for example, data received at 7.7 lines / mm (fine) was converted to twice the pixel density of 15.4 lines / mm (super fine) by the same processing regardless of whether it was a character image or a photographic image. When an image in which pixels and a halftone image are mixed is received, there is a disadvantage that the edge of the character portion is crushed and the gradation of the halftone image cannot be reproduced well.

The present invention eliminates the disadvantages of the prior art described above, and identifies whether received binary image data is a character image or a halftone image,
In the case of a character image, it is intended to provide a facsimile device that converts to high-resolution data by smoothing processing and that can smoothly reproduce the edge of the character portion and prevent the halftone image from deteriorating. The resolution of the received binary image data is determined based on the transmitted procedure signal, and one of a plurality of smoothing processes is selected according to the resolution, so that the optimum smoothing is performed according to the resolution of the received binary image data. It is an object of the present invention to provide a facsimile apparatus capable of performing processing and recording a high-quality character image.

In order to achieve the above object, a facsimile apparatus of the present invention includes a receiving unit that receives binary image data of a first resolution or a second resolution higher than the first resolution sent from a partner communication device. Determining means for determining whether the resolution of the binary image data received by the receiving means is one of the first and second resolutions based on a procedure signal sent from the partner communication device; From the obtained binary image data,
Identifying means for identifying whether the received binary image data is a character image or a halftone image; and a third resolution having a higher resolution than the first and second resolutions based on the binary image data received by the receiving means. Recording means for recording an image; first smoothing processing means for smoothing binary image data of the first resolution received by the receiving means to convert the binary image data into data of a third resolution; receiving by the receiving means Second smoothing processing means for performing smoothing processing on the binary image data having the second resolution to be converted into data having the third resolution. If the received binary image data is determined to be data of the first resolution when the image is identified as an image and the received binary image data is data of the first resolution, the first smoothing processing means performs smoothing. When an image is recorded based on the data subjected to the jing process, the identification unit identifies the received binary image data as a character image, and the determination unit determines that the received binary image data is data of the second resolution. Is characterized in that an image is recorded based on data smoothed by the second smoothing processing means.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a facsimile apparatus according to one embodiment of the present invention. FIG. 1 shows blocks used for receiving data directly related to the present embodiment.

In FIG. 1, reference numeral 1 denotes an image processing unit which performs subdivision processing on image data (binary data) sent from a partner facsimile apparatus and performs interpolation processing (smoothing) on a character image. When the transmission density is specified as 3.85 lines / mm (standard) in the sub-scanning direction by the procedure signal received from the other party's facsimile apparatus, the image processing unit 1 performs a four-fold smoothing process. 7.
In the case of 7 lines / mm (fine), a double smoothing process is performed. If data is sent from the partner device at 15.4 lines / mm (super fine), the image processing unit 1 does not perform the subdivision and smoothing processing.

2 is a modem for demodulating data on the line,
Is a CPU that controls the entire system, 4 is a reception data decoding unit that decodes reception data sent from the modem 2, and 5 is an image recording unit based on the binary decoding sent from the image processing unit 1. And a full multi-type recording unit such as a thermal head or an ink jet printer. The recording unit 5 receives a latch signal and a strobe signal from the CPU 3. 7 is a facsimile transmitter.

3-a and 3-b are signals exchanged between the modem and the CPU, and a procedure signal indicating the resolution of the transmission data transmitted from the facsimile transmitter is transmitted from the modem 2 to the signal 3-.
It is sent to the CPU 3 as a.

23-g, 21-b, 23-h and 23-i are signals for transmitting various data from the CPU 3 to the image processing unit 1. 23−
g is a start pulse signal, and when the image processing unit 1 subdivides data of one line in the main scanning into 2 or 4 lines,
It becomes a reference signal when subdividing the data of the second and subsequent lines to be subdivided. 21-b is a signal for selecting one of a plurality of data output from the image processing algorithm unit 19 in FIG. 4 described later. Note that the image processing algorithm unit 19 has four data when one pixel in one line is output as data for four lines, two data when output as data for two lines, and one data when no conversion is performed. Output a total of seven data.

Reference numeral 23-h denotes a buffer clear pulse used to clear the RAM 13 used as a plurality of line memories shown in FIG.

Reference numeral 11-a denotes serial image data decoded by the reception data decoding unit 4, which is input to the image processing unit 1 in synchronization with the transfer clock 23-a.

FIG. 2 is a diagram for explaining a flow of a procedure signal exchanged between a facsimile apparatus on the transmitting side and a facsimile apparatus on the receiving side.

FIG. 2A shows a procedure signal for calling the receiving side, CE of B
D is a procedure signal indicating that the receiving terminal is a non-voice terminal, C is a procedure signal indicating that the NSF is a non-standard device, C
SI is a procedure signal for notifying the telephone number of the receiving side, and DIS is a procedure signal for notifying that the receiving side has the CCITT standard function. Among the NSS, TSI, and DCS of D, NSS is a procedure signal for responding to the above-mentioned NSF, TSI is a procedure signal for notifying the telephone number of the transmitting side, and DCS is a procedure signal for responding to the above-mentioned DIS. In this embodiment, the transmitting side designates whether the transmission data is to be transmitted by standard, fine, or super fine using the NSS and DCS. The receiving side selects quadruple or double pixel density conversion or no conversion according to the designation of the pixel density. E TRAINING is a training signal, and TCF is a training check signal. The CFR of F is a procedure signal for notifying the transmitting side that the pre-procedure has been completed and message transmission can be started, and G represents image data. The Q signal of H is any of EOP, EOM, and MPS. In the case of EOP, it is a procedure signal for notifying the end of the procedure. When the MCF (message confirmation signal) of I is received, the line is disconnected by the DCN of J. Q
When the signal is EOM (message end signal), it indicates that the mode is changed and the next page is further transmitted.
After transmitting EOM, the procedure returns to the NSS procedure of D. If the Q signal is an MPS (multi-page signal), it indicates that the next page is to be transmitted without changing the mode, and returns to the G message transmission.

Fig. 3 shows the operation when extracting the resolution information of the transmission data from the NSS and DCS sent from the transmitter side, and selecting any of 2 times smoothing, 4 times smoothing and not performing smoothing based on it. FIG. This flowchart is executed by the CPU 3 shown in FIG. When the three smoothing modes are determined by the CPU 3, the modes are notified to the image processing unit 1 by 21-b. The image processing unit 1 selects a signal from an image processing algorithm unit 19 shown in FIG.

In FIG. 3, in step S1, it is determined whether or not there is a call from the transmitting side. If there is a call, the process proceeds to step S2 and CED
Is sent. Next, when NSS and DCS are received from the transmitting side, the process proceeds to step S4, and the resolution information declared in NSS and DCS is extracted. As a result, if the resolution is specified as 15.4 lines / mm, that is, super fine, the process proceeds to step S6 so that the smoothing process is not performed.

In step S57, a double smoothing process of 7.7 lines / mm → 15.4 lines / mm is selected in step S8 in which the resolution is designated as 7.7 lines / mm, ie, fine. If no fine is specified in step S7, the resolution is
It is determined that 3.85 lines / mm, that is, the standard is designated, and the flow advances to step S9 to select a smoothing process four times from 3.85 lines / mm to 15.4 lines / mm.

The mode selected in steps S6, S8 and S9 is sent to the image processing section 1 by 21-b.

At step S10, the CFR is transmitted, and at step S11, the message is received. If the EOP is received in step S12, the MCF is sent out in step S13, and if the DCN is received in step S14, the process proceeds to S15 to disconnect the line and end the processing. Step S
When the MPS is received at step 16, the process advances to step S11 to receive the message of the next page. When the EOM is received in step S17, the process returns to step S3, and the mode signal for the next page is set to NS.
S, received by DCS. If the procedure signal contains resolution information, the smoothing process is switched by the processes in steps S4 to S9 described above.

FIG. 4 is a block diagram showing details of the image processing unit 1. Reference numeral 11 denotes a D flip-flop for performing a line shift in the sub-scanning direction of image information to be referred to for performing image processing, 13 denotes a RAM for storing six lines of image information to be referred to, and 15 and 17 refer to. A shift register group for performing a bit shift of image information to be processed; 19, an image processing algorithm unit for performing double and quadruple smoothing processing; 21, image data output from the image processing algorithm unit 19;
A multiplexer for selecting and outputting based on the resolution data sent from the FF, a clock for D flip-flop 11, a clear, a write for RAM 13, an address, a clock for shift registers 15, 17 and a clear signal , And a control block for outputting data clocks and the like.

In the above configuration, the recording system interpolation processing (smoothing processing) will be described. When transmitting and receiving in a facsimile, if the maximum density of the sub-scanning line when performing recording on the receiving side is higher than the scanning line density of the transmission data on the transmitting side,
For example, when the transmission is performed in the standard mode and the receiver records in the super fine mode, one pixel of the received data is set to 4 pixels.
Subdivide into two. The data of the subdivided pixel is determined according to data around the pixel of interest.

The information on the linear density from the transmitting side is declared in the NSS and DCS described in FIG. 2 and FIG.

FIG. 5 is a diagram showing an example in which received data of one pixel is subdivided.

In FIG. 5, when data is sent in the standard mode from the transmitting side to the pixel of interest indicated by hatching,
a to 19-d are subdivided into four pixels.
e, 19-f. When the data is sent in the super-fine mode, 19-g data which is not subdivided is selected. In order to determine the subdivided pixel data, a reference area of 6 lines × 9 pixels is used.

In the present embodiment, image area separation of a character and a halftone image is performed from the binary image data of 6 lines × 9 pixels, and a smoothing process is performed only on the character. For the halftone image, the same data as the received data is output as subdivided pixels.

FIG. 6 is a view for explaining an example in which received data is subjected to double smoothing processing in the sub-scanning direction.

FIG. 6 (a) shows the received binary data, and FIG. 6 (b) shows the result of performing double smoothing processing in the sub-scanning direction in the present embodiment. Thus, a smooth image with few steps can be reproduced at the edge portion. When performing smoothing processing on the pixels indicated by oblique lines in FIG. 5, the binary image data of 19-e and 19-f are determined using the binary image data of 6 pixels × 9 pixels around as reference pixels. In FIG. 4, the received serial data Di is input from 11-a in synchronization with the clock from the decoding unit 4.

Then, as shown in FIG. 7, the data is latched to 1Q of the D flip-flop 11 by the 23-b clock, and at the same time, the data of O1 to O5 of the RAM 13 at the address at that time are also changed to 2Q to 6Q.
It is spatula. The 1Q to 6Q data latched to the D flip-flop 11 is input to the input section of i1 to i6 of the RAM 13, and is written by the WR signal of 23-e. At that time,
Focusing on the data written to the RAM 13, the data written to I1 is the serial image data, and the data written to i2 is the image data at the same address of the previous line read from O1. Similarly, data of three lines before i3 is written to i3, three lines before... I5 is written five lines before. That is, as described above, the reference data area can be shifted by one line in the sub-scanning direction by reading and writing the data of the RAM while shifting the data one bit at a time.

Then, the data of O1 to O6 in the RAM 13 is shifted to the shift registers 15 and 17. The shifted data is P in FIG. It corresponds to 1Q to 6Q in 9 rows.

The shift of the reference data area in the main scanning direction is as follows.
This is performed by inputting a 23-d shift register clock synchronized with the input serial image data to the shift registers 15 and 17.

The reference data (6 × 9 = 54 pixels in FIG. 5) prepared as described above is input to 19 image processing algorithm units. The 19 image processing algorithm unit simultaneously outputs the interpolated subdivided pixel data to 19-a to 19-g based on the input reference data. 19-a to 19-d are pixel data when one pixel is subdivided into four pixels (superfine recording by standard reception) 19-e to 19-f are pixel data when subdivided into two pixels, 19 −g is the pixel data when no segmentation is performed (in this case, no interpolation is performed and the pixel data of interest remains as it is).

Then, the main scanning is performed a plurality of times on the received pixel data for one main scanning to record the subdivided pixels. The standard reception and superfine printing of four subdivided pixels will be described as an example. I do. First, the received pixel data for one main scan is written into the RAM 13 while shifting in the sub-scan direction in accordance with the timing chart of FIG.
Reference image data is prepared using the data read from the AM 13 and input to the image processing algorithm unit 19. The image processing algorithm unit 19 outputs segmented image data of 19-a to 19-g. Then, the selection is made by switching the select signal 21-b of the multiplexer 21 in accordance with the resolution information from the transmission side, and the selection is transferred to the recording unit to perform recording. As shown in FIG. 7, the segmented image data 21-a of the first line is output in real time before inputting the data of one pixel from 11-a. The multiplexer 21 selects 19-a for the first line of the standard → superfine subdivision, and sequentially selects and records 19-b, 19-c, and 19-d for the second and subsequent lines. Here, considering the recording of the subdivision line, the received data of 19-a to 19-d corresponding to one received pixel must use the same reference image data. During the recording of the modified line, the above-described sub-scanning shift of the image data is not performed. That is, the data stored in the RAM 13 is repeatedly used to output the data of the second to fourth lines.

FIG. 7 is a timing chart at the time of outputting the subdivided image data of the first line.
4 shows a timing chart when outputting four lines of subdivided image data. In this case, since the image already input to the RAM 13 may be used as the reference image, the input serial image data 11-a, the input image transfer clock 23-a, and
The write signal 13-e to the RAM 13 becomes unnecessary.

FIG. 9 is a timing chart summarizing the operations of FIGS. 7 and 8.

As is clear from FIG. 9, the segmented image data of the first line is output as 21-b to 19-a in response to the input of 11-a, and the segmented image data of the second to fourth lines are respectively CP.
19-b, 19- according to the start pulse 23-g from U3
c, 19-d.

That is, the control block 23 may generate each clock for one main scan based on the start pulse 23-g, and output the output serial image data 21-a and the output image transfer clock 23-f. In FIG. 9, "Latch" indicates a data latch to the shift register in the thermal head, and "Record" indicates a strobe signal of the thermal head.

FIG. 10 is a diagram showing the flow of processing when receiving and recording image data. FIG. 10 shows an example in which data received at a standard resolution is recorded in a super fine mode.

Steps indicated by symbols a to d in FIG. 10 correspond to the engines a to d in FIG. 9, and steps denoted by e in FIG. 10 correspond to the timing chart of FIG.

In step S20, when the reception of the image data is started, the RAM
Clear 13 (line buffer consisting of 6 lines).

Referring to FIG. 11, CPU 3 has a buffer clear pulse 23h.
Is output to the control block 23. In the control block 23, the D flip-flop 11 is cleared by the D flip-flop clear pulse 23-j, and the clear signal is sent to the RAM write signal 23e.
To write to RAM13.

By setting the shift register clear pulse 23-k to a high level for one line, a plurality of lines (6
Clear the buffer for line) at the same time. As a result, the clearing time can be greatly reduced as compared with the case where the buffer is cleared by specifying the RAM address line by line.

Next, in step S21, the data 11-a sent from the decoding unit 4 is fetched. At this time, the data on the first line
The address of the memory is controlled so as to be stored in the last line of the RAM 13.

That is, the first and second lines of the input image data are RA
Since the image data is stored in the fifth and sixth lines of M13, the output image data 21-a at this time becomes zero. This is the step
This is because the data of the line before the target pixel (the hatched portion in FIG. 5) is cleared in S20. Therefore, by retaining the previous received data, it is possible to prevent unnecessary dots from appearing. In addition, although the output of the input image data is the data of the subdivided pixels for the target pixel two lines before, the subdivision processing can be performed in real time, and the processing speed can be reduced.

Steps S22 to S24 correspond to the part (a) of FIG. 9 described above, and the input image data 11-a is subjected to real-time segmentation processing. Steps S25 to S27 correspond to the part B in FIG. 9 and perform the subdivision processing of the second line. Similarly, steps S28 to S30 are the third line, and steps S31 to S33 are the fourth line.
A line segmentation process is performed.

As described above, since the subdivision processing is performed in response to the 23-g start pulse from the CPU 3 in the second and subsequent lines, control for that can be simplified and high-speed processing can be performed.

FIG. 12 shows a time chart when a 23-g start pulse is input, and shows the portion B in FIG. 9 in detail. When the control block 23 receives the start pulse 23-g from the CPU 3, it sequentially sends the address signal 23-c to the RAM 13 and sends out the clock 23-d to the shift registers 15 and 17 to sequentially shift the 6 × 9 pixels to obtain the image. The data is transferred to the processing algorithm unit 19. The multiplexer 21 selects one of the data output from the image processing algorithm unit 19 and outputs the output image data 21-a according to the output image transfer clock 23-f. 23-k is input to the shift registers 15 and 17 as a clear pulse for clearing data of 6 × 9 pixels when the subdivision processing of the next line is performed after the subdivision processing of one line is completed. When the subdivision processing of the second, third, and fourth lines is performed by this pulse, since the data of 6 × 9 pixels when the previous line is processed is cleared, it is necessary to prevent the occurrence of nozzles. Can be.

FIG. 13 is a block diagram showing details of the image processing algorithm unit 19 shown in FIG.

Reference numeral 31 denotes an image area separation circuit which determines whether the pixel of interest exists in a character area or a photograph area based on input binary image data of 6 × 9 = 54 pixels. The spatial frequency of the binary data in the 6 × 9 block is
It is performed by three combinations of periodicity and pixel isolation.

For the determination based on the spatial frequency, the number of density inversions is determined for each of the main scanning and sub-scanning directions, and the sum of the number of inversions is compared with a predetermined threshold. Is determined.

The determination based on the periodicity is effective for determining the image area of the image dithered from the transmitting side. In this case, it is assumed that dither processing is performed on the transmitting side by a 4 × 4 dither matrix, and the above-described 6 × 9 = 54 pixels are divided into this 4 × 4 matrix (a part of 4 × 4 pixels). There is also a matrix that only has the same number of pixels), and the number of matching pixels corresponding to a plurality of 4 × 4 matrices is checked. If this number is large, it is determined that the character is a character if the halftone is small.

The determination based on the pixel isolation is effective for determining the image area of an image that has been subjected to halftone processing by the error diffusion method from the transmission side. In this case, it is determined whether or not there is a black pixel adjacent to the upper, lower, left and right of each of the black pixels among the 6 × 9 = 54 pixels. .

If the number of isolated pixels is larger than a predetermined threshold, it is determined as halftone, and if smaller, it is determined as a character.

The image area separation circuit 31 determines the target pixel from halftone or character by taking the majority decision of the three determination results, and sends the identification result to the selectors 35 and 36. The image area separation circuit 31 is composed of a ROM that outputs the result of image area separation using data of 6 × 9 = 54 pixels as an address signal.

The quadruple smoothing circuit 32 subdivides the data of the target pixel four times in the sub-scanning direction, and the quadruple smoothing circuit 33 subdivides the data of the target pixel twice in the sub-scanning direction. Numeral 34 denotes a circuit that outputs the data of the target pixel as it is without performing smoothing.

4 times smoothing circuit 32, 2 times smoothing circuit 33,
The non-smoothing circuit is composed of a ROM that outputs the result of smoothing using data of 54 pixels as addresses.

Reference numerals 35 and 36 are selectors for selecting the data output from the smoothing circuits 32 and 33 or the data output from the non-smoothing circuit 34 according to the result of the image area separation of the image area separation circuit 31.

The selector 35 outputs 4-bit data from the non-smoothing circuit 34 as 19-a to 19-d when the image area of the pixel of interest is identified as halftone by the image area separation circuit 35,
If it is identified as a character, 4-bit data from the quadruple smoothing circuit 32 is output as 19-a to 19-d.

The selector 36 is a circuit without smoothing when the image area of the pixel of interest is identified as a halftone by the image area separation circuit 35.
The 2-bit data from 34 is output as 19-e and 19-f, and if identified as a character, double smoothing circuit
The 2-bit data from 33 is output as 19-e and 19-f.

As described above, in the present embodiment, as a result of the image area separation, a smoothing process of subdividing and interpolating pixels determined as characters as a result is performed, so that it is possible to reproduce a smooth character in which jaggedness of a character portion is prevented. it can. Further, since smoothing is not performed on a halftone image such as a photograph, it is possible to reproduce an image excellent in gradation with little deterioration in image quality.

Also, 19-a output from the image processing algorithm unit 19
To 19-g are sent to the multiplexer 21. The multiplexer 21 selects the selector 35, the selector 36 or the non-smoothing circuit based on the procedure signal sent from the transmission side.
Select and output any one of 34.

FIG. 14 is an example in which a part of the RAM 13 in FIG. 4 is changed, and the RAM 13 is changed to a RAM of which the input / output terminal is a bidirectional type. 32 is a tristate buffer having an output mode in a high impedance state, and 31 is a bidirectional type RAM having input / output terminals.

Then, in the configuration of FIG. 14, the D flip-flop 11
4 is input to the input / output terminal of the RAM 13 only when the memory write pulse is low, whereby the same processing as in FIG. 4 can be performed.

As described above, according to the present embodiment, the received binary data is subdivided based on the resolution information sent from the transmission side, so that the data sent from the transmission side at a low density can be recorded and output at a high density. And high-quality images can be reproduced.

Further, since the smoothing process is performed on pixels determined as characters by performing image area separation of the received binary data, deterioration of the halftone image can be prevented.

Further, according to the above-described embodiment, the function of performing the smoothing processing for each pixel in synchronization with the clock for transferring the received image data, and the processing is started in accordance with the start pulse and the predetermined
By providing a function to stop when the smoothing processing for the main scanning is completed, the interpolation processing (smoothing processing) can be realized by simple control which is almost the same as the conventional apparatus which does not perform the interpolation processing. It becomes possible.

In addition, since the processing speed of conversion into subdivided pixels at the time of smoothing processing is not limited by the clock for transferring received image data, high-speed processing becomes possible.

Further, according to the present embodiment, the writing operation to the memory and the interpolation / subdivision operation are performed simultaneously in synchronization with the clock for transferring the received image data, so that the interpolation / subdivision image processing can be performed at high speed. It becomes possible.

Further, when one line of received data is processed one by one into a plurality of subdivided lines, the same reference data is repeatedly read out from the same image buffer, so that the memory for storing the subdivided line data is provided. This eliminates the need for the apparatus, and can realize a reduction in size and cost of the apparatus, and an operation of storing the segmented line data in the shared memory is not required, so that the apparatus can be speeded up.

Further, according to the present embodiment, after the data read from the image buffer (RAM 13) is shifted by the shift register and then written to the image buffer at the same address, the data to be referred to when performing the subdivision processing can be read in the sub-scanning direction. Therefore, the buffer for storing the reference data can be realized with the minimum necessary, and the size and cost of the device can be reduced.

Also, by clearing the image buffers for a plurality of lines necessary for starting data reception at the same time during one line scanning, the clear operation period can be shortened.

〔The invention's effect〕

As described above, according to the present invention, it is determined whether the received binary image data is a character image or a halftone image, and if the received binary image data is a character image, it is converted to high-resolution data by smoothing processing. Reproduction can be performed, and deterioration of the halftone image can be prevented. Further, according to the present invention, the resolution of the received binary image data is determined based on the procedure signal sent from the partner communication device, and one of a plurality of smoothing processes is selected according to the resolution. Optimum smoothing processing can be performed in accordance with the resolution of an image to record a high-quality character image.

[Brief description of the drawings]

FIG. 1 is a block diagram of a facsimile apparatus according to an embodiment of the present invention, FIG. 2 is a view showing a procedure signal exchanged between a facsimile apparatus on a transmitting side and a receiving side, and FIG. 4 is a block diagram showing details of the image processing unit 1 shown in FIG. 1, FIG. 5 is a diagram showing a state of subdivision when performing subdivision and interpolation processing, FIG. 6 is a diagram showing an example of a reference pixel area when performing interpolation, FIG. 6 is a diagram showing an output example when subdivision and interpolation are performed, and FIG. 7 is an image synchronized with a clock for input image transfer. FIG. 8 and FIG. 12 are timing charts when the image processing block operates according to a start pulse, and FIG. 9 is four subdivisions of the received image data. Perform pixel processing and record FIG. 10 is a diagram showing a flow of processing when image data is received and recorded, and FIG. 11 is a timing of an operation for clearing a memory in response to a buffer clear start pulse. FIG. 13 is a block diagram showing details of the image processing algorithm unit 19 in FIG. 4, and FIG. 14 is a block diagram when FIG. 4 is partially modified. In the figure, 1 is an image processing unit, 2 is a modem, 3 is a CPU, 4 is a reception data decoding unit, 5 is a recording unit, 7 is a facsimile transmitter, 11 is a D flip-flop, 13 is RAM, and 15 and 17 are shift registers. , 19 is an image processing algorithm section, 21 is a multiplexer, 23 is a control block, 31 is an image area separation circuit, 32
Is a 4 times smoothing circuit, 33 is a 2 times smoothing circuit,
34 is a circuit without smoothing, and 35 and 36 are selectors.

Continuation of the front page (72) Inventor Yasuhide Ueno 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (56) References JP-A-62-277855 (JP, A) JP-A-54-51731 ( JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) H04N 1/387-1/393 H04N 1/40

Claims (1)

(57) [Claims] A first resolution transmitted from a partner communication apparatus or a second resolution of a second resolution higher than the first resolution.
Receiving means for receiving the value image data; and determining whether the resolution of the binary image data received by the receiving means is the first or second resolution based on a procedure signal sent from the partner communication device. Discriminating means; identifying means for identifying whether the received binary image data is a character image or a halftone image from the binary image data received by the receiving means; Recording means for recording an image at a third resolution higher than the first and second resolutions; and smoothing processing of the first resolution binary image data received by the receiving means, the data having a third resolution. First smoothing processing means for converting the binary image data of the second resolution received by the receiving means into data of a third resolution. A second smoothing processing unit for converting the received binary image data into a character image, wherein the identification unit identifies the received binary image data as a character image, and the determination unit converts the received binary image data into a first resolution data. If it is determined that the received binary image data is a character image, the identification unit identifies the received binary image data as a character image, and the determination unit determines that the received binary image data is a character image. A facsimile apparatus for recording an image based on the data smoothed by the second smoothing processing means when the image data is determined to be data of the second resolution;