JP2835266B2 - Programmable logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable logic circuit, and more particularly to a field programmable gate array (Field Programmable Gate Array).
The present invention relates to a programmable logic circuit called “Gate Array (FPGA)”.

2. Description of the Related Art Conventionally, there has been known a semiconductor integrated circuit having a function of realizing a target logic circuit by connecting a plurality of logic cells with a plurality of programmable signal lines. A method of determining a signal propagation path in a logic circuit and a method of programming a function realized by a logic cell can be generally classified into the following two methods.

According to a first programming method, a static random access memory (Static Random Access Memory) is used.
Random Access Memory: SRA
By controlling the on / off state of the switches in the signal propagation path based on the data stored in the memory cell of M), the signal propagation path and the function realized by the logic cell are decided. In this case, since the configuration of the logic circuit to be realized is determined by the data stored in the memory cells of the SRAM, programming can be performed a plurality of times.

On the other hand, according to the second programming method, the conduction state of the fuse in the signal propagation path is controlled to determine the signal propagation path and the function realized by the logic cell. In this case, since the configuration of the logic circuit to be realized is determined by the conduction state of the fuse, programming cannot be performed a plurality of times.

[0005]

2. Description of the Related Art When the basic structure of a logic cell is classified, it can be roughly classified into the following three types. A memory look-up table type logic cell is a cell that realizes an arbitrary logic by setting an input as a memory address and an output as a memory content indicated by the address. An AND-OR plane type logic cell is a cell that realizes an arbitrary logic by programming one or both of the built-in AND plane and AND plane. Further, the logic cell of the logic selection type is a cell that realizes an arbitrary logic by controlling a signal propagation path using a selection circuit such as a multiplexer that can select an output.

[0006]

However, in a memory cell of a memory look-up table type, the number of memory cells for holding an output value increases exponentially with an increase in the number of input signal lines. Resulting in. Therefore, when the number of input signals of the logic circuit increases, the required memory capacity increases, and there is a problem that it is difficult to realize such a logic circuit with a memory look-up table type logic cell.

Further, the AND-or-plane type logic cell has a problem that it is difficult to form a large-scale sequential logic circuit due to the structure using the AND-OR plane.

Further, the logic cell of the logic selection type has a problem that when the number of input signals of the logic circuit increases, the circuit scale of the selection circuit in the logic cell increases. In general, it is known that the circuit scale of the selection circuit increases exponentially with an increase in the number of input signals.

In all of the above logic cells, when the logic of the circuit portion, which is a component, is inverted from positive logic to negative logic in order to change the configuration of the logic circuit, the circuit scale may be significantly changed. Was. For this reason, when the design specification of the logic circuit is changed, there is a possibility that the logic circuit cannot be mapped. In other words, in order to reduce the circuit scale of a logic cell, according to a certain logic cell, an AND-OR type logic circuit is easy to configure, but an OR-AND type logic circuit is difficult to configure, or vice versa. There was also a problem that would.

On the other hand, most of the conventional logic cells are generally constituted by partial circuits as shown in FIG. That is,
The logic cell 100 includes a partial circuit 101 for forming a combinational logic circuit and a partial circuit 102 for forming a sequential logic circuit. When forming a combinational logic circuit, the partial circuit 101 of the logic cell 100 is used.
Is used. Therefore, when a logic circuit including many combinational logic circuits is mapped using the logic cell 100 shown in FIG. 47, the partial circuit 102 not used in this logic circuit is mapped.
Will increase. When a logic circuit including many sequential logic circuits is mapped using the logic cell 100 shown in FIG. 47, the number of partial circuits 101 not used for this logic circuit increases. Therefore, the utilization efficiency of the partial circuit 101 or 102 in the logic cell 100 is significantly reduced due to the configuration of the logic circuit to be mapped and the ratio between the combinational logic circuit portion and the sequential logic circuit portion in the logic circuit. There was a problem.

When configuring a logic circuit, it is necessary to configure a logic cell so as to realize both combinational logic and sequential logic, unless it is known in advance that only one of combinational logic and sequential logic is used. is there. But,
Since a normal logic circuit uses a combination of both combinational logic and sequential logic, as shown in FIG.
It was necessary to provide both the partial circuit 101 and the partial circuit 102 in 00.

As a result, in the conventional logic cell, there is a problem that the use efficiency of each partial circuit in the logic cell, that is, the use efficiency of the logic cell cannot be improved regardless of the configuration of the logic circuit to be mapped. .

[0013]

FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, a logic cell 1 has a partial circuit 2 for forming a combinational logic circuit and a switch circuit 3. The logic cell 1 is not provided with a dedicated partial circuit for forming a sequential logic circuit. Switch circuit 3
Selectively returns the output of the partial circuit 2 to the input of the partial circuit 2. An inversion function may be provided in one or both of the input unit and the output unit of the partial circuit 2.

The programmable logic circuit according to the present invention comprises:
It comprises a plurality of logic cells 1.

[0015]

When the switch circuit 3 of the logic cell 1 does not feed back the output of the partial circuit 2 to the input of the partial circuit 2,
Thus, a combinational logic circuit can be realized. Also, logic cell 1
When the switch circuit 3 returns the output of the partial circuit 2 to the input of the partial circuit 2, the logic cell 1 can realize a sequential logic circuit. Thus, an arbitrary logic can be realized by connecting one logic cell 1 or a plurality of logic cells 1.

Therefore, regardless of the configuration of the logic circuit to be mapped, the utilization efficiency of the partial circuit 2 in each logic cell 1, that is, the utilization efficiency of the logic cell 1 can be improved.
When one or both of the input section and the output section of the partial circuit 2 are provided with an inverting function, the inverter circuit which exists alone as a component of the programmable logic circuit is omitted, and the utilization efficiency of the logic cell 1 is further improved. As a result, the degree of integration of the programmable logic circuit can be improved.

[0017]

First, a first embodiment of the programmable logic circuit according to the present invention will be described with reference to FIG. FIG. 2 shows a configuration of a logic cell 1 which is a main part of the present embodiment. Logic cell 1
It comprises an input / output path B, basic logic circuits C1 and C2, inverting circuits C3 to C6, and a switch circuit C7. The input / output path B corresponds to the input and output of the logic cell 1 in FIG. The basic logic circuits C1 and C2 each include a logic cell 1
Is a logic circuit that constitutes the basic part. Inverting circuit C3 ~
C6 has a function of selectively inverting a part or all of the logic of each input signal. The inverting circuits C5 and C3 are respectively connected to the input side and the output side of the basic logic circuit C1. The inverting circuits C6 and C4 are respectively connected to the input side and the output side of the basic logic circuit C2. The basic logic circuits C1 and C2 and the inversion circuits C3 to C6
Corresponds to the partial circuit 2. Switch circuit C7
Is composed of a plurality of switches, and has a function of selectively changing the connection with the outside of the logic cell 1 and the internal connection of the logic cell 1. By selectively changing the internal connection of the logic cell 1, the switch circuit C7 controls a part or all of the outputs of the basic logic circuits C1 and C2 via the inverting circuits C3 and C4 to the basics via the inverting circuits C5 and C6. Feedback can be made to the inputs of the logic circuits C1 and C2. The switch circuit C7 corresponds to the switch circuit 3 in FIG.

The logic cell 1 functions as a normal combinational logic circuit unless the switch circuit C7 selectively connects the output signal line of the input / output path B and the input signal line of the input / output path B. On the other hand, when the output signal line of the input / output path B and the input signal line of the input / output path B are selectively connected by programming the switch of the switch circuit C7,
In FIG. 2, a signal propagation path C7 → C5 → C1 → C3 → C7 and a signal propagation path C7 → C6 → C2 → C4 → C7 are formed, and the logic cell 1 functions as a sequential logic circuit. That is, the logic cell 1 can function as a combinational logic circuit or a sequential logic circuit in accordance with the programming of the switch circuit C7.

In an actual programmable logic circuit, a plurality of such logic cells 1 are provided. Further, the number of basic logic circuits is not limited to two. Further, a part of the inverting circuit may be omitted or omitted.

FIG. 3 shows a first embodiment of the internal configuration of the logic cell 1 shown in FIG. 3, a sub-block 11 includes a basic logic circuit C1 and inverting circuits C3 and C5, and corresponds to the partial circuit 2 in FIG. Sub-block 1
2 comprises a basic logic circuit C2 and inverting circuits C4 and C6, and corresponds to the partial circuit 2 in FIG. The basic logic circuit C1 includes AND circuits 11a,
11b and an OR circuit 11c. The basic logic circuit C2 includes AND circuits 12a and 12a connected as shown.
b and an OR circuit 12c. In this embodiment, the inverting circuits C5 and C6 each comprise five programmable (programmable) inverters. On the other hand, inverting circuits C3 and C
4 comprises one programmable inverter each.

In this embodiment, the input / output path B includes two output signal lines B1 and B2 and seven input signal lines B3 to B9.
It consists of a total of nine signal lines B1 to B9. Sub-block 1
Outputs 1 and 12 are connected to output signal lines B1 and B2. The switch circuit C7 includes a plurality of programmable switches SW indicated by “circles” in FIG. One or a plurality of switches SW are provided for each of the signal lines B1 to B9. For example, when three switches provided for the input signal line B3 are turned on, a signal from the input signal line B3 is supplied to one inverter of the inverter circuit C5 and two inverters of the inverter circuit C6. Then, the input signal line B3
If the inverters of the inverting circuits C5 and C6 to which the signal is supplied are programmed to invert the logic of the signal, the signal from the input signal line B3 has its logic inverted and then the corresponding basic logic circuit C1 , C2. On the other hand, for example, when three switches SW provided for the output signal line B2 are turned on, a signal from the output signal line B2 is fed back to two inverters of the inversion circuit C5 and one inverter of the inversion circuit C6. . And the output signal line B
If the inverters of the inverting circuits C5 and C6 supplied with the signal from the second circuit 2 are programmed to invert the logic of the signal, the signal from the output signal line B2 has its logic inverted and then the corresponding basic logic circuit It is supplied to C1 and C2. As described above, when at least one of the switches SW provided for the output signal lines B1 and B2 is turned on, the logic cells 1 can sequentially function as a logic circuit. When all the switches SW provided for the output signal lines B1 and B2 are turned off, the logic cells 1 can be combined to function as a logic circuit.

FIG. 4 shows a second embodiment of the internal configuration of the logic cell 1 shown in FIG. 4, the same parts as those of FIG. 3 are denoted by the same reference numerals, and the description thereof will be omitted. In FIG. 3, the basic logic circuits C1 and C2 are respectively constituted by AND-OR circuits, but in FIG. 4, the basic logic circuits C1 and C2 are respectively constituted by AND-circuits.
It is composed of a NOR circuit. That is, the basic logic circuit C
Reference numeral 1 denotes AND circuits 11a and 11b connected as shown.
And a NOR circuit 11d. Also, the basic logic circuit C2
Is composed of AND circuits 12a and 12b and a NOR circuit 12d connected as shown.

FIG. 5 shows a third embodiment of the internal configuration of the logic cell 1 shown in FIG. 5, the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 3, the basic logic circuits C1 and C2 are each configured by an AND-OR circuit, but in FIG. 5, the basic logic circuits C1 and C2 are each configured by an OR-AND circuit. That is, the basic logic circuit C
1 comprises OR circuits 11e and 11f and an AND circuit 11c connected as shown. Also, the basic logic circuit C2
Is composed of NOR circuits 12e and 12f and an AND circuit 12c connected as shown.

FIG. 6 shows a fourth embodiment of the internal configuration of the logic cell 1 shown in FIG. 6, the same parts as those in FIGS. 3 and 5 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 3, the basic logic circuits C1 and C2 are each configured by an AND-OR circuit, but in FIG. 6, the basic logic circuits C1 and C2 are each configured by an OR-AND circuit. That is, the basic logic circuit C1 is connected to the OR circuit 11e,
11f and a NAND circuit 11g. The basic logic circuit C2 includes NOR circuits 12e and 12e connected as shown.
f and a NAND circuit 12g.

FIG. 7 shows a fifth embodiment of the internal configuration of the logic cell 1 shown in FIG. 7, the same parts as those in FIG. 3 are denoted by the same reference numerals, and the description thereof will be omitted. In FIG. 3, the basic logic circuits C1 and C2 are each constituted by an AND-OR circuit, but in FIG. 7, the basic logic circuits C1 and C2 are each constituted by a NAND circuit.
It is composed of an AND circuit. In other words, the basic logic circuit C1 is connected to the NAND circuits 11h and 11h connected as shown.
i and an AND circuit 11c. Also, the basic logic circuit C
2 are NAND circuits 12h and 12i connected as shown.
And an AND circuit 12c.

FIG. 8 shows a sixth embodiment of the internal configuration of the logic cell 1 shown in FIG. 8, the same parts as those in FIGS. 6 and 7 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 7, each of the basic logic circuits C1 and C2 is constituted by a NAND-and circuit, whereas in FIG. 8, each of the basic logic circuits C1 and C2 is constituted by a NAND-and circuit. That is, the basic logic circuit C1 is connected to the NAND circuit 1 connected as shown.
1h, 11i and a NAND circuit 11g. The basic logic circuit C2 is connected to a NAND circuit 12 connected as shown.
h, 12i and a NAND circuit 12g.

FIG. 9 shows a seventh embodiment of the internal configuration of the logic cell 1 shown in FIG. In FIG. 9, the same parts as those in FIG. In FIG. 3, the basic logic circuits C1 and C2 are each configured by an AND-OR circuit, but in FIG. 9, the basic logic circuits C1 and C2 are each configured by a NOR-OR circuit. That is, the basic logic circuit C1
Is composed of NOR circuits 11j and 11k and an OR circuit 111 connected as shown. The basic logic circuit C2 includes NOR circuits 12j and 12k and an OR circuit 12l connected as shown.

FIG. 10 shows an eighth embodiment of the internal configuration of the logic cell 1 shown in FIG. 10, the same parts as those in FIGS. 4 and 9 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 9, the basic logic circuits C1 and C2 are each configured by a NOR-OR circuit, whereas in FIG. 10, the basic logic circuits C1 and C2 are each configured by a NOR-NOR circuit. That is, the basic logic circuit C1 is connected to the NOR circuit 11 connected as shown.
j, 11k and a NOR circuit 11d. The basic logic circuit C2 is connected to the NOR circuits 12j, 1 connected as shown.
2k and a NOR circuit 12d.

As described above, according to the present embodiment, the on / off state of the programmable switch of the switch circuit C7 in the logic cell 1 and the inversion state of the inversion circuits C3 to C6 are arbitrarily controlled, whereby the logic cell 1 is controlled. Thus, a sequential logic circuit such as a flip-flop circuit shown in FIG. 11 can be realized.
In the figure, (a) is a set / reset (SR) flip-flop, (b) is a JK (JK) flip-flop, and (c) is an SR flip-flop having a preset terminal and a reset terminal. , (D) and (e) show a delay (D) flip-flop having a preset terminal and a reset terminal, respectively.

As is apparent from the above description, each of the basic logic circuits C1 and C2 is configured by combining two or more circuits of an AND circuit, a NAND circuit, an OR circuit, and a NOR circuit. In addition, the circuits that can be selected to configure each basic logic circuit are the same as the logic of the input signal of the basic logic circuit, or
In any of the inverted cases, the resulting reduced circuit is an AND-OR circuit, an OR-AND circuit,
It constitutes a NOR circuit and an OR-Nand circuit.
This can be proved from the following lemmas 1 and 2.

(Lemma 1) A circuit which can be selected to constitute a basic logic circuit is a circuit obtained by simplifying the logic of an input signal of the basic logic circuit as it is or inverting it. It constitutes an OR circuit, an OR-and circuit, an AND-NOR circuit, and an OR-Nand circuit.

(Proof 1) “A circuit that can be selected to constitute a basic logic circuit is a circuit obtained by simplifying the logic of the input signal of the basic logic circuit, either as it is or when the logic is inverted. -OR circuit, OR-AND circuit, AND-NOR circuit, and OR-NAND circuit ", assuming that the circuits constituting the basic logic circuit are simplified. Circuit, OR circuit and NOR circuit, one-stage multi-input-
It becomes a one-output combinational logic circuit. Accordingly, exclusive (exclusive) OR or exclusive NOR cannot be expressed by one logic cell. Thereby, "the circuit that can be selected to configure the basic logic circuit, in either case where the logic of the input signal of the basic logic circuit is intact or inverted, the circuit resulting from the simplification is an AND-OR circuit, An OR-AND circuit, an AND-NOR circuit, and an OR-Nand circuit. "

(Lemma 2) A circuit that can be selected to constitute a basic logic circuit is a circuit obtained by simplifying the logic of an input signal of the basic logic circuit as it is or inverting the logic of the input signal. When forming an OR circuit, an OR-and circuit, an AND-NOR circuit, and an OR-Nand circuit, all the sequential logic circuits shown in FIG. 11 can be formed.

(Proof 2) When the simplified circuit constitutes an AND-OR circuit, an OR-AND circuit, an AND-NOR circuit, and an OR-NAND circuit, the logic of the input signal of the basic logic circuit is changed. The logic circuits that are all inverted are (1) NOR-OR circuit, (2) NOR-NO circuit, (3)
Either a NAND-AND circuit or (4) a NAND-NAND circuit. In the cases (1) and (3), the logic of the output signal of the basic logic circuit is also inverted. Therefore, "the circuits that can be selected to configure the basic logic circuit are either the inversion of the logic of the input signal of the basic logic circuit or the inversion of the logic of the input signal of the basic logic circuit. -AND circuit, AND-NOR circuit and OR circuit
If a NAND circuit is formed, all the sequential logic circuits shown in FIG. 11 can be formed. "
Needless to say, in FIG. 11, the NAND circuit may be replaced with a NOR circuit.

Next, the connection between the programmable switch SW of the switch circuit C7 and the signal lines B1 to B9 of the input / output path B will be described with reference to FIG.

As shown enlarged on the right side of FIG. 12, the switch SW is connected to one signal line of the input / output path B and one signal line connected to the sub-block C1 or C2. It is turned on / off by a control signal CNT supplied to the control terminal. In the illustrated example, the switch SW is connected to the input signal line B5 and the signal line L connected to the sub-block C2.

FIG. 13 shows an embodiment of the inverting circuit C3. The inversion circuit C3 includes an inverter 23 connected as shown, and switches 24 and 25. Input terminal 21
Is supplied to the switch 24 via the inverter 23 on the one hand and directly to the switch 25 on the other hand. A control signal is applied to the control terminal 22 to determine whether the inverting circuit C3 outputs the input signal as it is or outputs it after inverting it. The control signal from the control terminal 22 is supplied to the control terminal of the switch 24 as it is, and is supplied to the control terminal of the switch 25 after being inverted. The outputs of switches 24 and 25 are both output terminal 2
6 is connected. Thereby, for example, the control terminal 22
When a low-level control signal is applied to the input terminal 21, the signal applied to the input terminal 21 is inverted and output from the output terminal 26, and when a high-level control signal is applied to the control terminal 22, the signal is applied to the input terminal 21. Output terminal 2
6 is output.

The same configuration as that of FIG. 13 can be used for the inverting circuit C4. Further, since each of the inverting circuits C5 and C6 has five input signals, for example, five circuits having the configuration shown in FIG. 13 may be provided.

Next, the connection between the logic cells 1 will be described with reference to FIG. FIG. 14 shows an embodiment of the connection between the inter-cell path 30 which is a set of signal lines connecting the logic cells 1 and the switch circuit C7. 3, the same parts as those of FIG. 3 are denoted by the same reference numerals, and the description thereof will be omitted.

In FIG. 14, each programmable switch SW of the switch circuit C7 is connected to the signal lines B1 to B1 of the input / output path B.
One of the signal lines B8 is connected to one of the signal lines BB1 to BB10 of the inter-cell path 30. In the present embodiment, the signal lines BB9, BB10
Are used to transfer clock signals. A switch group 31 is provided for the output lines B1 and B2 of the input / output path B. The switch SW of the switch group 31 is connected to each signal line B
B1 to BB10, the output signal lines B1 and B2 of the logic cell 1 and the signal line B of the inter-cell path 30
B1 to BB8 can be freely connected. A switch group 32 is provided for the signal lines B2 to B8 of the input / output path B. Since the switches SW of the switch group 32 are provided only for predetermined signal lines among the signal lines BB1 to BB8, the switches SW of the input lines B3 to B8 of the logic cell 1 and the signal lines BB1 to BB8 of the inter-cell path 30 are provided. Among them, it can be connected to a predetermined signal line. Further, a switch group 33 is provided for the input signal line B3 of the input / output path B. Therefore, the input signal line B3 of the input / output path B and the signal lines BB9 and BB10 of the inter-cell path 30 can be connected via the switch SW of the switch group 33.

The signal lines B1 to B8 and the signal lines BB
Needless to say, one switch SW may be provided for 1 to BB10.

FIGS. 15 to 17 show second to fourth embodiments of a programmable logic circuit which can form a sequential logic circuit by using a plurality of the above sub-blocks 11, respectively.

The second embodiment of the programmable logic circuit shown in FIG. 15 comprises four sub-blocks 11-1 to 11-4 and a switch SW connected as shown. This programmable logic circuit functions as a combinational logic circuit or a sequential logic circuit such as a flip-flop depending on the on / off state of each switch SW. In this embodiment, the programmable logic circuit has four input terminals P1 to P1.
P4 and two output terminals P15 and P16 are provided. The switch SW is connected to the input terminal P2 and the sub-block 1
1-1, the input terminal P5, the input terminal P3 and the input terminal P6 of the sub-block 11-1, the input terminal P3 and the input terminal P7 of the sub-block 11-3, the input terminal P
2 and the input terminal P8 of the sub-block 11-3, between the output terminal P15 and the input terminal P12 of the sub-block 11-4, and between the output terminal P16 and the input terminal P11 of the sub-block 11-2. Is provided. Also, input terminal P
1 is connected to the input terminal P9 of the sub-block 11-2,
The input terminal P4 is the input terminal P14 of the sub-block 11-4.
It is connected to the. Further, the output terminal P17 of the sub-block 11-1 is connected to the input terminal P10 of the sub-block 11-2, and the output terminal P1 of the sub-block 11-3.
8 is connected to the input terminal P13 of the sub-block 11-4. Note that each pair of switches SW connected by broken lines is
They are linked and turned on / off at the same time.

The third embodiment of the programmable logic circuit shown in FIG. 16 comprises four sub-blocks 11-1 to 11-4 connected as shown and a switch SW. This programmable logic circuit functions as a combinational logic circuit or a sequential logic circuit such as a flip-flop depending on the on / off state of each switch SW. 15, the same components as those in FIG. 15 are denoted by the same reference numerals, and the description thereof will be omitted.

In this embodiment, six input terminals P1, P2
A, P2B, P3, P4 and P21 are provided.
The switch SW is further connected between the input terminal P2A and the input terminal P5 of the sub-block 11-1, between the input terminal P2B and the input terminal P8 of the sub-block 11-3, and the input terminal P
21 and the input terminal P6 of the sub-block 11-1, between the input terminal P21 and the input terminal P7 of the sub-block 11-3, the input terminal P6 of the sub-block 11-1 and the input terminal of the sub-block 11-2. P11 and between the input terminal P7 of the sub-block 11-3 and the input terminal P12 of the sub-block 11-4. The switches SW connected by broken lines are linked and turned on / off at the same time.

The fourth embodiment of the programmable logic circuit shown in FIG. 17 comprises four sub-blocks 11-5 to 11-10 connected as shown, and a switch SW. This programmable logic circuit is configured to turn on / off each switch SW.
Depending on the off state, the circuit functions as a combinational logic circuit or a sequential logic circuit such as a flip-flop. In this embodiment, the programmable logic circuit has six input terminals P3
0 to P35 and two output terminals P59 and P60. The switch SW is connected between the input terminal P30 and the input terminal P58 of the sub-block 11-9, the input terminal P3.
0 and the input terminal P45 of the sub-block 11-7, the input terminal P30 and the input terminal P46 of the sub-block 11-8.
Between the input terminal P31 and the input terminal P41 of the sub-block 11-5, between the input terminal P31 and the sub-block 11-5.
-6 between the input terminal P42, the input terminal P31 and the input terminal P59 of the sub-block 11-10,
31 and the input terminal P45 of the sub-block 11-7,
The input terminal P32 and the input terminal P4 of the sub-block 11-5
0, between the input terminal P32 and the input terminal P59 of the sub-block 11-10, between the input terminal P33 and the input terminal P42 of the sub-block 11-6, and between the input terminal P33 and the input of the sub-block 11-7. Between the terminal P44, between the input terminal P33 and the input terminal P47 of the sub-block 11-8, between the input terminal P34 and the input terminal P40 of the sub-block 11-5, and between the input terminal P34 and the sub-block 11-6.
, Between the input terminal P34 and the input terminal P47 of the sub-block 11-8, between the input terminal P35 and the input terminal P41 of the sub-block 11-5, and between the input terminal P35 and the sub-block 11-. 9 between the input terminal P58, the input terminal P35 and the input terminal P46 of the sub-block 11-8, and the output terminal P56 of the sub-block 11-9.
And the input terminal P43 of the sub-block 11-6, the output terminal P56 of the sub-block 11-9 and the sub-block 11
-7, the input terminal P45 of the sub-block 11-9 and the input terminal P4 of the sub-block 11-8.
6, between the output terminal P57 of the sub-block 11-10 and the input terminal P41 of the sub-block 11-5, and between the output terminal P57 of the sub-block 11-10 and the sub-block 11
-6 between the input terminal P42 and the sub-block 11-
It is provided between the ten output terminals P57 and the input terminal P45 of the sub-block 11-7.

The output terminal P48 of the sub-block 11-5 is connected to the input terminal P52 of the sub-block 11-9, and the output terminal P49 of the sub-block 11-6 is connected to the sub-block 1
1-9 is connected to the input terminal P53. The output terminal P50 of the sub-block 11-7 is connected to the sub-block 11-10.
The output terminal P51 of the sub-block 11-8 is connected to the input terminal P54 of the sub-block 11-10.
55. The output terminal P56 of the sub-block 11-9 is connected to the output terminal P59 of the programmable logic circuit, and the output terminal P57 of the sub-block 11-10 is connected to the output terminal P60 of the programmable logic circuit.

In this embodiment, by appropriately controlling the ON / OFF state of each switch SW, an RS flip-flop, a clocked RS (RS-CK) flip-flop, a D flip-flop, and a JK At least one kind of sequential logic circuit among flip-flops can be realized, and at least one kind of combinational logic circuit among AND, NAND, OR, NOR, exclusive OR, exclusive NOR, and half adder can be realized.

Next, a description will be given of a fifth embodiment of the programmable logic circuit according to the present invention, by referring to FIG. FIG. 18 shows a configuration of a logic cell 31 which is a main part of the present embodiment. The logic cell 31 includes an input / output path B and basic logic circuits C11 and C1.
2, C21 and C22, inverting circuits C5 and C6, and a switch circuit C7. The input / output path B corresponds to the input and output of the logic cell 1 in FIG. Each of the basic logic circuits C11, C12, C21, and C22 has a logic cell 3
1 is a logic circuit that constitutes the basic part. Inverting circuit C
5 and C6 have a function of selectively inverting the logic of a part or all of the input signals. Inverting circuit C5
Is connected to the input side of the basic logic circuit C11. The outputs of the basic logic circuits C11 and C21 are input to the corresponding basic logic circuits C12 and C22, respectively, and are also fed back to the inputs of the basic logic circuits C11 and C21. The outputs of the basic logic circuits C12 and C22 are input to the switch circuit C7 and are also fed back to the inputs of the basic logic circuits C12 and C22. Further, the outputs of the basic logic circuits C12 and C22 are input to the basic logic circuits C21 and C11, respectively.
On the other hand, the inversion circuit C6 is connected to the input side of the basic logic circuit C21. Basic logic circuits C11, C12, C2
1 and C22 and the inverting circuits C5 and C6 correspond to the partial circuit 2 in FIG.

The switch circuit C7 includes a plurality of switches and has a function of selectively changing the connection between the logic cell 31 and the outside and the internal connection of the logic cell 31. Logic cell 31
, The switch circuit C7 switches part or all of the outputs of the basic logic circuits C11 and C21 via the basic logic circuits C12 and C22 to the inverting circuit C2.
5 and C6, it is possible to feed back to the inputs of the basic logic circuits C11 and C21. The switch circuit C7 corresponds to the switch circuit 3 in FIG.

The logic cell 31 functions as a normal combinational logic circuit unless the switch circuit C7 selectively connects the output signal line of the input / output path B and the input signal line of the input / output path B. On the other hand, if the output signal line of the input / output path B and the input signal line of the input / output path B are selectively connected by programming the switch of the switch circuit C7, for example, the signal propagation path C7 → C5 in FIG. → C11
→ C12 → C7 and signal propagation path C7 → C6 → C21 →
C22 → C7 is formed, and the logic cell 31 functions as a sequential logic circuit. That is, the logic cell 31 can function as a combinational logic circuit or a sequential logic circuit in accordance with the programming of the switch circuit C7.

In an actual programmable logic circuit, a plurality of such logic cells 31 are provided. Further, the number of basic logic circuits is not limited to four. Furthermore,
A part of the inverting circuit may be omitted.

FIG. 19 shows an embodiment of the configuration of the logic cell 31 shown in FIG. In FIG. 19, a sub-block 41 includes basic logic circuits C11 and C12 and an inversion circuit C5.
This corresponds to the partial circuit 2 in FIG. The sub-block 42 includes basic logic circuits C21 and C22 and an inversion circuit C.
6 and corresponds to the partial circuit 2 in FIG.
The basic logic circuit C11 includes OR circuits 41a and 41b, an AND circuit 41c, and an inverter circuit 41d connected as shown. The basic logic circuit C12 includes NAND circuits 41e and 41f and a switch circuit 41g connected as shown. In this embodiment, the switch circuit 41g is regarded as a part of the basic logic circuit C12 for convenience, but the switch circuit 41g may be regarded as a part of the basic logic circuit C11, for example. Similarly, the basic logic circuit C21 includes OR circuits 42a and 42 connected as shown.
b, an AND circuit 42c, and an inverter circuit 42d. The basic logic circuit C22 includes NAND circuits 42e and 42f and a switch circuit 42g connected as shown.
Consists of In this embodiment, the switch circuit 42g is regarded as a part of the basic logic circuit C22 for convenience, but the switch circuit 42g may be regarded as a part of the basic logic circuit C21, for example. Each of the switch circuits 41g and 42g includes two switch elements and one inverter.

Each of the inverting circuits C5 and C6 comprises a programmable (programmable) inverter. As the configuration of the programmable inverter, the configuration described with reference to FIG. 13 can be used. The inverting circuit may be provided on the input side and / or the output side of any sub-block, and may be provided only for any signal line of the sub-block.

In this embodiment, the input / output path B is composed of two output signal lines and fourteen input signal lines, that is, a total of 16 signal lines. Outputs of the sub-blocks 41 and 42 are connected to output signal lines of the input / output path B. Switch circuit C7
Consists of a local signal distributor 44 and a global signal distributor 45. The local signal distributor 44 and the global signal distributor 45 each include a plurality of programmable switches SW indicated by “circles” in FIG. Within the local signal distributor 44,
One or a plurality of switches SW are provided for each signal line of the input / output path B. In the global signal distributor 45, a plurality of switches SW are provided for specific input signal lines of the input / output path B (two input signal lines in this embodiment).

The local signal distributor 44
Are provided for the local signal lines S1 to S9, and are provided for exchanging signals with neighboring logic cells. That is, the local signal distributor 44 is used for selecting a signal to be applied to the sub blocks 41 and 42. The switch SW in the local signal distributor 44 is connected to each of the sub-blocks 41 and 4.
2 are arranged so that a combinational logic circuit frequently used in design can be easily realized.

Global signal distributor 4
5 are provided for the global signal lines φ1 to φ4, and the global signal lines φ1 to φ4 are
1, 42 are provided. The switch SW in the global signal distributor 45 is
A specific input signal line of the input / output path B and each of the global signal lines φ1 to φ4 are arranged so as to be connectable. Of course, the switches SW in the global signal distributor 45 may be provided only for arbitrary global signal lines φ1 to φ4.

Each of the basic logic circuits C11, C12, C21,
C22 switches its own output to its input
Has a path that can be returned via the. Therefore, the switch S
By turning on W, each of the basic logic circuits C11, C1
2, C21 and C22 can function as sequential logic circuits. Therefore, both the sub-block 41 including the basic logic circuits C11 and C12 and the sub-block 42 including the basic logic circuits C21 and C22 can function as sequential logic circuits. In addition, the basic logic circuits C11 and C12 in the sub-blocks 41 and 42 and the basic logic circuits C21 and C
22 as a sequential logic circuit, and each basic logic circuit C
By applying reference signals having different phases to 11, C12, C21, and C22, a master-slave type sequential logic circuit can be configured.

In this embodiment, each sub-block is composed of two basic logic circuits. However, a configuration composed of one basic logic circuit as in the first embodiment may be composed of three or more basic logic circuits. It is good also as composition.

As is clear from the above description, the basic logic circuits C11, C12, C21 and C22 are respectively AND circuits,
It is configured by combining two or more circuits among a NAND circuit, an OR circuit, and a NOR circuit. The circuits that can be selected to configure each basic logic circuit include, in either the case where the logic of the input signal of the basic logic circuit is intact or the case where the logic is inverted, the circuit resulting from the simplification is an AND-OR circuit or an OR circuit. −
It constitutes an AND circuit, an AND-NOR circuit and an OR-Nand circuit. This can be proved from the following lemmas 3 and 4.

(Lemma 3) A circuit which can be selected to constitute a basic logic circuit is a circuit obtained by simplifying the logic of an input signal of the basic logic circuit as it is, or inverting the logic of the input signal. It constitutes an OR circuit, an OR-and circuit, an AND-NOR circuit, and an OR-Nand circuit.

(Certification 3) “A circuit that can be selected to constitute a basic logic circuit is a circuit obtained by simplifying the logic of an input signal of the basic logic circuit either as it is or when the logic is inverted. -OR circuit, OR-AND circuit, AND-NOR circuit, and OR-NAND circuit ", assuming that the circuits constituting the basic logic circuit are simplified. Circuit, OR circuit and NOR circuit, one-stage multi-input-
It becomes a one-output combinational logic circuit. Therefore, exclusive OR or exclusive NOR cannot be expressed by one logic cell. Thereby, "the circuit that can be selected to configure the basic logic circuit, in either case where the logic of the input signal of the basic logic circuit is intact or inverted, the circuit resulting from the simplification is an AND-OR circuit, OR-AND CIRCUIT, AND-NOOR CIRCUIT, AND OR
A NAND circuit. "

(Lemma 4) A circuit that can be selected to form a basic logic circuit is a circuit obtained by simplifying the logic of an input signal of the basic logic circuit either as it is or when the logic is inverted. When forming an OR circuit, an OR-and circuit, an AND-NOR circuit, and an OR-Nand circuit, all the sequential logic circuits shown in FIG. 11 can be formed.

(Proof 4) (a) When the simplified circuit constitutes an AND-OR circuit, OR-AND circuit, AND-NOR circuit and OR-NAND circuit,
All logic circuits for inverting the logic of the input signal of the basic logic circuit are (1) NOR-OR circuit, (2) NOR-NO circuit,
One of (3) NAND-and circuit and (4) NAND-Nand circuit. In the case of (1) and (3),
The logic of the output signal of the basic logic circuit is also inverted. Therefore,
“A circuit that can be selected to configure the basic logic circuit is a circuit obtained by simplifying the logic of the input signal of the basic logic circuit as it is or inverting the logic of the input signal. Circuit, an AND-NOR circuit and an OR-NAND circuit,
All of the sequential logic circuits shown in FIG. Needless to say, in FIG. 11, the NAND circuit may be replaced with a NOR circuit.

(A) Further, when the simplified circuit constitutes an AND-OR circuit, an OR-AND circuit, an AND-NOR circuit, and an OR-NAND circuit, a desired input signal of the basic logic circuit is obtained. By inverting the logic and providing a feedback path, a D flip-flop can be configured. The two sets of D flip-flops that can be configured by this
a, Fb, the output terminal of Fa is connected to the input terminal of Fb, a reference signal φ is applied to Fa, and an inverted reference signal φ bar is applied to Fb, thereby forming a sequential logic circuit. Is a master-slave flip-flop.

By the way, in FIG. 19, the inverting circuits C5 and C6
Is not limited to the configuration shown in FIG. As an example, the inverting circuits C5 and C6 each include a selector 51, 52, and 53 connected as shown in FIG.
And switches SW1 and SW2.

FIG. 20 shows an embodiment of the configuration of the selector 51 in this case. The configuration of the selectors 52 and 53 may be the same as the configuration of the selector 51. The selector 51 includes switch elements 61 and 62 connected as shown. The input terminals of the switch elements 61 and 62 are connected to the input signal In. A,
In. B is applied, the output terminal is connected, and outputs an output signal Out. The control signal Sel is applied to the inversion control terminal of the switch element 61 and the non-inversion control terminal of the switch element 62, respectively.

FIG. 21 shows a selective inversion circuit 54 in this case.
An example of the configuration will be described. The selective inversion circuit 54 includes switch elements 71 to 76 and inverters 77 and 78 connected as shown. In this case, the selective inversion circuit 54
Are two input signals In0 and In1 and one reference signal φ
And three control signals Sel0, Sel1, and Sel2, and output signals Out0 and O0 according to these signals.
ut1 is output.

The configuration of the switches SW1 and SW2 may be the same as the configuration of the switch SW.

FIGS. 22 and 23 show sixth and seventh embodiments of a programmable logic circuit capable of forming a sequential logic circuit by using a plurality of the sub-blocks 41 as described above.

The sixth embodiment of the programmable logic circuit shown in FIG. 22 comprises two sub-blocks 41-1 and 41-2 and two switches SW connected as shown. This programmable logic circuit functions as a combinational logic circuit or a sequential logic circuit such as a flip-flop depending on the on / off state of each switch SW. In the present embodiment, the programmable logic circuit has one input terminal P71 and one output terminal P80. The switch SW is connected between the input terminal P72 of the sub-block 41-1 and the output terminal P74 of the sub-block 41-1 and between the input terminal P76 of the sub-block 41-2 and the output terminal P78 of the sub-block 41-2. It is provided in. The input terminal P71 is connected to the input terminal P73 of the sub-block 41-1. The output terminal P79 of the sub-block 41-2 is connected to the output terminal P79. Furthermore,
The output terminal P75 of the sub-block 41-1 is connected to the input terminal P77 of the sub-block 41-2. The output terminal P79 of the sub-block 41-2 is connected to the output terminal P80.

The seventh embodiment of the programmable logic circuit shown in FIG. 23 comprises four sub-blocks 41-1 to 41-4 and six switches SW connected as shown. This programmable logic circuit functions as a combinational logic circuit or a sequential logic circuit such as a flip-flop depending on the on / off state of each switch SW. In this embodiment, the programmable logic circuit has two input terminals P71 and P111 and two output terminals P80 and P1.
20 are provided. The switch SW is connected between the input terminal P72 of the sub-block 41-1 and the output terminal P74 of the sub-block 41-1, between the input terminal P76 of the sub-block 41-2 and the output terminal P78 of the sub-block 41-2, Between the input terminal P213 of the sub-block 41-3 and the output terminal P115 of the sub-block 41-3, the input terminal P117 of the sub-block 41-4 and the sub-block 41-4.
Between the input terminal P121 of the sub-block 41-1 and the output terminal P1 of the sub-block 41-4.
24, and the input terminal P1 of the sub-block 41-3.
23 and the output terminal P122 of the sub-block 41-2. The input terminal P71 is connected to the input terminal PP73 of the sub-block 41-1.
11 is connected to the input terminal P112 of the sub-block 41-3. Further, the output terminal P of the sub-block 41-1
Reference numeral 75 is connected to the input terminal P80 of the sub-block 41-2, and the output terminal P115 of the sub-block 41-3 is connected to the input terminal P117 of the sub-block 41-4. The output terminal P122 of the sub-block 41-2 is connected to the output terminal P80, and the output terminal P118 of the sub-block 41-4 is connected to the output terminal P120.

The on / off state of each switch SW of the switch circuit C7 can be controlled by various methods. Therefore, four representative control methods will be described below with reference to FIGS.

FIG. 24 is a diagram for explaining the first control method. In this case, each switch SW itself comprises a fuse or an anti-fuse. Therefore, the ON / OFF state of each switch SW is fixedly programmed depending on whether the fuse is blown and blown or the antifuse is blown and short-circuited.

FIG. 25 is a diagram for explaining the second control method. In this case, the on / off state of each switch SW is
It is controlled by signals obtained via the corresponding fuse or antifuse F. Therefore, also in this case, the on / off state of each switch SW is fixedly programmed.

FIG. 26 is a diagram for explaining the third control method. In this case, the on / off state of each switch SW is
It is controlled by a signal of a corresponding bit of the memory 81.
Therefore, the on / off state of each switch SW in this case can be freely programmed by rewriting the contents of the memory 81.

FIG. 27 is a diagram for explaining the fourth control method. In this case, the on / off state of each switch SW is
The output of the memory 81 is controlled by a signal obtained by decoding by the decoder 82. Therefore, also in this case, the on / off state of each switch SW can be freely programmed by rewriting the contents of the memory 81. Furthermore,
In the case of FIG. 26, the bit number of the memory 81 is set to the switch SW.
27, the same number of switches SW can be controlled with a smaller number of bits of the memory 81 because the decoder 82 is used in the case of FIG.

When the third or fourth control method is adopted, the memory 81 may be provided outside the programmable logic circuit, or may be provided inside the programmable logic circuit.

FIG. 28 shows a case where the memories 81 provided for the respective logic cells 1 or 31 are provided outside the programmable logic circuit (FPGA) 85, respectively. That is, each memory 81 is provided in an external memory chip 86 different from the programmable logic circuit 85. Each memory 81 in the memory chip 86 is connected to the corresponding logic cell 1 or 31 in the programmable logic circuit 85.

FIG. 29 shows a case where the memories 81 provided for the respective logic cells 1 or 31 are provided inside the programmable logic circuit 85, respectively. That is,
Each memory 81 is connected to a corresponding logic cell 1 or 31 in the programmable logic circuit 85.

FIG. 30 shows a case where the memories 81 provided for the respective logic cells 1 or 31 are provided inside the programmable logic circuit 85, respectively. In this case, each memory 81 is provided in one logic cell 1 or 31, and is connected to a desired part in the logic cell 1 or 31.

It is to be noted that the number of switches SW required to configure the switch circuit C7 is N, and that all switches SW are turned on / off.
When the number of bits of the memory 81 required to control the OFF state is defined as M, and the operation floor (F (x)) is defined as an operation that returns a minimum integer value not less than the value F (x), M ≧ floor (log ₂ N) always holds.

The value of each bit of the memory 81, that is, the ON / OFF state of each switch SW is determined as shown in FIG. First, a design drawing of a desired logic circuit is created. Next, computer processing is performed based on this design drawing to determine what kind of connection in the programmable logic circuit 85 can realize the function of the desired logic circuit. Then, the on / off state of each switch SW required for making the determined connection is determined, and data necessary for obtaining the on / off state is written in the memory 81.

These processes are shown in a flowchart.
As shown in FIG. In the figure, a step 91 designs a desired logic circuit using an arbitrary design tool. Step 9
2 inputs a design drawing of a desired logic circuit to a computer and converts the data of the design drawing into data relating to the ON / OFF state of the switch SW in the programmable logic circuit 85. In step 93, the programmable logic circuit 85 is programmed so as to function as the desired logic circuit by writing data on the ON / OFF state of the switch SW into the memory 81 inside or outside the programmable logic circuit 85.

In order to connect the logic cells freely, it is necessary to increase the number of signal lines connecting the logic cells and increase the number of programmable switches. However, as the number of signal lines and switches increases, a large area is required to provide input / output paths on the chip of the programmable logic circuit. Further, if the number of switches is large, the memory capacity for storing the on / off state of the switches increases, and it becomes necessary to provide a large number of memory cells. Therefore, an embodiment capable of solving these problems will be described below.

FIG. 33 is a plan view showing an eighth embodiment of the programmable logic circuit according to the present invention. In the figure, 32 × 32 = 1024 logic cells 1 (or 31) are arranged in a matrix in a central cell region 201. Two adjacent logic cells 1 are connected by an inter-cell path 204 including two signal lines. Cell region 201
The input / output path 202 is provided outside the box. The input / output path 202 includes two signal lines that are always at a fixed logical signal level and a plurality of programmable switches S.
And a plurality of signal lines having a structure separated by W.
Outside the input / output path 202, 16 × 4 = 64 input / output pads 203 are provided.

The two fixed logic signal level signal lines are connected to the signal lines for controlling the signal transmission direction of the input / output pad 203 when the signal transmission direction of the input / output pad 203 is constant. Is done. Programmable switch SW
A signal line having a structure separated by
Reference numeral 3 denotes a signal line for inputting a signal from the logic cell 1, or a signal line for the logic cell 1 to input a signal from the input / output pad 203. The signal line for determining the signal transmission direction of the input / output pad 203 includes two signal lines having a fixed logical signal level and a plurality of signal lines having a structure separated by a plurality of programmable switches SW. , Are connected via a programmable switch SW. Other signal lines of the input / output pad 203 are connected to a plurality of signal lines having a structure separated by the plurality of programmable switches SW via the programmable switches SW.

That is, each logic cell 1 is a partial hardware of a minimum unit when a certain function is realized by hardware. Therefore, all the logic circuits can be realized by the combination of the logic cells 1. The logic cell 1 roughly has the following three functions. 1) By programming, a sequential logic circuit such as various flip-flops frequently used in designing a logic circuit and a combinational logic circuit are realized. 2) Output a signal to the input / output path 202. 3) Input a signal from the input / output path 202.

The input / output path 202 is a group of signal lines for transmitting and receiving signals between the logic cell 1 and the input / output pad 203. All signals input from outside the programmable logic circuit via the input / output pad 203 and signals output from the logic cell 1 to the outside of the programmable logic circuit pass through the input / output path 202. In this embodiment,
The input / output path 202 includes an arbitrary number of normal signal lines and an arbitrary number of signal lines having a structure separated by a plurality of programmable switches SW. The input / output path 202 roughly has the following four functions. 1) Input a signal from the input / output pad 203. 2) Output a signal to the input / output pad 203. 3) Input a signal from the logic cell 1. 4) Output a signal to the logic cell 1.

Further, the input / output pad 203 is partial hardware for performing all input operations and output operations of the logic circuit. The input / output pad 203 roughly has the following three functions. 1) Output a signal from outside the programmable logic circuit to the input / output path 202. 2) The signal output from the logic cell 1 to the input / output path 202 is output outside the programmable logic circuit. 3) The operations 1) and 2) are performed simultaneously. However, in this case, the signal transmission direction is such that the logic cell 1
02 is controlled by the signal output to the control signal.

In the case of 1) or 2), since the signal transmission direction is constant, the logic signal level of the direction control terminal of the input / output pad 203 holds a value of “1” or “0”. Connected to signal line.

FIG. 34 shows logic cell 1 and inter-cell path 204.
Indicates connection with Each of the logic cells 1 has an inter-cell path 20 extending in the vertical direction as shown partially enlarged in FIG.
4 and an inter-cell path 204 extending in the lateral direction. Logic cell 1 is an inter-cell path 2 extending in the vertical direction.
The signal line that constitutes 04 is a node (signal sampling point)
The signal lines that are connected by a, d, e, and h and that constitute the inter-cell path 204 extending in the horizontal direction are nodes b, c, f, and g.
Connected by Also, between nodes a and h, nodes b and c
A programmable switch SW is inserted between the nodes d and e and between the nodes f and g. By programming each switch SW, the user determines whether to use the inter-cell path 204 provided between the logic cells 1 as a long-distance wiring or a short-distance wiring. That is, on both sides of each switch SW, a node for inputting / outputting all signals to / from the logic cell 1 is provided.
34B are provided on the intersections of the inter-cell paths 204 extending in the vertical and horizontal directions as shown in the perspective view of FIG.

FIG. 35 shows the logic cell 1 and the inter-cell path 2
FIG. 4 is a circuit diagram showing connection with a switch 04 including a switch SW. As shown in FIG.
4 are connected to corresponding signal lines forming the inter-cell path 204 extending in the horizontal direction via the programmable switches SW. Therefore, it is also possible to connect the signal lines forming the inter-cell path 204 extending in the vertical direction and the signal lines forming the inter-cell path 204 extending in the horizontal direction.

FIG. 36 shows an embodiment of the input / output pad 203. In the figure, terminals 203A, 203B, 203C
And buffers 203E and 203F. Terminal 20
3A is connected to the input / output terminal of the programmable logic circuit. Input and output of all signals between the programmable logic circuit and the outside are performed via this terminal 203A. The output of the buffer 203E is connected to a terminal 203A, and the input of the buffer 203E is connected to a terminal 203B.
On the other hand, the input of the buffer 203F is connected to the terminal 203A, and the output of the buffer 203F is connected to the terminal 203D. A signal to be output from the logic cell 1 to the outside of the programmable logic circuit is input to the terminal 203B.
Further, a signal to be input to the logic cell 1 from outside the programmable logic circuit is output to the terminal 203D. A control signal for determining the signal transmission direction of the input / output pad 203 is applied to the direction control terminal 203C of the input / output pad 203. This control signal is supplied to the buffer 203E as it is and supplied to the buffer 203F after being inverted, so that when one of the buffers 203E and 203F is on, the other is always off.

Next, an embodiment of the input / output path 202 for connecting the input / output pad 203 and the logic cell 1 will be described with reference to FIGS.
This will be described together with No. 9.

In the embodiment shown in FIG.
2 are provided in a loop, and a plurality of programmable switches SW are inserted. Terminals 203B, 203C, 203D of input / output pad 203
Are nodes A, B,. . . Connected to any of the nodes. Thereby, for example, the communication time between the node A and the node H can be reduced.

In the embodiment shown in FIG.
A plurality of programmable switches SW are inserted into one signal line that constitutes No. 2. Also, a programmable switch SW is inserted between the node B and the node F. Terminals 203B, 203C, 2 of input / output pad 203
03D are nodes A, B,. . . Connected to any of the nodes. Thereby, for example, the communication time between the node B and the node F can be reduced.

In the embodiment shown in FIG.
A plurality of programmable switches SW are inserted into one signal line that constitutes No. 2. A fixed wiring is provided between the node B and the node F. I / O pad 203
Terminals 203B, 203C, and 203D are connected to nodes A,
B,. . . Connected to any of the nodes. Thereby, for example, the communication time between the node B and the node F can be reduced.

Next, FIG. 40 shows a main part of the first embodiment of the connection between the input / output pad 203 and the logic cell 1 by the input / output path 202 shown in FIG. In the figure, the programmable switch SW connecting the input / output path 202 with the input / output pad 203 and the logic cell 1 is indicated by a “circle”, and the input / output path 20
2, the programmable switch SW is indicated by the symbol of the switch element. In this embodiment, four input / output pads 203
And two logic cells 1 are connected between a pair of switches SW provided in the input / output path 202.

FIG. 41 shows the input / output path 202 shown in FIG.
Connection between input / output pad 203 and logic cell 1
2 shows a main part of the embodiment. In the figure, the programmable switch SW connecting the input / output path 202 to the input / output pad 203 and the logic cell 1 is indicated by a “circle”, and the programmable switch SW in the input / output path 202 is indicated by a switch element symbol. In this embodiment, two input / output pads 203 and two logic cells 1 are connected between a pair of switches SW provided in an input / output path 202.

FIG. 42 shows the input / output path 202 shown in FIG.
Connection between input / output pad 203 and logic cell 1
2 shows a main part of the embodiment. In the figure, the programmable switch SW connecting the input / output path 202 to the input / output pad 203 and the logic cell 1 is indicated by a “circle”, and the programmable switch SW in the input / output path 202 is indicated by a switch element symbol. In this embodiment, two input / output pads 203 and four logic cells 1 are connected between a pair of switches SW provided in the input / output path 202.

Next, each embodiment of the inter-cell path 204 will be described with reference to FIG.
This will be described with reference to FIGS. For convenience of explanation, it is assumed that the sub-block 11 of the logic cell 1 has a configuration as shown in FIG.

In the embodiment shown in FIG.
4 are connected to each other via a programmable switch SW in a comb shape. As an example, an internal bus 210 including three signal lines i1, i2, and j1 is connected to a programmable switch SW.
Is connected to the sub-block 11 of the logic cell 1. Specifically, each input of the sub-block 11 is connected to at least one of the signal lines i1 and i2 of the internal bus 210 via the switch SW. Further, the sub-block 11
Are fixedly connected to the signal line j1 of the internal path 210, and the signal line j1 is connected to the interconnections 11 to 18 and 11 'to 18' of the inter-cell path 204 via the switch SW. . In this embodiment, 44 (= 8 + 8 + 16)
+ 8 + 4) switch SW, and each input and output of the sub-block 11 can be connected to any of the interconnections 11 to 18 and 11 'to 18' of the inter-cell path 204. That is, in this embodiment, the internal bus 2
Assuming that the number of 10 is L, the number of sum terms or product terms in the sum-product expression in the sub-block 11 of the logic cell 1 is T, and the number of outputs of the sub-block 11 is m, the following relationship is established. I do.

L ≧ T + m In FIG. 43, two OR circuits 11
Since e and 11f are provided, the number of terms in the sum is 2, and the above relationship is L ≧ 2 + 1 = 3.

In the embodiment shown in FIG.
4 are connected to each other via a programmable switch SW in a comb shape. Also, the internal bus 210 is not provided, and the sub-block 11
Are connected to the sub-block 11 of the logic cell 1 via one signal line and the programmable switch SW. Specifically, each input of the sub-block 11 is connected to the interconnections 11 to 18 of the inter-cell path 204 via the switch SW.
It is connected to at least one of l1 'to l8'. Further, the output of the sub-block 11 is connected to the interconnections 11 to 18 and 11 'to 18' via the switch SW. In the present embodiment, 40 (= (4 + 4 + 4 + 4) +1
6 + 8) switch SW is provided, and each input and output of the sub-block 11 can be connected to any of the interconnections 11 to 18 and 11 'to 18' of the inter-cell path 204.

FIG. 45 is a block diagram of the sub-block 11 shown in FIG.
FIG. 3 is a perspective view showing the connection between each input and each of interconnections l1 to l8 and l1 'to l8'. Each input of the sub-block 11 is connected to nodes P1 to P8, P1 'to P8',
To l8, l1 'to l8'.

Incidentally, the logic cell 1 is formed by a so-called bus wiring system.
Interconnect l between the sub-block 11 and the inter-cell path 2104
1 to 18 and 11 'to 18', the programmable switch SW is connected to the sub-block 11 as shown in FIG.
Must be provided for each input and each interconnection l1-l8, l1'-l8 '. Therefore, in the example of FIG. 46, 48 switches (= 8 × 5 + 8) are required. However, the connection to the interconnections l1 'to l8' cannot be made without the specific switches SW1 to SW8.

On the other hand, in the embodiment of FIGS. 43 and 44, the interconnections 11 to 18 and 11 'to 18' are more freely provided.
Can be connected via the switch SW. Further, since the number of switches SW required can be reduced as compared with the case of FIG. 46, the area occupied by the wiring (and the switches SW) for interconnecting the logic cells 1 can be reduced. In the embodiment shown in FIG.
The use of 0 limits the input to the sub-block 11 of the logic cell 1, but this problem does not occur in the embodiment of FIG. In particular, in the embodiment shown in FIG. 44, the number of switches SW passing when connecting
Therefore, the delay of the signal can be reduced.

In each of the embodiments described above, the programmable logic circuit has been described as including a plurality of logic cells. However, it is not necessary that all the logic cells have the above configuration. That is, when the function to be realized by the programmable logic circuit is known in advance, a predetermined number of conventional combinational logic cells and / or sequential logic cells may be provided in addition to the logic cell having the above configuration. In this case, since the number of combination logic cells and / or sequential logic cells that will be used is known in advance, the usage efficiency of the logic cells does not decrease.

The present invention has been described with reference to the embodiments.
The present invention is not limited to these embodiments, and it goes without saying that many modifications and improvements are possible within the scope of the present invention.

[0111]

According to the present invention, in the programmable logic circuit having a plurality of logic cells, at least certain of the logic cell, in its Re itself a predetermined combinational logic functions lifting
Chi, is provided with the connection can switch circuit path between the input and output of the logic cell, realize any combinational logic functions and sequential logic functions by programming the on / off state of the switching circuit As a result, it is possible to improve the utilization efficiency of the logic cells constituting the programmable logic circuit regardless of the configuration of the logic circuit to be realized.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a configuration of a logic cell which is a main part of the first embodiment of the programmable logic circuit.

FIG. 3 is a circuit diagram showing a first embodiment of an internal configuration of a logic cell.

FIG. 4 is a circuit diagram showing a second embodiment of the internal configuration of the logic cell.

FIG. 5 is a circuit diagram showing a third embodiment of the internal configuration of the logic cell.

FIG. 6 is a circuit diagram showing a fourth embodiment of the internal configuration of the logic cell.

FIG. 7 is a circuit diagram showing a fifth embodiment of the internal configuration of the logic cell.

FIG. 8 is a circuit diagram showing a sixth embodiment of the internal configuration of the logic cell.

FIG. 9 is a circuit diagram showing a seventh embodiment of the internal configuration of the logic cell.

FIG. 10 is a circuit diagram showing an eighth embodiment of the internal configuration of the logic cell.

FIG. 11 is a circuit diagram showing a sequential logic circuit that can be realized by a logic cell.

FIG. 12 is a diagram illustrating a connection between a programmable switch of a switch circuit and a signal line of an input / output path.

FIG. 13 is a circuit diagram showing an embodiment of an inversion circuit.

FIG. 14 is a diagram showing an example of connection between a path between cells and a switch circuit.

FIG. 15 is a circuit diagram showing a second embodiment of a programmable logic circuit capable of forming a sequential logic circuit using a plurality of sub-blocks.

FIG. 16 is a circuit diagram showing a third embodiment of a programmable logic circuit capable of forming a sequential logic circuit by using a plurality of sub-blocks.

FIG. 17 is a circuit diagram showing a fourth embodiment of a programmable logic circuit capable of forming a sequential logic circuit by using a plurality of sub-blocks.

FIG. 18 is a block diagram showing a fifth embodiment of the programmable logic circuit.

FIG. 19 is a circuit diagram showing a configuration of a logic cell which is a main part of a fifth embodiment of the programmable logic circuit.

FIG. 20 is a circuit diagram showing one embodiment of a selector.

FIG. 21 is a circuit diagram showing one embodiment of a selective inversion circuit.

FIG. 22 is a circuit diagram showing a sixth embodiment of a programmable logic circuit capable of forming a sequential logic circuit using a plurality of sub-blocks.

FIG. 23 is a circuit diagram showing a seventh embodiment of a programmable logic circuit capable of forming a sequential logic circuit using a plurality of sub-blocks.

FIG. 24 is a diagram illustrating a first control method of the programmable switch.

FIG. 25 is a diagram illustrating a second control method of the programmable switch.

FIG. 26 is a diagram illustrating a third control method of the programmable switch.

FIG. 27 is a diagram illustrating a fourth control method of the programmable switch.

FIG. 28 is a plan view showing a case where a memory is provided outside a programmable logic circuit.

FIG. 29 is a plan view showing a case where a memory is provided inside a programmable logic circuit.

FIG. 30 is a plan view showing a case where a memory is provided inside a programmable logic circuit.

FIG. 31 is a diagram for explaining determination of an on / off state of a programmable switch.

FIG. 32 is a flowchart illustrating a process of determining an on / off state of a programmable switch.

FIG. 33 is a plan view showing an eighth embodiment of the programmable logic circuit.

FIG. 34 is a diagram illustrating connection between a logic cell and an inter-cell path.

FIG. 35 is a circuit diagram showing a connection between a logic cell and an inter-cell path including a programmable switch.

FIG. 36 is a diagram showing one embodiment of an input / output pad.

FIG. 37 is a diagram illustrating an example of an input / output path.

FIG. 38 is a diagram illustrating an example of an input / output path.

FIG. 39 is a diagram illustrating an example of an input / output path.

FIG. 40 is a diagram showing a main part of a first embodiment of connection between an input / output pad and a logic cell by an input / output path.

FIG. 41 is a diagram showing a main part of a second embodiment of connection between an input / output pad and a logic cell by an input / output path.

FIG. 42 is a diagram showing a main part of a third embodiment of connection between an input / output pad and a logic cell by an input / output path.

FIG. 43 is a diagram illustrating an example of an inter-cell path.

FIG. 44 is a diagram for explaining another embodiment of the inter-cell path.

45 is a perspective view showing a connection between each input of a sub-block of a logic cell in FIG. 44 and each interconnection of an inter-cell path.

FIG. 46 is a diagram illustrating connection between a sub-block of a logic cell and a mutual wiring of an inter-cell path by a bus wiring method.

FIG. 47 is a block diagram showing an example of a conventional logic cell.

[Explanation of symbols]

 1,31 logic cell 2 partial circuit 3 switch circuit B input / output path C1, C2 basic logic circuit C3-C6 inversion circuit C7 switch circuit SW programmable switch 11,12 sub-block C11, C12 basic logic circuit C21, C22 basic logic circuit 81 Memory 82 Decoder 85 Programmable logic circuit 86 Memory chip 201 Cell area 202 I / O path 203 I / O pad 204 Intercell path 210 Internal bus

Claims (29)

(57) [Claims] In a programmable logic circuit having a plurality of logic cells, at least a specific logic cell includes an AND-OR circuit, an AND-NOR circuit, an OR-and-AND circuit.
Road, or-nand circuit, nand-and circuit, nand-
Of NAND circuit, NOR-OR circuit and NOR-NO circuit
Basic logic circuit configured using at least one type of circuit
Subroutine that has a predetermined combinational logic function
A lock, and a path connection can switch circuits between the input and output of the sub-blocks, the logic functions and sequential logic functions in any combination by programming the on / off state of the switch circuit A realizable programmable logic circuit. Wherein further comprising input and output paths comprising a plurality of signal lines for outputting signals from the input and the logical cell of a signal to the logic cell, the switching circuit may be any input and output of 該Sa subblock The programmable logic circuit according to claim 1, further comprising a programmable switch connectable to said input / output path. Programmable switch of claim 3, wherein said switch circuit according to claim consisting of full Yuzu or antifuse 2
Programmable logic circuit. 4. The programmable logic circuit according to claim 2, wherein the programmable switch of the switch circuit comprises a switch element whose on / off state is variably set by a first control signal. 5. The programmable logic circuit according to claim 4, further comprising means for generating said first control signal. 6. The programmable logic circuit according to claim 5, wherein said means includes a memory for storing said first control signal. 7. The programmable logic circuit according to claim 5, wherein said means includes a memory for storing control information, and a decoder for generating said first control signal based on the control information in said memory. 8. The number of programmable switches required to configure the switch circuit is N, the number of bits of memory required to control the on / off state of all the programmable switches is M, and the operation floor (F ( 8. The programmable logic circuit according to claim 7, wherein M ≧ floor (log ₂ N) is always satisfied when x)) is defined as an operation that returns a minimum integer value that is not less than a value F (x). 9. The sub-block, wherein each of the basic logic
The logic of any of the input and output signals of the circuit
And an inverting circuit capable of inverting based on the second control signal.
9. Programmable theory according to any one of claims 1 to 8.
Logic circuit. 10. The switch circuit according to claim 1 , wherein:
Connect the path between the input and output of the
To realize the function of flip-flop
The programmable logic circuit according to any one of 1 to 9. 11. The function of the flip-flop is S−
R flip-flop, RS-CK flip-flop, D
Claim flip-flop, a Function of at least one flip-flop out of the J-K flip-flop 1
0 programmable logic circuit. 12. The method of claim 11, wherein the switch circuit is, by not forming the feedback path a path between the input and the output of the previous SL sub-block as a non-connected, to realize the function of the logic circuit combination
The programmable logic circuit according to claim 1 . 13. The function of the combinational logic circuit is
Circuit, NAND circuit, OR circuit, NOR circuit, EXCLU
-Exclusive OR circuit, exclusive NOR circuit and half
Claims that are a function of at least one of the adders
Item 13. The programmable logic circuit according to Item 12. 14. further comprising inter-cell path consisting of signal Line that connects the logic cells to each other, a plurality of programmable switches to the signal line of the inter-cell path is inserted,
The programmable logic circuit according to any one of claims 1 to 13 in which the connection between the programmable switches of the on / off state by Ri said logical <br/> management cell is determined. 15. An input / output pad for inputting and outputting a signal to and from the logic cell, and an input / output path connectable to the inter-cell path and the input / output pad. The programmable logic circuit according to claim 14, wherein the connection to the output path is made through a programmable switch. 16. The programmable logic circuit according to claim 15, wherein said input / output path includes a loop-shaped signal line into which a plurality of programmable switches are inserted. 17. The input / output path includes a first signal line into which a plurality of programmable switches are inserted and a second signal line connecting predetermined two nodes among nodes between adjacent programmable switches. The programmable logic circuit of claim 15, including: 18. The programmable logic circuit according to claim 17, wherein a programmable switch is inserted in said second signal line. 19. The logic cells are arranged in a matrix in a cell region of a programmable logic circuit, the inter-cell paths extend in the vertical and horizontal directions along the arrangement of the logic cells, and the input / output pads are arranged at the outermost periphery. provided outside the logic cell parts, the input and output paths programmable logic circuit according to any one of claims 15 to 18 which are disposed between the logic cell and said input output pad of the outermost portion. 20. The inter-cell path comprises a first interconnection and a second interconnection connected in a comb-like manner via a programmable switch, and the logic cell connects the inter-cell path and an internal bus. are connected via, internal buses, each first interconnection and the second at least one programmable switcher switch the input signal lines are connected through to the input of the logic cell of the interconnect When,
16. The programmable logic circuit according to claim 15, further comprising an output signal line fixedly connected to an output of said logic cell and connected to both said first interconnection and said second interconnection via a programmable switch. 21. Assuming that the number of said internal buses is L, the number of sum terms or product terms in the sum-product expression in said logic cell is T, and the number of outputs of said logic cell is m, L ≧ 21. The programmable logic circuit according to claim 20, wherein a relationship of T + m is established. 22. The inter-cell path is composed of a first interconnection and a second interconnection connected to the comb-like through a programmable switch, the output is the inter-cell path and signals of the logic cell are connected via Route, signal lines are connected via programmable switches to both the first interconnection and the second interconnection, each input of the logic cell first interconnect及beauty the 16. The programmable logic circuit according to claim 15, wherein the programmable logic circuit is connected to at least one of the second interconnections via a programmable switch. 23. A programmable logic circuit having a plurality of logic cells, wherein at least a specific logic cell is an AND-OR circuit, an AND-NOR circuit, an OR-AND circuit,
Road, or-nand circuit, nand-and circuit, nand-
Of NAND circuit, NOR-OR circuit and NOR-NO circuit
Basic logic circuit configured using at least one type of circuit
And a switch having a predetermined combinational logic function and capable of connecting a path between the input and output of the logic cell.
Comprising a latch circuit, to program the on / off state of the switch circuit
Realizes any combinational logic function and sequential logic function
Programmable logic circuit. 24. The semiconductor device further comprises an input / output path provided for at least the specific logic cell and configured by a plurality of signal lines for inputting / outputting data to / from the logic cell; and programmable logic circuit according to claim 23 Symbol mounting further comprises a programmable switch which can be connected to any signal line of the output the output path. Programmable switch of claim 25, wherein said switching circuit is a full Yuzu or antifuse claim 24 programmable logic circuit according. 26. The programmable logic circuit according to claim 24, wherein the programmable switch of the switch circuit is a switch element whose ON / OFF state is variably set by a control signal. 27. The programmable logic circuit according to claim 26, further comprising means for generating said control signal. 28. The programmable logic circuit according to claim 27, wherein said control signal generating means is provided in a memory storing said control signal. 29. The control signal generating means includes: a memory storing the control information; and a decoder decoding the control information to generate the control signal.
8. The programmable logic circuit according to 7.