JP2834169B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a pseudo static random access memory (PSRAM) having a built-in refresh timer circuit.
It relates to technologies that are particularly effective for use in y).

[Conventional technology]

The basic configuration is a memory array in which dynamic memory cells are arranged in a grid,
There is a pseudo static RAM with an input / output interface compatible with M. The pseudo static RAM has a self-refresh function for refreshing data held in a memory cell at a predetermined cycle.

The pseudo static RAM is described in, for example, "Hitachi IC Memory Data Book", pp. 229 to 234, published by Hitachi, Ltd. in March 1987.

[Problems to be solved by the invention]

The conventional pseudo-static RAM described above is
In order to realize the self-refresh function, there are provided a refresh timer circuit for forming a refresh control signal at a predetermined cycle, and a refresh address counter for performing a step operation in accordance with the refresh control signal and sequentially specifying a word line to be refreshed. . Here, the cycle of the refresh control signal must be able to stably guarantee the data holding performance of the dynamic memory cell. Therefore, the refresh timer circuit is provided with a plurality of capacitors and fuse means for switching the cycle of the refresh control signal, and these fuse means are selectively cut in accordance with the data holding performance of the memory cell.

However, it has been clarified by the present inventors that the above-mentioned pseudo-static RAM has the following problems. That is, since the capacitor and the fuse for setting the cycle of the refresh control signal require a relatively large layout area, the number of the capacitors and the fuse is limited. In addition, the disconnection processing of the fuse unit is performed without monitoring the refresh control signal, and the cycle of the refresh control signal itself after disconnection also exhibits a relatively large variation in power supply voltage or temperature and a variation in process. For this reason, it is difficult to finely set the cycle of the refresh control signal in accordance with the data retention performance of the memory cell, and it is necessary to provide a sufficient margin in consideration of process variations and the like. This results in the refresh cycle being shortened more than necessary, and in particular, an ultra-low power consumption type pseudo-static type that is backed up by a battery.
This is one of the reasons why it is not possible to realize a sufficiently low power consumption in a RAM or the like.

An object of the present invention is to provide a semiconductor memory device such as a pseudo-static type RAM which can set a refresh cycle accurately and finely. Another object of the present invention is to provide a battery-backed pseudo-static RA.
The aim is to further reduce the power consumption of M etc.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
An oscillator circuit for forming a clock signal and a counter circuit for performing a stepping operation in accordance with the clock signal and forming a refresh control signal when the counted value reaches a predetermined value are provided in a refresh timer circuit such as a pseudo static RAM. Provide. Further, a fuse means for setting an initial count value corresponding to each bit of the counter circuit is provided, and the refresh control signal can be monitored from outside.

(Operation)

According to the above means, the cycle of the refresh control signal can be set accurately and finely according to the data holding performance of the memory cell. As a result, the refresh cycle of the battery-backed pseudo-static RAM and the like can be substantially lengthened, so that the power consumption of the pseudo-static RAM and the like provided for battery backup can be further reduced.

〔Example〕

FIG. 4 is a block diagram showing one embodiment of a pseudo static RAM (PSRAM) to which the present invention is applied. FIG. 1 also shows the pseudo-static RA of FIG.
FIG. 2 is a circuit block diagram of one embodiment of the M refresh timer circuit RTM, and FIG. 2 is a circuit diagram of one embodiment of the unit counter circuit UTC1 included in the refresh timer circuit RTM of FIG. I have. FIG. 3 is a timing chart of an embodiment of the refresh timer circuit RTM shown in FIG. With reference to these figures, the configuration and operation of the pseudo-static RAM of this embodiment and the features thereof will be described. The circuit elements shown in FIGS. 1 and 2 and the circuit elements constituting each block shown in FIGS. 2 and 4 are not particularly limited, but are formed on one semiconductor substrate such as single crystal silicon. Is done. Also, the second
In the figure, the MOSFET with an arrow added to the channel (back gate) portion is a P-channel type, and is distinguished from an N-channel MOSFET without an arrow.

In the pseudo-static RAM of this embodiment, the memory array is composed of so-called one-element dynamic memory cells, and high integration and low power consumption of the circuit are achieved. Further, X address signals AX0 to AXi and Y address signals AY0 to AYj are input through separate external terminals, respectively, and as chip control signals チ ッ プ, write enable ▼ and output enable signal と し て as control signals.
By providing ▼, it is assumed that the input / output interface conditions compatible with the normal static RAM are provided. In this embodiment, the output enable signal ▲
▼ is not particularly limited, but the refresh control signal ▲
Also used as ▼. That is, when the chip enable signal ▼ is set to the low level before the output enable signal ▼ changes to the low level, the normal output control is performed according to the output enable signal ▼, and the output is performed while the chip enable signal ▼ is at the high level. When the enable signal ▼ is continuously at the low level, the pseudo static RAM is set to the self refresh mode.

Further, the pseudo-static RAM of this embodiment has a timing signal φ in the self-refresh mode.
It includes a refresh timer circuit that forms rc (refresh control signal) at a predetermined cycle, and a refresh address counter RFC that performs a step operation in accordance with the timing signal φrc and sequentially specifies a word line to be refreshed. Among these, the refresh timer circuit RTM forms an oscillation circuit OSC for forming a predetermined clock signal, and performs the stepping operation in accordance with the clock signal, and forms the timing signal φrc when the count value becomes all-bit logic “1”. 8-bit timer counter circuit TMC (counter circuit)
And In this embodiment, the timing signal φ
Although rc is not particularly limited, the chip enable signal ▲
When ▼ is set to a high level higher than the power supply voltage of the circuit, it is transmitted through the data input / output terminal DIO. Each bit of the timer counter circuit TMC includes a correspondingly provided fuse means, as described later,
By selectively cutting these fuse means, the count initial value is arbitrarily set for each bit. As a result, the refresh cycle of the pseudo-static RAM can be accurately and 2-8 while monitoring the timing signal φrc.
It is finely set to the power, that is, 256 steps. When the fuse means of the timer counter circuit TMC is not blown, the initial count value is not particularly limited, but is set to a predetermined value such that the pseudo static RAM has a typical refresh cycle.

In FIG. 4, the memory array MARY includes, but is not limited to, (p + 1) word lines arranged in the vertical direction, q + 1 sets of complementary data lines arranged in the horizontal direction, and complements of these word lines. (P + 1) × (q + 1) dynamic memory cells arranged in a grid at the intersections of the data lines.

The word lines forming the memory array MARY are coupled to a row address decoder RAD, and are selectively selected.
Although there is no particular limitation on the row address decoder RAD,
From the row address buffer RAB, the (i + 1) -bit complementary internal address signals a x0 to a xi (here, for example, the non-inverted internal address signal ax0 and the inverted internal address signal ▼ are collectively represented as a complementary internal address signal a x0. Is supplied, and the timing signal φx is supplied from the timing generation circuit TG. Here, the timing signal φx
Is normally set to a low level, and is set to a high level at a predetermined timing when the pseudo static RAM is set to a normal operation mode or a self-refresh mode.

The row address decoder RAD outputs the timing signal φ
When x is set to a high level, it is selectively activated. In this operation state, the row address decoder RA
D decodes the complementary internal address signals a x0 to a xi and selectively sets the corresponding word line of the memory array MARY to a high level selection state.

The row address buffer RAB receives and holds a row address signal transmitted from the address multiplexer AMX. The complementary internal address signals a x0 to a xi are formed based on these row address signals.

To one input terminal of the address multiplexer AMX,
X address signals AX0 to AXi are supplied via external terminals AX0 to AXi, and refresh address signals rx0 to rx0 to
rxi is supplied. The address multiplexer AMX is further supplied with a timing signal φsr as a selection control signal from the timing generation circuit TG.

The address multiplexer AMX is a pseudo-static type R
When AM is in the normal operation mode and the timing signal φsr is at the low level, the X address signals AX0 to AXi are selected and used as the row address signal. When the pseudo-static RAM is set to the self-refresh mode and the timing signal φsr is set to the high level, the refresh address signals rx0 to rxi are selected and used as the row address signal.

The refresh address counter RFC performs a step-by-step operation according to a timing signal φrc supplied from the refresh timer circuit RTM.
rx0 to rxi are formed. Needless to say, the initial count value of the refresh address counter RFC is "0", and the final count value is "p".

Although not particularly limited, the refresh timer circuit RTM includes an oscillation circuit OSC and a timer counter circuit TMC as shown in FIG. Among them, the timer counter circuit TMC includes, but not limited to, an 8-bit unit counter circuit UTC and an AND gate circuit AG1.

Although not particularly limited, the oscillation signal OSC of the refresh timer circuit RTM is supplied with the timing signal φsr. The oscillation circuit OSC is selectively activated by setting the pseudo-static RAM to the self-refresh mode and setting the timing signal φsr to the high level. In this operating state, as shown in FIG. 3, the oscillation circuit OSC has a predetermined period, for example, 10 μs (microsecond).
A timing signal φtc (clock signal) to be To is formed.

Timing signal φtc formed by oscillation circuit OSC
Are commonly supplied to the clock input terminals CP of the unit counter circuits UTC0 to UTC7 constituting the timer counter circuit TMC. The carry input terminal CI of the unit counter circuit UTC0
Although not particularly limited, the power supply voltage of the circuit, that is, the logic high level is fixedly supplied, and the carry output signal CO, that is, φsc0, is supplied to the carry input terminal CI of the unit counter circuit UTC1 in the next stage. Similarly, the unit counter circuit
UTC1 to UTC6 carry output signal CO, that is, φsc1 to
φsc6 is supplied to carry input terminals CI of the next-stage unit counter circuits UTC2 to UTC7, respectively. The carry output signal CO of the unit counter circuit UTC7, that is, φsc7, is supplied to one input terminal of the AND gate circuit AG1. The timing signal φtc is supplied to the other input terminal of the AND gate circuit AG1, and the output signal is the timing signal φrc, that is, the refresh control signal. The timing signal φrc is used as the refresh address counter RF
C, and also to the timing generation circuit TG and test output buffer TOB, and to the unit counter circuit U
It is supplied in common to the preset input terminals PS of TC0 to UTC7.

The unit counter circuits UTC0 to UTC7 that constitute the timer counter circuit TMC are not particularly limited, but each have a unit counter circuit UTC1 as shown in FIG.
A master latch ML and a slave latch SL, which are formed by cross-connecting a plurality of CMOS inverter circuits, have a basic configuration. Between the output node of the master latch ML and the input node of the slave latch SL, the output signal of the NAND gate circuit NAG1, that is, the internal control signal cp1 and the like (cp0 to cp7; similarly, the unit counter circuit UTC1 is similarly shown as a representative example) Is provided with a clocked inverter circuit CN2 which is selectively brought into a transmission state when is at a high level. The output signal of the slave latch SL is the internal control signal tc1 or the like, and is the third signal of the NAND gate circuit NAG2 that constitutes the hazard prevention circuit HG.
Is supplied to the input terminal of. The output signal of the slave latch SL, that is, the internal control signal tc1 or the like is converted into an inverted internal control signal ▲ ▼ through a CMOS inverter circuit, and furthermore, a clocked signal selectively transmitted when the internal control signal cp1 is at a low level. Via the inverter circuit CN1,
The signal is transmitted to the input node of the master latch ML.

The input node of the master latch ML further receives an internal control signal ps via a connection switching point CS and a transmission gate TG.
1 etc. are supplied. Here, the connection switching point CS is not particularly limited, but is selectively coupled to either the node sp or the sn by the master slice. When the timing signal φrc, that is, the preset input signal PS, is at a high level, the node sp is at a high level on the condition that the corresponding fuse means FP1 is blown. To a high level on condition that the fuse means FP1 and the like to be blown are not cut. When the preset input signal PS is set to the high level, the transmission gate TG is set to the transmission state. As a result, the master latch ML of each unit counter circuit receives the corresponding internal control signal ps1.
For example, according to the connection state of the corresponding connection switching point CS and the disconnection state of the fuse means FP1, the set or reset state is set. That is, the master latch ML of each unit counter circuit outputs its output signal, that is, its internal signal, on the condition that the corresponding connection switching point CS is coupled to the node sp when the corresponding fuse means FP1 and the like are not cut. The control signals tp1 and the like are preset to a set state in which they are at a high level, and the corresponding connection switching point CS
Is reset to a reset state on the condition that is coupled to the node sn side. When the corresponding fuse means FP1 and the like are cut, the master latch ML of each unit counter circuit is preset to a state opposite to the above case.

In the pseudo-static RAM of this embodiment, the initial count value of the timer counter circuit TMC is not particularly limited, but when all the fuse means FP0 to FP7 are not blown, for example, "00000111" in binary, that is, "22" in decimal.
Therefore, the connection switching points CS of the unit counter circuits UTC0 to UTC4 are all connected to the node sn, and the connection switching points CS of the unit counter circuits UTC5 to UTC7 are all connected to the node sp. As described later, the preset signal of the timer counter circuit TMC, that is, the timing signal φrc is “2” when the count value of the timer counter circuit TMC is decimal.
55 ", that is, when all bit logics are set to" 1 ", it is set to a high level in synchronization with the timing signal φtc. Therefore, the timer counter circuit TMC operates in the initial state in which all the fuse means FP0 to FP7 are not cut. It functions as a so-called divide-by-32 counter circuit, that is, the pseudo-static RAM of this embodiment has fuse means FP0 to FP7 corresponding to each bit of the timer counter circuit TMC.
In addition, by providing the connection switching point CS, the refresh cycle in the initial state where all the fuse means are not cut can be set to a typical value, and for example, in accordance with the data holding performance of the memory cell determined by the probe test. The refresh cycle can be individually optimized.

A first input terminal of the NAND gate circuit NAG1 of the unit counter circuits UTC0 to UTC7 constituting the timer counter circuit TMC is coupled to a carry input terminal CI of each unit counter circuit, and a second input terminal thereof is connected to the clock input terminal CP. Is combined with An inverted signal of the preset input signal PS is supplied to a third input terminal of the NAND gate circuit NAG1. The output signal of the NAND gate circuit NAG1 is the clocked inverter circuits CN1 and CN
Supplied to 2. As a result, as shown in FIG. 3, the internal control signals cp1 and the like are selectively set to a low level when both the output carry signal φsc0 and the like and the timing signal φtc of the preceding unit counter circuit UTC0 and the like are set to the high level. Is done. The internal control signal cp1 etc.
Is forcibly returned to the high level.

NAND gate circuit NAG2 that constitutes hazard prevention circuit HG
The output carry signal φsc0 of the unit counter circuit UTC0 of the preceding stage and the like are supplied to the second input terminal. After the output signal of the NAND gate circuit NAG2 is inverted by the CMOS inverter circuit, the output signal is output from the unit counter circuit UTC1 or the like, that is, the output carry signal φsc1 or the like. As a result, as shown in FIG. 3, the output carry signal φsc0 and the like of the unit counter circuit UTC0 and the like of the preceding stage are set to the high level and the output of the corresponding slave latch SL is output. Signal, ie internal control signal tc
When 1 or the like is set to the high level, it is selectively set to the high level in synchronization with the output carry signal φsc0 of the head unit counter circuit UTC0. In other words, the output carry signal of each unit counter circuit is equal to the count value of all unit counter circuits provided in the preceding stage when the output carry signals of all unit counter circuits provided in the preceding stage are at a high level. When it is set to logic "1", it is selectively set to the high level for one cycle of the timing signal φtc. As a result, the output carry signal φsc7 of the last unit counter circuit UTC7 becomes the output carry signal φsc of all the unit counter circuits UTC0 to UTC7 as shown in FIG.
When all of sc0 to φsc7 are set to the high level, in other words, when the count value of the timer counter circuit TMC is set to the logical value of all bits “1”, that is, the decimal number “255”, it is selectively set to the high level.

In FIG. 1, the output carry signal φsc of the unit counter circuit UTC7 is supplied to one input terminal of the AND gate circuit AG1, as described above. The timing signal φtc is supplied to the other input terminal of the AND gate circuit AG1. The output signal of the AND gate circuit AG1 is used as the timing signal φrc as the refresh address counter RF.
C and timing generator TG and test output buffer TOB
And are commonly supplied to the preset input terminals PS of the unit counter circuits UTC0 to UTC7. As a result, as shown in FIG. 3, when the carry output signal φsc7 and the timing signal φtc are both at a high level, in other words, the count value of the timer counter circuit TMC is a logical " When it is set to 1 "and the timing signal φtc is set to the high level, it is selectively set to the high level. As a result, the timing signal φrc, that is, the period Trc of the refresh control signal, is Trc = To × m, where m is the division ratio of the timer counter circuit TMC, that is, modulo. Here, as described above, the modulo m of the timer counter circuit TMC is set to 32 in an initial state in which all the fuse means FP0 to FP7 of the unit counter circuits UTC0 to UTC7 are not cut, and after the probe test, the data holding of the memory cell is performed. Switching is performed by selectively cutting the fuse means according to the performance. As a result, the above cycle Trc
Is 320 μs in the initial state of the pseudo static RAM
After the fuse is cut, an arbitrary value between 0 and 2560 μs can be taken at a 10 μs pitch.

In FIG. 4, one of the complementary data lines constituting the memory array MARY is coupled to the corresponding unit amplifier circuit of the sense amplifier SA, and the other is coupled to the corresponding switch MOSFET of the column switch CSW.

The sense amplifier SA includes q + 1 unit amplifier circuits provided corresponding to each complementary data line of the memory array MARY. Although these unit amplifier circuits are not particularly limited, the timing signal φpa supplied from the timing generation circuit TG
Is selectively activated in accordance with In this operation state, each unit amplifier circuit of the sense amplifier SA amplifies the small read signal output from the (q + 1) memory cells coupled to the selected word line via the corresponding complementary data line, and It is a level or low level binary read signal. When the pseudo-static RAM is set to the self-refresh mode, these binary read signals are rewritten to the corresponding memory cells, and the stored data is refreshed. That is, the word lines W0 to Wp of the memory array MARY are sequentially set to the high-level selection state, and each time the unit amplifier circuits of the sense amplifier SA are simultaneously operated, the refresh operation of the dynamic memory cell is performed in word line units. It can be realized.

The column switches CSW are q + 1 pairs of switch MOSFETs provided corresponding to each complementary data line of the memory array MARY.
including. One of these switch MOSFETs is respectively coupled to a corresponding complementary data line, and the other is commonly coupled to a non-inverted signal line CD and an inverted signal line ▼ of the complementary common data line. The gates of each pair of switch MOSFETs are commonly coupled, and a corresponding data line selection signal is supplied from the column address decoder CAD.

Each pair of switch MOSFETs that make up the column switch CSW
Is turned on when the corresponding data line selection signals Y0 to Yn are alternatively set to the high level, and the memory array
A set of complementary data lines designated as MARY are selectively connected to the common complementary data lines CD and ▲ ▼.

The column address decoder CAD supplies a complementary internal address signal a y of j + 1 bits from the column address buffer CAB.
0 to a yj are supplied, and a timing signal φy is supplied from the timing generation circuit TG. Timing signal φy
Is normally set to a low level, and is set to a high level when the amplification operation by the sense amplifier SA is completed when the pseudo static RAM is selected in the normal operation mode.

The column address decoder CAD is selectively activated by setting the timing signal φy to a high level. In this operating state, the column address decoder CAD decodes the complementary internal address signals a y0~ a yj, and corresponding alternatively to the high level the data line selection signal.

The column address buffer CAB takes in Y address signals AY0 to AYj supplied via external terminals AY0 to AYj,
Hold. Further, based on these Y-address signal AY0～AYj, forming the complementary internal address signals a y0~ a yj.

The complementary common data line CD
Are combined. The main amplifier MA includes, but is not limited to, a write amplifier and a read amplifier. this house,
The input terminal of the write amplifier is coupled to the output terminal of the data input buffer DIB via the internal write data line wd,
Its output terminal is coupled to the complementary common data line CD. On the other hand, the input terminal of the read amplifier is coupled to the complementary common data line CD. The output terminal is coupled to the input terminal of the data output buffer DOB via the internal read data line rd. The timing signal φw is supplied from the timing generation circuit TG to the write amplifier, and the timing signal φr is supplied to the read amplifier.

The write amplifier of the main amplifier MA is selectively activated by the timing signal φw being set to a high level. In this operation state, the write amplifier operates the internal write data w supplied from the data input buffer DIB.
A complementary write signal is formed in accordance with d and supplied to the selected memory cell of the memory array MARY via the complementary common data line CD. On the other hand, the read amplifier of the main amplifier MA is selectively activated by the timing signal φr being set to the high level. In this operation state, the read amplifier further amplifies the binary read signal output from the selected memory cell of the memory array MARY via the complementary common data line CD • ▲, and outputs the data as internal read data rd. Transmit to buffer DOB.

When the dynamic RAM is set to the write operation mode, the data input buffer DIB is selectively activated according to the timing signal φdi supplied from the timing generation circuit TG. In this operation state, the data input buffer DIB captures and holds the write data supplied via the data input / output terminal DIO. In addition, these write signals are transmitted through the internal write data line wd,
The signal is transmitted to the light amplifier of the main amplifier MA.

When the dynamic RAM is set to the read operation mode, the data output buffer DOB is selectively activated according to the timing signal φdo supplied from the timing generation circuit TG. In this operation state, the data output buffer DOB outputs a read signal of the memory cell transmitted from the main amplifier MA via the internal read data rd,
The data is sent out via the data input / output terminal DIO. When the timing signal φdo is at a low level, the output of the data output buffer DOB is in a high impedance state.

The pseudo-static RAM of this embodiment further includes a test output buffer TOB. The test output buffer TOB has
As described above, the timing signal φrc is supplied from the refresh timer circuit RTM, and the timing generation circuit TG
Supplies a timing signal φto. The timing signal φto is selectively set to a high level when the output enable signal ▼ is set to a high level higher than the power supply voltage of the circuit and the pseudo static RAM is set to a predetermined test mode.

The test output buffer TOB is selectively activated by setting the timing signal φto to a high level.
In this operation state, the test output buffer TOB takes in the timing signal φrc and outputs the data input / output terminal DIO
To the outside via. When the timing signal φto is at a low level, the output of the test output buffer TOB is in a high impedance state. That is, in the pseudo-static RAM of this embodiment, the output enable signal ▲
By setting ▼ to a high level higher than the power supply voltage of the circuit,
The self-refresh mode can be performed while monitoring the refresh control signal, that is, the timing signal φrc. As a result, the refresh cycle can be set accurately and finely according to the data holding performance of the memory cell.

The timing generation circuit TG outputs the chip enable signal ▲
Based on ▼, write enable signal ▲, and output enable signal ▲ ▼, the above various timing signals are formed. Further, various timing signals necessary for the self-refresh mode are formed in accordance with a refresh control signal supplied from the refresh timer circuit RTM, that is, a timing signal φrc.

As described above, the pseudo-static RAM of this embodiment
Has a basic configuration of a memory array MARY in which dynamic memory cells are arranged in a lattice pattern, and has a self-refresh function for periodically refreshing data stored in these memory cells. Pseudo-static RAM
A refresh timer circuit RTM for forming a refresh control signal, that is, a timing signal φrc at a predetermined cycle in the self-refresh mode, and a refresh address counter RFC for performing a step operation in accordance with the timing signal φrc and sequentially specifying a word line to be refreshed. And The refresh timer circuit RTM includes an oscillation circuit OSC that forms a predetermined clock signal, and an 8-bit circuit that performs a stepping operation in accordance with the clock signal and forms the timing signal φrc when the count value of all the bits is logic “1”. And a timer counter circuit TMC. In this embodiment, the timing signal φrc is not limited, but is sent out via the data input / output terminal DIO when the output enable signal ▼ is at a high level exceeding the power supply voltage of the circuit. Further, each bit of the timer counter circuit TMC includes a fuse unit provided correspondingly, and by selectively cutting these fuse units, the initial count value is arbitrarily set for each bit. As a result, the refresh cycle of the pseudo-static type RAM is set precisely and finely to 2 8, that is, 256 steps while monitoring the timing signal φrc. As a result, the refresh cycle of the pseudo static RAM is equivalently lengthened, and the current consumption during standby is reduced.

As shown in the present embodiment, when the present invention is applied to a semiconductor memory device such as a pseudo-static RAM having a refresh timer circuit, the following operational effects can be obtained. That is, (1) an oscillator circuit for forming a clock signal in a refresh timer circuit such as a pseudo-static RAM, and a step-in operation in accordance with the clock signal to form a refresh control signal when the counted value reaches a predetermined value. And a fuse circuit for setting an initial count value for each bit of the counter circuit, so that the refresh cycle of the pseudo static RAM or the like can be finely adjusted according to the number of bits of the counter circuit. The effect of being able to set is obtained.

(2) In the above item (1), by enabling the refresh control signal to be monitored from the outside, it is possible to obtain an effect that the refresh cycle of the pseudo-static RAM or the like can be accurately set.

(3) According to the above items (1) and (2), the refresh cycle of the pseudo static RAM or the like can be set accurately and finely in accordance with, for example, the data holding performance of a memory cell determined by a probe test. Is obtained.

(4) According to the above items (1) to (3), the effect that the refresh cycle of the pseudo static RAM can be equivalently lengthened can be obtained.

(5) According to the above items (1) to (4), it is possible to obtain an effect that current consumption during standby of a pseudo-static type RAM or the like that is provided for battery backup can be reduced and its power consumption can be reduced. .

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in FIG. 1, the number of bits of the timer counter circuit TMC is arbitrary, and the circuit configuration of the unit counter circuit shown in FIG. 2 is not limited by this embodiment. The oscillation circuit OSC has its oscillation frequency, that is, the timing signal φtc, by selectively coupling a predetermined capacitor, for example.
May be changed. The typical count initial value of the timer counter circuit TMC set by the connection switching point CS is not necessarily 32.
Also, fuse means FP provided in each unit counter circuit
0 to FP7 may be blown by, for example, an electrical method, or fuse means may be selectively provided only in some unit counter circuits. In FIG.
The memory array MARY may be composed of a plurality of memory mats. In this case, a refresh operation for a plurality of word lines may be performed simultaneously by setting one word line in each memory mat. The pseudo-static RAM may be a so-called multi-bit memory that simultaneously inputs and outputs a plurality of bits of storage data, or may have a refresh mode other than the self-refresh mode. The pseudo-static RAM may be capable of monitoring, for example, the timing signal φtc in addition to the timing signal φrc, or may be dedicated to an external terminal or a test pad for monitoring these signals. Further, the timer counter circuit TMC and the unit counter circuit UTC shown in FIGS.
1, a specific circuit configuration, a combination of each timing signal and internal control signal shown in FIG. 3, and a block configuration of a pseudo static RAM shown in FIG.
Various embodiments can be employed.

In the above description, the case where the invention made by the inventor is mainly applied to a pseudo-static RAM as a background of application has been described. However, the present invention is not limited thereto.
It is also applicable to M and other semiconductor storage devices. The present invention can be widely applied to a semiconductor memory device having at least a refresh timer circuit or a digital integrated circuit device including such a semiconductor memory device.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows. That is, a refresh timer circuit such as a pseudo-static type RAM is provided with an oscillation circuit for forming a clock signal, and a counter circuit for performing a step-by-step operation in accordance with the clock signal and forming a refresh control signal when the counted value reaches a predetermined value. Are provided. Further, a fuse means for setting a count initial value corresponding to each bit of the counter circuit is provided so that the refresh control signal can be monitored from outside. This makes it possible to precisely and finely set the refresh cycle of the pseudo-static RAM or the like according to, for example, the data retention performance of the memory cell determined by a probe test. , Which can promote low power consumption.

[Brief description of the drawings]

FIG. 1 shows a pseudo-static RA to which the present invention is applied.
FIG. 2 is a circuit block diagram showing an embodiment of an M refresh timer circuit, FIG. 2 is a circuit diagram showing an embodiment of a unit counter circuit included in the refresh timer circuit of FIG. 1, and FIG. 4 is a timing chart showing one embodiment of the refresh timer circuit. FIG. 4 is a block diagram showing one embodiment of a pseudo static RAM including the refresh timer circuit of FIG. RTM: refresh timer circuit, OSC: oscillator circuit,
TMC: Timer counter circuit, UTC0 to UTC7: Unit counter circuit, AG1: AND gate circuit. ML: Master latch, SL: Slave latch, CN1 to C
N2: Clocked inverter circuit, CS: Connection switching point, TG: Transmission gate, FP1: Fuse means, HG:
Hazard prevention circuit, NAG1 ~ NAG2 ... Nand gate circuit. PSRAM: pseudo-static RAM, MARY: memory array, SA: sense amplifier, CSW: column switch, RAD
... Row address decoder, CAD ... Column address decoder, RAB ... Row address buffer, AMX ... Address multiplexer, RFC ... Refresh address counter, CAB ... Column address buffer, MA ... Main amplifier, DIB ... Data Input buffer, DOB: Data output buffer, TOB: Test output buffer, TG: Timing generation circuit.

────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Shoji Kubono 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Hitachi Ultra-LSE Engineering Co., Ltd. (56) References JP-A-63 JP-A-206994 (JP, A) JP-A-63-175294 (JP, A) JP-A-61-173522 (JP, A) JP-A-60-83294 (JP, A) (58) Fields investigated (Int. . ⁶ , DB name) G11C 11/40-11/409

Claims (9)

(57) [Claims] An oscillator circuit for forming a clock signal, a refresh timer circuit including a plurality of counter circuits, and forming a refresh control signal by dividing the clock signal at a predetermined ratio by the plurality of counter circuits. A plurality of connection switching points whose connections are determined by wiring to determine a first division ratio of the refresh timer circuit; and
A semiconductor memory device having a plurality of fuse means for setting a frequency division ratio. 2. The semiconductor memory device according to claim 1, wherein said second frequency division ratio can be set to a value larger or smaller than said first frequency division ratio. 3. The counter connection circuit according to claim 1, wherein said plurality of connection switching points and said plurality of fuse means are provided corresponding to said plurality of counter circuits, and said connection switching point is a corresponding one of said counter circuits. A semiconductor, wherein an initial state of a set or reset is determined by wiring, and the fuse means uses one of the set or reset determined at a corresponding connection switching point in the corresponding counter circuit as the other. Storage device. 4. The semiconductor memory device according to claim 1, wherein said semiconductor memory device comprises a plurality of dynamic memory cells;
A semiconductor memory device, further comprising: a refresh control circuit that divides the plurality of dynamic memory cells into a predetermined group and performs refresh repeatedly with the refresh control signal having a predetermined cycle. 5. The semiconductor memory device according to claim 1, wherein, in a specific test mode, data for reading or writing the refresh control signal to or from the dynamic memory cell in the normal mode is input or output. A semiconductor memory device further comprising means for outputting from a terminal to which the signal is output. 6. The semiconductor memory device according to claim 1, wherein said connection switching point is connected to a wiring by a master slice. 7. A plurality of dynamic memory cells, a refresh control circuit for dividing the plurality of dynamic memory cells into a predetermined group and repeatedly performing refresh by a refresh control signal having a predetermined cycle, and forming a clock signal. An oscillation circuit, a refresh timer circuit that forms the refresh control signal by dividing the clock signal at a predetermined ratio by a plurality of counter circuits, a plurality of connection switching points, and a plurality of fuse units. In the semiconductor memory device, in order to determine a first frequency division ratio of the refresh timer circuit, a first step of connecting the plurality of connection switching points to a predetermined path by wiring is performed according to the first frequency division ratio. Inspecting the refresh control signal and checking the refresh control signal according to the result of the inspection. Method of manufacturing a semiconductor memory device characterized by a second step of cutting the means to allow changing the first division ratio to the second division ratio. 8. The method according to claim 7, wherein the plurality of connection switching points and the plurality of fuse units are provided corresponding to the plurality of counter circuits, and the first step is performed by wiring connection at the connection switching point. Determining the reset or preset of the corresponding counter circuit, and the second step is to switch one of the reset or preset determined at the corresponding connection switching point in the corresponding counter circuit by cutting the fuse means. A method of manufacturing a semiconductor memory device. 9. The method of manufacturing a semiconductor memory device according to claim 7, wherein said plurality of connection switching points are interconnected by a master slice.