JP2830122B2 - Microprocessor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a microprocessor.

[Conventional technology]

Conventionally, in a microprocessor, the gain of a clock used is not externally controlled. In order to reduce noise energy transmitted / radiated from a board using the microprocessor, the gain output from the microprocessor is not used. For example, a filter such as a lag filter is inserted for each clock to cut a strong conducted / radiated energy component.

FIG. 3 is a block diagram showing an example of a conventional microprocessor. In FIG. 3, the microprocessor
25 includes an oscillation circuit 26, a buffer 27, and an internal circuit 28. The output of the buffer 27 is connected to a filter 29 having a band cut characteristic.

A part of the clock output from the oscillation circuit 26 is input to the internal circuit 28, and also input to the filter 29 via the buffer 27, and the microprocessor 29
Unnecessary conduction / radiation components of the clock output from 25 are cut and supplied to a predetermined external circuit. In this case, rounding, distortion, delay, and the like of the clock waveform due to the filter 29 occur. Particularly, when the clock frequency is high, the delay is often unacceptable in order to synchronize with the external connection circuit. FIGS. 4A and 4B show input / output waveforms of the filter 29, respectively.

[Problems to be solved by the invention]

In the conventional microprocessor described above, among the unnecessary components transmitted / emitted from the electronic circuit product including the microprocessor, particularly, the component based on the basic clock frequency of the microprocessor is higher than other frequency components.
Generally, the level of radiant energy also increases,
It has become difficult to suppress this component. For this reason, a filter for cutting the unnecessary conduction / radiation components is used. However, insertion of this filter causes rounding, distortion, delay, and the like in an output clock,
In particular, in the case of a system having a high clock frequency, in order to establish high-speed synchronization with an external connection circuit, the delay is often not allowed to occur, which is a drawback of causing a failure. In addition, there is a disadvantage that the rounding and distortion during the transition period of the clock waveform reduce the noise resistance of the system.

[Means for solving the problem]

The microprocessor of the present invention is a microprocessor that functions to supply an internal clock signal to an external circuit in order to synchronize timing with a predetermined external circuit arranged in the periphery. A clock generating means for generating the clock signal supplied to the internal circuit, and a control by a predetermined control voltage supplied from an external clock gain adjusting means in response to the input of the clock signal generated by the clock generating means Clock level control and adjustment means functioning to control and adjust the output voltage level of the clock signal to an appropriate level through operation and to supply the clock signal to the external circuit is provided at least internally.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 (a) is a block diagram including a first embodiment of the present invention and an external circuit placed around it, and FIG. 1 (b) is a partial block diagram of FIG. 1 (a). As shown in FIG. 1 (a), the microprocessor 1 of this embodiment
Peripheral circuit 5 of external circuit and clock gain adjusting circuit 6
In response to the above, the oscillation circuit 2, the amplification circuit 3, and the internal circuit 4
And is provided. As shown in FIG. 1 (b), in the present embodiment, the amplifier circuit 3 includes a PMOS transistor 7 and an NMOS transistor 8,
The clock gain adjustment circuit 6 includes a resistor 9 and a Zener diode 10.

Part of the basic clock output from the oscillation circuit 2 is input to the internal circuit 4, and part of the basic clock is input to the amplifier circuit 3, amplified, and output to the peripheral circuit 5. A constant voltage divided by the resistor 9 and the zener diode 10 is supplied to the amplifier circuit 3 from the clock gain adjustment circuit 6 as a control voltage for the output voltage level of the clock, and the PMOS transistor 7 and the NMOS transistor 8 In the amplifier circuit 3 based on the combination of the above, the clock input from the oscillation circuit 2 is set to a predetermined output voltage level and sent to the peripheral circuit 5. Note that the internal circuit 4 also includes an amplifier circuit for the clock input from the oscillation circuit 2, but the reason why the clock output from the amplifier circuit 3 is not used for the internal circuit is that the peripheral circuit wraps around. This is because the effect of the coming noise is not given to the internal circuit 4 included in the microprocessor 1.

Next, a second embodiment of the present invention will be described. FIG. 2 (a) is a block diagram including a second embodiment of the present invention and an external circuit placed around it, and FIG. 1 (b) is a block diagram showing the second embodiment.
FIG. 2 is a partial block diagram of FIG. As shown in FIG. 2A, the microprocessor 11 of the present embodiment includes an oscillation circuit 12, an amplification circuit 13, and an internal circuit corresponding to the peripheral circuit 15 of the external circuit and the clock gain adjustment circuit 16. 14 and
It is comprised including. As shown in FIG. 2 (b),
In the present embodiment, the amplifier circuit 13 is a PMOS transistor
Through circuit 17 including 18, 19 and NMOS transistors 20, 21
And PMOS transistors 22 and 23 and NMOS transistor 24
And a clock gain adjustment circuit.
16 is composed of a resistor 25 and a Zener diode 26.

This embodiment is different from the above-described first embodiment in that the present embodiment can be implemented using the existing test terminal 101 without newly providing an external terminal. The test terminal 101 is an input terminal, and when a high level is input, the microprocessor 11
Operates in normal mode, and operates in test mode when a low level is input. The test mode is used for non-defective inspection at the time of factory inspection, and the user generally uses the test mode fixed at a high level.

A part of the basic clock output from the oscillation circuit 12 is input to the internal circuit 14, a part is input to the amplifier circuit 13, amplified, and output to the peripheral circuit 15. When the terminal 101 is at a high level, a signal for controlling the amplitude gain is input from the terminal 101 to the amplifier circuit 13. The high level voltage of the external output terminal of the amplifier circuit 13 is the voltage between the drain and the source of the PMOS transistor 23 because the PMOS transistor 22 is off and the voltage level of the terminal 101 is the same.

From the clock gain adjustment circuit 16, a constant voltage divided and set by the resistor 25 and the zener diode 26 is supplied as a control voltage for the clock level.

When the input of the terminal 101 is at the low level, the PMOS transistor 22 is turned on, and the high level output voltage of the clock output signal supplied from the amplifier circuit 13 to the peripheral circuit 15 is
The voltage is the same as the voltage level of V _DD .

〔The invention's effect〕

As described above in detail, the present invention makes it possible to reduce the level of clock noise by adjusting the amplitude of a clock in a microprocessor by an external control circuit connected to an external terminal. In addition, there is an effect that the reliability of the electric circuit product in the peripheral circuit can be improved.

[Brief description of the drawings]

FIG. 1 (a) is a block diagram of a first embodiment of the present invention and peripheral circuits, FIG. 1 (b) is a partial block diagram of FIG. 1 (a), and FIG. FIG. 2 (b) is a partial block diagram of FIG. 2 (a), FIG. 3 is a block diagram of a conventional example, FIG. (A) and (b) are diagrams showing input / output waveforms in the conventional example. In the figure, 1, 11, 25 ... microprocessor, 2,
12, 26 ... oscillation circuit, 3, 13 ... amplification circuit, 4, 14, 28
... internal circuits, 5, 15 ... peripheral circuits, 6, 16 ... clock gain adjustment circuits, 7, 18, 19, 22, 23 ... PMOS transistors, 8, 10, 21, 24 ... NMOS transistors.

Claims (1)

(57) [Claims] 1. A microprocessor functioning to supply an internal clock signal to an external circuit in order to synchronize timing with a predetermined external circuit disposed around the microprocessor. A clock generation unit that generates the clock signal supplied to the control unit; and a control unit that receives a clock signal generated by the clock generation unit and performs control by a predetermined control voltage supplied from an external clock gain adjustment unit. And a clock level control adjusting unit that functions to control and adjust the output voltage level of the clock signal to an appropriate level via the external circuit and supply the output voltage to the external circuit.