JP2824736B2 - Sense circuit of semiconductor memory device and semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention selects and outputs output data of a memory cell selected according to a read address from a plurality of memory cells corresponding to one data line of an output data bus of a semiconductor memory device. The present invention relates to a sense circuit that amplifies and outputs the amplified data to one data line of a data bus. In particular, a plurality of memory cells are divided into a plurality of groups, and a pre-sense amplifier for amplifying the output of the memory cell is provided for each of the groups, and a wired-OR (OR) of the outputs of the pre-sense amplifiers is used to obtain a read address. The present invention also relates to a sense circuit that selects output data of a memory cell selected together.

[0002]

2. Description of the Related Art As the capacity of a semiconductor memory device has been increased, the chip area has increased, and as a result, the wiring length of a read data bus in the chip has become longer. When the wiring length becomes longer,
The resistance R and the parasitic capacitance C of the wiring increase, and a signal delay (RC delay) due to the wiring increases, which hinders a reduction in access time.

Therefore, conventionally, in order to reduce the parasitic capacitance of the data bus wiring of the sense circuit after the pre-sense amplifier, the collector node output of the current switch of the ECL constituting the pre-sense amplifier is output by the emitter node via the emitter follower. It is proposed to output to a bus (ISSCC 91 (SESSION 3)
/ HIGH-SPEED RAM / PAPER WP
3.5)). In other words, as is apparent from the structure of the bipolar transistor, the parasitic capacitance of the emitter is sufficiently smaller than the parasitic capacitance of the collector. Therefore, when output is performed by the emitter node via the emitter follower, the parasitic capacitance of the data bus wiring after the pre-sense amplifier is obtained. This is because it can reduce.

Further, according to the above-mentioned prior art, a circuit for controlling a base voltage of an emitter follower of a presense amplifier output section is provided, and the base voltage of a presense amplifier which does not include a memory cell corresponding to a read address is usually adjusted. Is sufficiently lower than the signal voltage. Therefore, a clear level difference appears in the output voltage (emitter voltage) of the output emitter follower between the case where the selected memory cell is included and the case where the selected memory cell is not included.
By adopting R, the output signal of the selected memory cell can be easily selected or specified.

Thus, a plurality of pre-sense amplifiers are appropriately divided into a plurality of groups, a wired OR of their outputs is taken for each of the divided pre-sense amplifier groups, and a wired OR output of these groups is further passed through an emitter follower.
Since it is possible to adopt a configuration in which the wired OR is employed in a plurality of stages in a hierarchical manner, the RC delay can be reduced by dividing the data bus wiring of the sense circuit into multiple stages.
That is, since the RC delay is determined by the RC from the emitter of the emitter follower in the preceding stage to the base of the emitter follower in the stage, the wiring length between the stages can be further reduced by dividing the data bus wiring. Because.

[0006]

However, the emitter output voltage of the emitter follower is equal to the signal voltage input to the base of the emitter follower by the base-emitter voltage V _BE (for example, about 0.8 V). descend. Therefore, if the wired OR via the emitter follower is divided into a plurality of stages, the signal voltage is greatly reduced, and becomes lower than the lower limit voltage of the operation of the sense amplifier provided in the final output section or the operation of the next-stage emitter follower. Cases arise.
For example, if the sense amplifier is ECL (Emitter-Coupled Logi
c), the voltage drop between the base and the emitter of the current switch is V
Assuming that _BE is 0.8 V and the minimum operating voltage of the constant current source connected to the emitter of the current switch is 0.4 V, the lower limit input voltage at which the current switch can operate is about 1.2 V. Therefore, when the power supply voltage of the memory device is 3.3 V, it is not possible to provide three or more stages of wired OR via the emitter follower, including the emitter follower at the output part of the pre-sense amplifier. Thus, the shortening of the access time is limited.

Further, if an attempt is made to lower the power supply voltage (for example, 2.0 V) in order to reduce power consumption, multi-stage data buses will be hindered, and an increase in access time will be limited.

There is also a method in which the level of the signal voltage lowered by the emitter follower is boosted by a shift-up circuit using a current switch. However, the signal voltage boosted and output by the current switch is constant regardless of the level of the input signal voltage. Therefore, although the output signal of the selected pre-sense amplifier is higher than the output signals of the other non-selected pre-sense amplifiers, if the voltage is boosted by the current switch, it becomes the same level, so that it is impossible to distinguish. In other words, wired O
The relative relationship of the level of the input signal of R will be lost,
Even if the wired OR is employed, the output signal of the selected memory cell cannot be specified. Therefore, when the voltage is boosted by the current switch, a logic circuit for separately selecting the output signal of the pre-sense amplifier selected from the output signals is required, and the configuration of the sense circuit becomes complicated.

SUMMARY OF THE INVENTION It is an object of the present invention to divide the outputs of a plurality of pre-sense amplifiers into a plurality of stages in a hierarchical manner and take a wired OR through an emitter follower. To provide a sense circuit that can ensure the above.

Another object of the present invention is to take a wired OR of the outputs of a plurality of pre-sense amplifiers having an emitter follower in the output section, secure the operating voltage of the last-stage sense amplifier, and reduce the power supply voltage. It is to provide a sense circuit that can be reduced.

It is another object of the present invention to provide a semiconductor memory device in which the access time is shortened and the power supply voltage is reduced.

[0012]

In order to achieve the above object, a first aspect of the present invention is to read from a plurality of memory cells provided for each of a plurality of memory cell groups and belonging to each memory cell group. Pre-sense amplifiers that amplify and output the pre-sense signals, and divide the pre-sense amplifiers into a plurality of pre-sense amplifier groups, and connect the outputs of the pre-sense amplifiers to each pre-sense amplifier group in common via an emitter follower to wire A plurality of common lines that take an OR, a plurality of common lines provided by dividing the plurality of common lines into a plurality of stages so as to take a wired OR of the signals, and connecting the respective stages by an emitter follower, and a final stage And a sense amplifier for amplifying and outputting the output of the common line of the plurality of common lines. During, N side of the PN junction is connected to the common line of the preceding stage, P side is connected to the common line of the succeeding stage, and P
A shift-up circuit whose side is connected to a high-potential power supply via a first current source is inserted.

According to a second aspect of the present invention, there is provided a plurality of pre-sense amplifiers provided for each of a plurality of memory cell groups and amplifying and outputting signals read from a plurality of memory cells belonging to each memory cell group. The plurality of pre-sense amplifiers are divided into a plurality of pre-sense amplifier groups, and the outputs of the pre-sense amplifiers are commonly connected to each of the pre-sense amplifier groups via an emitter follower, and a plurality of common lines for taking a wired OR are used. A sense amplifier for amplifying and outputting a signal obtained by taking a wired OR of line signals, wherein a pull-up circuit is connected to a common line of the pre-sense amplifier group, and The circuit includes a pre-sense amplifier belonging to the pre-sense amplifier group including a memory cell selected by an address. A shift-up circuit comprising a multi-emitter transistor having a plurality of emitters for boosting a signal voltage at an input portion of the sense amplifier by operating the common line to connect to a high voltage power supply when the select signal shown is not selected And a common line is connected to each emitter of the multi-emitter transistor, a collector and a base are connected in common, connected to a high voltage power supply via a current source, and a base is connected to an input of the sense amplifier. A shift-up circuit is inserted.

[0014]

According to the present invention, the signal level of the common line can be shifted up by the voltage corresponding to the forward voltage drop (V _D ) of the PN junction by the PN junction of the shift-up circuit. Therefore, even if the signals of a plurality of common lines are boosted by the shift-up circuit of the present invention, the signals can be shifted up while maintaining the level relationship between the signal levels of the common lines. By taking the OR, only the output signal of the selected pre-sense amplifier can be output via the sense amplifier.

Further, the step-up level can be adjusted to an integral multiple of V _D by the series number of stages of the PN junction. For this reason, even if the signal voltage is reduced according to the number of stages of the emitter follower by taking a plurality of stages of wired OR via the emitter follower, the shift-down circuit lowers the operation lower limit voltage of the ECL current switch or the subsequent stage of the emitter follower. Can be secured. Furthermore, a sense circuit that can operate even when the voltage of the power supply is reduced to, for example, 2.0 V or less can be realized.

It is preferable that the pre-sense amplifier amplify an input signal by a current switch and output the amplified signal via an emitter follower, since the parasitic capacitance of the data bus wiring can be further reduced. In this case, when the signal is amplified by the current switch, the signal levels of the plurality of pre-sense amplifiers become the same. Therefore, when the selection signal of the pre-sense amplifier is not selected, the signal input to the base of the emitter follower is lower than the normal signal voltage. In addition, a base voltage control circuit for switching to a sufficiently low voltage must be provided.

Further, the current set value of the first current source of the shift-up circuit is set to be smaller than 1/2 of the set current value of the second current source connected between the common line of the preceding stage and the low potential power supply. It is preferable to set a small value. Thus, the influence of the potential on the common line due to the current flowing from the first current source via the PN junction can be reduced.

The PN junction can be realized by a diode or a diode-connected transistor.

The shift-up circuit is preferably provided at a position near the common line on the subsequent stage.

On the other hand, according to another aspect of the present invention, among the common line signals input to the plurality of emitters of the multi-emitter transistor, the pull-up circuit receiving the selection signal indicating selection does not operate. The line signal is input to the emitter of the multi-emitter transistor as it is, and the pull-up circuit to which the unselected selection signal is input operates,
The common line signal is raised to the voltage of the high voltage power supply and input to the emitter of the multi-emitter transistor. As a result, current flows from the collector of the multi-emitter transistor to the common line where the level of the signal input to the emitter is the lowest, and the voltage of the common connection between the collector and base, which is the output of the shift-up circuit, is input to the emitter. the voltage of the signal level is the lowest common line was, because is boosted by a voltage corresponding to a forward voltage drop V _D of the PN junction, can be correspondingly low the supply voltage.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIGS. 1 to 3 show a configuration of a semiconductor memory device according to an embodiment of the present invention, mainly a sense circuit. FIG. 1 is a configuration diagram of a sense circuit according to a characteristic part of the present invention, FIG. 2 is a schematic diagram of a portion related to a sense circuit of a semiconductor memory device, and FIG. 3 is a configuration diagram of a semiconductor memory mat and a pre-sense amplifier. These figures show only a portion corresponding to one bit of the data bus for the sake of simplicity, but the other bits have the same configuration. The output signal of the memory cell is a pair of complementary signals (H, L) as shown in FIGS. 1 and 3, but is shown by a single line in FIG. 2 for simplicity.

As shown in FIG. 2, the number of memory cells corresponding to the memory capacity is divided into a plurality (eight in the figure) of rectangular memory blocks 10 and symmetrically arranged on a semiconductor chip. Each memory block 10 is divided into a plurality (for example, 16) of memory mats 30 having the configuration shown in FIG. Each memory mat 30 is plural (for example, eight)
Column 40. Each column 40 is configured to include a plurality (for example, 1024) of memory cells 31.

As shown in FIG. 1, each memory block 10
The number of pre-sense amplifiers 11 corresponding to the number of the memory mats 30 are arranged on the side of the chip center side.
The output of each pre-sense amplifier 11 is commonly connected to a first-layer common line (common emitter line) 12. The first-layer common line 12 is connected to a low-potential power supply Vee via a current source 13 and to a second-layer common line 15 via a first emitter follower 14.

The second level common line (common emitter line) 1
5 is connected to a low-potential power supply Vee via a current source 16 and to a third-layer common line (common emitter line) 20 via a shift-up circuit 17 and a second emitter follower 19. I have.

The third level common line 20 is connected to the low potential power supply Vee via the current source 21 and to the input of the sense amplifier 22. The output of the sense amplifier 22 is connected to an output buffer (not shown) via one corresponding bit line 23 of the data bus.

The detailed configuration of each part of the embodiment having the above-described configuration will be described along a data read path of a memory cell using an SRAM as an example. The memory cell 31 is formed by a flip-flop and a transfer gate.
As shown in FIG. 3, the output ends of the plurality of memory cells 31 included in the column 40 are connected to a pair of data lines 32a, 32a.
2b. Further, a selection signal is input to each memory cell 31 via a word line WL33. A load circuit 34 is connected to the data lines 32a and 32b, and each of the data lines 32a and 32b is
Common lines (common data lines) 3 via 5a and 5b
6a, 6b. The common lines 36a and 36b are commonly connected to the data lines 32a and 32b of a plurality of (eight in this embodiment) columns 40. by this,
According to the selection signal input to the word line 33 and the column selection switches 35a and 35b, the storage contents of the specific memory cell 31 are changed to the common lines 36a and
b. The common lines 36a and 36b have a plurality of columns 40.
Of the data lines 32a and 32b are input to the pre-sense amplifier 11.

The pre-sense amplifier 11 has a known configuration described in the related art, and complementary signals H and L input from the common lines 36a and 36b are input emitter followers 41, respectively.
Is input to the current switch 42 and amplified.
The signal is output to the first-layer common lines 12a and 12b via the base voltage control circuit 43 and the output emitter follower 44. The collectors of the bipolar transistors Q ₁ and Q ₂ constituting the input emitter follower 41 are connected to a high potential power supply Vcc,
The emitter is connected to the bases of the bipolar transistors Q ₃ and Q ₄ constituting the current switch 42. The emitters of these transistors Q ₁ and Q ₂ are connected to current sources 45 and 4
6 is connected to Vee. The input emitter follower 41 shifts down the level of the complementary signals H and L by 1 V _BE in order to prevent the saturation operation of the ECL current switch 42 due to the complementary signals H and L.

The collectors of the bipolar transistors Q ₃ and Q ₄ constituting the current switch 42 are connected to the base voltage control circuit 43 as outputs, respectively, and to Vcc via resistors RL and RH. The emitters of the transistors Q ₃ and Q ₄ are commonly connected, and are connected to Vee via the current source 47.

When the input pre-sense amplifier selection signal is "select", the base voltage control circuit 43 outputs the output signal of the current switch 42 to the bases of the bipolar transistors Q ₅ and Q ₆ constituting the output emitter follower 44 as it is. I do. When the pre-sense amplifier selection signal is “non-selected”, a voltage sufficiently lower than the output signal of the current switch 42 is output.

The collectors of the transistors Q ₅ and Q ₆ of the output emitter follower 44 are connected to Vcc. Also,
The emitters of the transistors Q ₅ and Q ₆ are connected to the first-level common lines 12a and 12b, respectively. These common lines 12a and 12b are connected to Vee via current sources 13a and 13b, respectively. Note that the current switch 4
Reference numeral 2 denotes a bipolar transistor. However, a MOS transistor can be used instead.

The first-layer common lines 12 a and 12 b are provided separately for each memory block 10, and take the wired OR of the output signals of the pre-sense amplifiers 11 connected to one memory block 10. I have.

The first line of the common line 1 of the memory block 10
As shown in FIG. 1, 2a and 2b are connected to second-layer common lines 15a and 15b via a first emitter follower 14 as a data transfer for each of a plurality of memory blocks 10 that are appropriately determined. . The first emitter follower 14 includes a pair of bipolar transistors Q ₇ and Q ₈ corresponding to a pair of complementary signals.
_7, the collector of Q ₈ is connected to Vcc, which are connected to the common emitter line 15a, the b. Also, the common line 15
a and b are connected to Vee via current sources 16a and 16b, respectively. The first-layer common lines 12a and 12b of the other memory blocks 10 are also connected to the second-layer common lines 15a and 15b via the emitter followers 14. This allows
A wired OR of the output signals of the plurality of emitter followers 14 connected to the common lines 15a and 15b is employed. By this emitter follower 14, the first-layer common lines 12a and 12b
And the common lines 15a and 15b of the second hierarchy are separated, and the resistance R and the parasitic capacitance C of the wiring which substantially affect the signal delay are reduced.

Next, the shift-up circuit 17 according to the feature of the present invention will be described. The shift-up circuit 17 is a circuit that boosts the signal voltage of the pair of common lines 15a and 15b, and connects the cathode of a series connection circuit of diodes D ₁₁ and D _{12 to} the common line 15a, and connects the diode D ₂₁ to the common line 15b. connects the cathode of the series connection circuit of D _22, with the outputs their anodes, respectively a current source 24
It is connected to Vcc via a and b. Here, the number of series-connected diodes is not limited to two, and is appropriately selected according to the boosting level. In other words, the boost level corresponds to the forward drop V _D (= V _BE ) of the diode, so that a necessary number of them may be used in series. Further, the present invention is not limited to a diode, and a bipolar transistor may be used by connecting a base and a collector (so-called diode connection).

Outputs 18a, b of shift-up circuit 17
Are, as shown in FIG. 1, bipolar transistors Q ₉ ,
Through the second emitter follower 19 consisting of Q _10, it is connected a common line 20a of the third layer, the b.
A signal boosted by another shift-up circuit (not shown) is output to the common lines 20 a and 20 b of the third hierarchy via the second emitter follower 19. Thus, the third-layer common lines 20a and 20b take the wired OR of the output signals of the connected second emitter followers 19. In this embodiment, the final stage is a wired OR.

Thus, the final stage of the wired OR
And a pair of complementary signals obtained from the sense amplifier 2
Are input to the bases of two bipolar transistors Q ₁₁ and Q ₁₂ . The collectors of these transistors Q ₁₁ and Q ₁₂ are connected to Vcc via resistors R ₁ and R ₂ , respectively.
The emitter is connected to Vee via a current source 25.

The operation of the embodiment constructed as described above will be described focusing on the shift-up circuit 17 which is a characteristic part.
This will be described with reference to FIG. For simplicity of description, as shown in FIG.
4 common lines 12a with a wired OR of 1 output
(12a ₁ , 12a ₂ , 12a ₃ , 12a ₄ ) are input, and are wired OR with the common line 15a via the bipolar transistor Q ₇ (Q ₇₁ , Q ₇₂ , Q ₇₃ , Q ₇₄ ) of the emitter follower 14 respectively. And shift up circuit 1
The operation of boosting the voltage by the circuit including the seven diodes D ₁₁ and D ₁₂ will be described.

Now, Vcc = 0v, Vee = -3.3v
And then, the pre-sense amplifier 1 connected to a common line 12a ₁
It is assumed that 1 is selected. The output voltage of the output emitter follower 44 of the selected pre-sense amplifier 11 is, for example, -1.2 V (or -1.5 V), and the output voltage of the output emitter follower 44 of the unselected pre-sense amplifier 11 is -2. 2.0. Transistor Q ₇₁ to Q ₇₄ of each emitter follower since the emitter is commonly connected, most base voltage is high the transistor Q ₇₁ is turned on for Vee. This allows
The emitter voltage of the common line 15a is equal to its base voltage (-1.
2 V) to -2.0 V which is lower by V _BE (= 0.8 V). On the other hand, the other transistors Q _{72 to} Q ₇₄ involved in non-selection
Has a base voltage of -2.0 V and cannot be turned on because of the same potential as the emitter voltage. Therefore, only the output 12a ₁ of the output emitter follower 44 of the pre-sense amplifier 11 is selected is output to the common line 15a, which will cause the wired OR of the four signals of a common line 12a ₁ ~12a ₄ is employed.

The signal (−2.0 V) of the common line 15 a is further wired-ORed by using the emitter follower 19, and the signal of the common line 20 is converted to the bipolar transistor Q ₁₁ of the ECL current switch constituting the sense amplifier 22.
The base-Vee voltage is 0.5
Since only v can be obtained, the sense amplifier 22 cannot be operated. That is, as described above, the operating lower limit voltage of the ECL current switch is such that the voltage drop V _BE between the base and the emitter of the current switch is 0.8 V, and the minimum operating voltage of the constant current source connected to the emitter of the current switch is 0. This is because if it is .4v, it is about 1.2v.

Therefore, in this embodiment, the diodes D ₁₁ ,
Common line 15a by the shift-up circuit 17 composed of a D ₁₂
Is boosted. That is, the diodes D ₁₁ and D ₁₂ are Vcc → current source 24a → D ₁₁ → D
₁₂ → current source 16a → Vee, so that their anode voltages are lower than the signal voltage of the common line 15a by two diode forward voltage drops = 2 × V _D
(= 2 × 0.8 v), and is boosted to −1.0 v. That is, the signal voltage obtained by boosting the voltage corresponding to the number of diodes in series with the signal voltage × V _D is applied to the common line 18.
output to a.

By the way, the signal output to the common line 18a has a wired OR with the signal output to the other common line 18a. Therefore, the signal voltage of another common line 18a not including the selected pre-sense amplifier 11 will be considered. In this case, in FIG. 4, all the voltage input to the base of the transistor Q ₇₁ to Q ₇₄ is -2.0
v. Now, assuming that the voltage drop of the current source 16a is 0.4 V or more, the emitter potential (15a) becomes -2.9, which is lower than the base-emitter voltage V _BE = 0.8 V of the transistors Q _{71 to} Q _74. Only 0.7v. Therefore, it sinks current corresponding to a current source 16a minute transistor Q ₇₁ to Q _74, the voltage of the common line 15a becomes -2.9V. Even if the voltage is similarly boosted by the shift-up circuit 17, the voltage is only -1.3V, so that the signal voltage of the common line 18a of the selected pre-sense amplifier 11 is -1.
The relationship sufficiently lower than 0v can be maintained. In other words, the voltage can be boosted while maintaining the relative relationship between the input-side voltage levels.
These are wired OR via an emitter follower 19
, Only the signal on the common line 18a of the selected pre-sense amplifier 11 can be output.

On the other hand, if a current switch is used in the shift-up circuit, the relative relationship between the voltage levels of the input signals is broken, and even if the wired OR is employed, the output signal of the selected pre-sense amplifier is selected and output. The problem of being unable to do so will be described with reference to FIG.
FIG. 5 shows an output signal obtained by taking a wired OR of the output signals of the four memory blocks shown in FIG. 4 via the emitter follower group 14-1 and an output signal of the other four memory blocks. Emitter follower group 14
2 shows an example of taking a wired OR with an output signal obtained by taking a wired OR via -2. Instead of the up-shifting circuit 17 as shown, to connect the collectors of the pair of bipolar transistors Q _20, Q _21, respectively via a resistor R _3, R ₄ Vcc, their emitters via a current source 27 Vee connected to, and applies a current switch 17 '- 1,17'-2, outputs the collector of the transistor Q _20. As in the case of FIG. 4, it is assumed that the output signal related to the pre-sense amplifier 11 selected to the base of the transistor Q ₇₁ of the emitter follower group 14-1 is input. In this case, the emitter follower group 14-1
The voltage of the output signal of the common line 15a is -2.0 V, as described above. On the other hand, the voltage of the output signal of the common line 15a of the emitter follower group 14-2 is -2.
7v. These signals are the current switch 17'-
Is input to the base of 1,17'-2, both the voltage of the collector output 18a becomes (Vcc-ΔV _R) v.
Here, [Delta] V _R is the voltage drop across the resistor R _3. That is,
Output 18a of current switch 17'-1, 17'-2
Does not represent the relative relationship between the voltage levels of the input signals, so that the next-stage emitter followers 19-1 and 19-1
No wired OR can be taken via -2.

According to this embodiment, when the current flowing through the diode of the shift-up circuit 17 increases,
An effect such as an increase in the potential of the common line in the preceding stage that becomes an input occurs, and an accurate voltage level of the input signal cannot be maintained. Therefore, the current sources 24a, 24b of the shift-up circuit 17
It is important to set the set current I ₁ of the current source 16a, b to be sufficiently lower than the set current I ₂ of the current sources 16a and 16b of the preceding common line. For example, I ₁ is less than half of I ₂ , preferably 1/6
Set to about. However, the current sources 24a and 24b are connected to the common line 1
8a and 8b serve as a current source for charging the parasitic capacitance.
_Set to ₁ .

As described above, according to this embodiment,
When the outputs of the plurality of pre-sense amplifiers are divided hierarchically and in multiple stages to take a wired OR through the emitter follower, the signal voltage lowered by the emitter follower is boosted by a shift-up circuit composed of a diode. Even when the output signal of the wired OR falls below the operation lower limit voltage of the next or last stage transistor, the sense circuit can be reliably operated.

As a result, the wired OR via the emitter follower can be divided into arbitrary stages, and the parasitic capacitance and the resistance of the wiring can be substantially reduced, so that R
The access time can be shortened by reducing the C delay.

Further, according to the shift-up circuit of the present embodiment, since the voltage can be boosted while maintaining the relative relationship between the levels of the input signals, the wired OR can be employed as it is via the emitter follower. Becomes easier.

Even if the power supply voltage is lowered (for example, 2.0 V) to reduce the power consumption, the data bus wiring can be multi-staged and the access time can be shortened.

Further, by applying the sense circuit of this embodiment, the read access time of the semiconductor memory device can be shortened, and the power supply voltage can be reduced.

(Embodiment 2) FIG. 6 shows the configuration of a sense circuit to which another embodiment of the present invention is applied.

This embodiment is an example of a sense circuit mainly corresponding to a low-voltage power supply. As shown, the plurality of pre-sense amplifiers 11 are divided into a plurality of blocks 50, and the emitter follower outputs of the plurality of pre-sense amplifiers 11 are connected to a common line (common emitter line) 12 for each block, and are pulled to the common line 12. The up circuit 41 and the current source 13 are connected. One main sense amplifier 60 is provided for the plurality of blocks 50.

The pre-sense amplifier 11 has the same configuration as that shown in FIG. The pull-up circuit 41 is controlled by a block selection signal BS (when selected: H, when not selected: L). When the common line 12 is short-circuited to Vcc when not selected, the voltage of the common line 12 is raised to Vcc, and selected. Sometimes the connection to Vcc is released.

The main sense amplifier 60 includes a current switch 61 and shift-up circuits 62a and 62b. The current switch 61 connects the collectors of the pair of bipolar transistors Q ₁₁ and Q ₁₂ to Vcc via the resistors R ₁ and R ₂ , and connects the emitter to Ve via the current source 25.
e, and outputs the collector voltage as an output signal 23 to the output buffer. The shift-up circuit 62
a and b are multi-emitter transistors Q ₃₁ and Q ₃₁ , respectively.
₃₂ collector and base are connected in common, and this is connected to the current source 27
The emitters are connected to Vcc via a and b, respectively, and the respective emitters are connected to the common lines 12a and b of each block 50.

The operation of the embodiment constructed as described above will be described with reference to the voltage level change of each section shown in FIG. The sense circuit handles a pair of complementary signals (H, L), but for the sake of simplicity, the description will be made based on the lower signal L. 3 and 7, the signal L input to the pre-sense amplifier 11 changes the amplitude of the complementary signal (H−L = Vcc) from Vcc.
(Less than 50 mv). The level of the signal L input to the ECL current switch 42 of the pre-sense amplifier 11 becomes a level (Vcc− (1V _BE +50 mv)) shifted down by V _BE (for example, 0.8 V) by the input emitter follower 41. Also, E
The emitter potential of the current switch 42 of CL becomes a level lower by 2 V _BE than Vcc. Now, V _BE = 0.8
v, and the minimum operating voltage of the current source 47 is 0.4 V, the presense amplifier 11 operates at a power supply voltage (Vcc-Vee) of 2.0 V or more.

The output (collector node) of the current switch 42 lowers the level of the signal H by about 0.4 V by the resistance _RH , and further lowers the level of the signal _L by the amplitude (for example, 0.3 V) by RL. That is, the current switch 4
2, the level of the output signal L becomes Vcc-0.7v. The output of the current switch 42 is an output emitter follower 44
, A wired OR is taken by the common line 12.
The level of the signal L on the common line 12 is 1.5 V lower than Vcc.
(= 0.7V + 0.8V) The level is lowered, but since the voltage of 0.5V is applied to the current source 16 of the common line 12, it operates sufficiently.

The common line 12 is independent for each block 50, and the signal L of the common line 12 of the selected block 50 is
Only at a level 1.5 V lower than Vcc,
The signal L on the common line 12 of the unselected block 50 goes to the Vcc level. The signal on the common line 12 of each block 50 is a diode-connected multi-emitter transistor Q ₃₁ , Q
Input to each of ₃₂ emitter nodes.

The potential of the base nodes of the diode-connected multi-emitter transistors Q ₃₁ and Q ₃₂ is shifted up by 1 V _{BE from} the lowest level of the plurality of emitter nodes (ie, the signal level of the common line 12 of the selected block 50). It will be a level that you have. This is because the potential difference between the base node and the other high-level emitter node is turned off at 1 V _BE or less. Block 5 selected in this way
Since the signal of the 0 common line 12 is boosted by 1V _BE , it becomes a level for sufficiently operating the current switch 61, and is amplified by the current switch 61 and output to the output buffer. That is, the input level on the signal H side of the current switch 61 becomes a level lower than Vcc by 0.4 V,
The emitter node of the current switch 61 is at a level 1.2 V lower than Vcc. Therefore, since the voltage of 0.8 V is applied to the current source 25 of the current switch 61, it operates sufficiently.

As described above, according to this embodiment,
A sense circuit that operates sufficiently even when the power supply voltage is about 2.0 V can be realized.

The first embodiment and the second embodiment can be combined.

[0059]

According to the present invention, since the potential can be shifted up while maintaining the relative level of the complementary signal of the common line, the shifted-up signal can be further subjected to a wired OR using an emitter follower. . As a result, the data bus wiring of the sense circuit can be configured in a multi-stage hierarchy, and the RC delay of the wiring can be significantly reduced by dividing the data bus wiring into an arbitrary number of stages.

The combination of a shift-up circuit using a multi-emitter transistor and a pull-up circuit makes it possible to specify or select a directly selected common line. (For example, about 2.0 V) can be realized at the same time.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a sense circuit according to an embodiment of the present invention.

FIG. 2 is an overall configuration diagram of a main part of a semiconductor memory device according to one embodiment of the present invention;

FIG. 3 is a detailed circuit diagram around a memory mat and a pre-sense amplifier.

FIG. 4 is a diagram for explaining the operation of an emitter follower and a shift-up circuit, which are characteristic parts of the embodiment of FIG. 1;

FIG. 5 is a diagram for explaining an operation of a shift-up circuit using a current switch for comparison.

FIG. 6 is a configuration diagram of a sense circuit according to another embodiment of the present invention.

FIG. 7 is a diagram illustrating voltage levels of respective units in the embodiment in FIG. 6;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Presense amplifier 12 1st hierarchy common line 14 1st emitter follower 15 2nd hierarchy common line 16, 16a, b Current source 17 Shift-up circuit 19 2nd emitter follower 20 3rd hierarchy common line 22 Sense amplifier 24, 24a, b the current source 41 the pull-up circuit 61 current switch 62a, b upshift circuit Q _31, Q ₃₂ multi-emitter transistor

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masahiro Iwamura 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Noboru Akiyama 7-1-1, Omikamachi, Hitachi City, Ibaraki Prefecture No. 1 Hitachi, Ltd. Hitachi Research Laboratory (56) References JP-A-63-259891 (JP, A) JP-A-52-33231 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB Name) G11C 11/416 H03K 5/003

Claims (7)

(57) [Claims] 1. A plurality of pre-sense amplifiers provided for each of a plurality of memory cell groups and amplifying and outputting signals read from a plurality of memory cells belonging to each memory cell group; In order to take a wired OR of the signals of the plurality of common lines and a plurality of common lines that are divided into a group of presense amplifiers, and the outputs of the presense amplifiers are commonly connected to each other via an emitter follower for each group of presense amplifiers, and A semiconductor memory device includes a plurality of common lines provided in a plurality of stages and connected between the stages by an emitter follower, and a sense amplifier for amplifying and outputting the output of the last common line. In the sense circuit, between at least one of the plurality of common lines, the N side of the PN junction is connected to the preceding common line, and the P side is connected to the subsequent common line. Is connected to, and the sense circuit of the semiconductor memory device, wherein a P-side inserting the shift-up circuit formed by connecting the high-potential power supply through the first current source. 2. The sense circuit of a semiconductor memory device according to claim 1, wherein said pre-sense amplifier amplifies an input signal by a current switch and outputs the amplified signal via an emitter follower. A base voltage control circuit for switching a signal input to the base of the emitter follower to a voltage sufficiently lower than a normal signal voltage when the selection signal is not selected. . 3. The sense circuit of the semiconductor memory device according to claim 1, wherein a current set value of a first current source of the shift-up circuit is
A second terminal connected between the common line of the preceding stage and a low potential power supply.
A sense circuit for a semiconductor memory device, wherein the value is set to a value smaller than 1/2 of the set current value of the current source. 4. The sense circuit according to claim 1, wherein the PN junction is one of a diode and a diode-connected transistor. circuit. 5. The sense circuit of a semiconductor memory device according to claim 1, wherein said shift-up circuit is provided at a position near a common line on a subsequent stage. . 6. A plurality of pre-sense amplifiers provided for each of a plurality of memory cell groups and amplifying and outputting signals read from a plurality of memory cells belonging to each memory cell group, and a plurality of pre-sense amplifiers comprising a plurality of pre-sense amplifiers. Divided into pre-sense amplifier groups, the outputs of the pre-sense amplifiers were commonly connected via emitter followers for each of the pre-sense amplifier groups, and a plurality of common lines for taking a wired OR, and a wired OR of signals of the plurality of common lines were taken. A sense amplifier for amplifying and outputting a signal, wherein a pull-up circuit is connected to a common line of the pre-sense amplifier group, and the pull-up circuit is connected to a pre-sense circuit belonging to the pre-sense amplifier group. The selection signal indicating that the amplifier includes the memory cell selected by the address is not selected. The common line is connected to a high-voltage power supply, and a shift-up circuit comprising a multi-emitter transistor having a plurality of emitters for boosting a signal voltage is inserted into an input portion of the sense amplifier, and the multi-emitter transistor is inserted. The common line is connected to each of the emitters, the collector and the base are connected in common, connected to a high voltage power supply via a current source, and the base is connected to the input of the sense amplifier. Sense circuit. 7. A semiconductor memory device comprising the sense circuit of the semiconductor memory device according to claim 1.