JP2821963B2 - Stabilized power supply circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stabilized power supply circuit for stabilizing an output voltage by pulse width control and stabilizing an output voltage by a saturable reactor. A master control system that stabilizes the output voltage on the secondary side of the transformer by turning on and off the primary side of the transformer by pulse width control, and uses a saturable reactor for the output voltage on the other secondary side of the transformer There is known a stabilized power supply circuit including a slave control system that stabilizes the power. A dummy load is connected so that the master control system is not loaded. However, since a power loss occurs due to the dummy load, it is required to reduce the power loss.

[0002]

2. Description of the Related Art FIG. 3 is an explanatory view of a conventional example. A switching transistor 45 is connected in series to a primary winding 41 of a transformer 44, and a DC current flowing from a DC power supply 50 to the primary winding 41 is applied to the switching transistor 45. On and off. The first secondary winding 4 of the transformer 44
2 is rectified and smoothed by a rectifying and smoothing circuit including diodes D1 and D2, a capacitor C1 and a choke coil L1. The output voltage of the rectifying and smoothing circuit is compared with a set value by a pulse width control circuit 47, and the ON time width of the switching transistor 45 is controlled so that the output voltage becomes the set value, thereby stabilizing the output voltage. Will be This control system becomes the master control system. RD is a dummy resistor for preventing the master control system from being completely loaded.

A rectifying and smoothing circuit composed of diodes D3 and D4, a capacitor C2 and a choke coil L2 is connected to a second secondary winding 43 of a transformer 44 via a saturable reactor 48, and the output voltage is a resistor. The voltage is divided by R4 and R5 and input to the control terminal of the shunt regulator 49. The shunt regulator 49 performs a constant voltage action. Therefore, when the output voltage becomes higher than the set value, the current flowing through the shunt regulator 49 increases, and accordingly, the base current of the transistor 46 also increases and flows through the transistor 46. The current increases. That is, the saturable reactor 4 flowing through the diode D5
8, the reset current increases, and the output voltage decreases.

[0004] Conversely, when the output voltage becomes lower than the set value, the current flowing through the shunt regulator 49 decreases, so that the base current of the transistor 46 also decreases, and the current flowing through the transistor 46 decreases.
That is, the reset current of the saturable reactor 48 flowing through the diode D5 decreases, and the output voltage increases. Accordingly, the induced voltage of the second secondary winding 43 of the transformer 44 has a value controlled by the master control system on the first secondary winding 42 side, but the saturable reactor 48, the transistor 46, and the shunt regulator 49, diode D
The output voltage is stabilized by the slave control system including 5 and the like.

[0005]

SUMMARY OF THE INVENTION In a conventional stabilized power supply circuit having a master control system based on pulse width control and a slave control system based on a saturable reactor, a configuration in which the steady load current of the master control system is large is used. In this case, when the master control system has no load, the pulse width control circuit 47 controls the switching transistor 45 to have an ON time width that can only compensate for the loss due to the capacitor C1, and this ON time width is extremely large. It becomes narrow. When the ON time width is reduced in this manner, the output voltage of the slave control system decreases due to the dead angle of the saturable reactor 48 of the slave control system. As a result, a low-voltage alarm signal is output from a low-voltage detection circuit (not shown), and the operation of the stabilized power supply circuit is stopped. That is, when no load is connected to the master control system, the power cannot be turned on.

In order to eliminate such a defect, a dummy resistor R
A configuration is adopted in which the resistance value of D is reduced to increase the dummy current, and even when no load is connected, the minimum load current flows so that the ON time width of the switching transistor 45 is maintained at a certain width. ing. It has also been proposed to increase the choke coil L1. However, when the current flowing through the dummy resistor RD is increased, the power loss is increased, so that the efficiency is reduced and a configuration for dissipating heat generated by the power loss is required. Further, enlarging the choke coil L1 causes a disadvantage that the size of the choke coil L1 is increased and the mounting space is increased. SUMMARY OF THE INVENTION It is an object of the present invention to enable a master control system to be started without load and to omit a dummy resistor.

[0007]

Referring to FIG. 1, a stabilized power supply circuit according to the present invention comprises a transformer having a primary winding 1 and at least first and second secondary windings 2 and 3. 4
A switching transistor 5 connected in series to the primary winding 1 and a rectifying / smoothing circuit 6 connected to the first secondary winding 2
A pulse width control circuit 7 for controlling the on-time width of the switching transistor 5 so that the output voltage of the rectifying / smoothing circuit 6 becomes a set value, and a saturable reactor 8 connected to the second secondary winding 3. A reset circuit 1 including a transistor 13, a shunt regulator 14, a diode 15 and the like for supplying a reset current of the saturable reactor 8.
In the stabilized power supply circuit provided with 0, a detection unit 12 for detecting that the on-time width of the switching transistor 5 by the pulse width control circuit 7 has become narrow and the output voltage of the rectifying / smoothing circuit 9 has dropped below a set value. And a bypass circuit 11 for bypassing the saturable reactor 8 by a detection output of the detection unit 12.

[0008]

When the switching transistor controlled by the pulse width control circuit is turned on, a current flows from the DC power supply to the primary winding of the transformer. By controlling the ON time width of the switching transistor 5, the output voltage of the rectifying and smoothing circuit 6 constituting the master control system is stabilized. The output voltage of the rectifying / smoothing circuit 9 constituting the slave control system is controlled by the transistor 13 and the shunt regulator 1.
4. The reset current of the saturable reactor 8 is controlled and stabilized by the reset circuit 10 including the diode 15.

When no load is applied to the master control system, the pulse width control circuit 7 controls the switching transistor 5 so that the on-time width is minimized. In that case, the rectifying and smoothing circuit 9 is controlled by the dead angle of the saturable reactor 8.
Output voltage falls below the set value. This decrease in the output voltage is detected by the detection unit 12 and the bypass circuit 11 is controlled to bypass the saturable reactor 8. Thereby,
The voltage induced in the secondary winding 3 of the transformer 4 is directly applied to the rectifying and smoothing circuit 9 and rectified and smoothed.
Therefore, it is possible to prevent the output voltage from dropping and outputting a low-voltage alarm. Further, since the power supply can be turned on in the no-load state of the master control system, the dummy resistor 16
Can be made relatively large, thereby reducing power loss. Alternatively, the dummy resistor 16 can be omitted.

[0010]

FIG. 2 is an explanatory view of an embodiment of the present invention.
Is a primary winding, 22 and 23 are first and second secondary windings, 24
Is a transformer, 25 is a switching transistor, 26 is a transistor, 27 is a pulse width control circuit, 28 is a saturable reactor, 29 and 30 are shunt regulators, 31
Is a photo bidirectional thyristor constituting a bypass circuit, 32
Is a Zener diode, 33 is a DC power supply, D1 to D5 are diodes, C1 and C2 are capacitors, R1 to R7 are resistors, Rd is a dummy resistor, and L1 and L2 are choke coils.

The diodes D1 and D2 and the choke coil L
1 and the capacitor C1 constitute a rectifying / smoothing circuit on the side of the mactor control system.
The ON time width of the switching transistor 25 is controlled in accordance with the difference. The diodes D3 and D4, the choke coil L2, and the capacitor C2 constitute a rectifying / smoothing circuit on the slave control system side, and the induced voltage of the second secondary winding 23 of the transformer 24 is
The current is rectified and smoothed by a rectifying / smoothing circuit via the saturable reactor 28.

A reset circuit is constituted by the transistor 26, the shunt regulator 29, the resistors R1 to R6, and the diode D5, a detection section is constituted by the resistor R7 and the shunt regulator 30, and a bypass circuit is constituted by the photo bidirectional thyristor 31. Have been. The Zener diode 32 is composed of the resistor R7 and the shunt regulator 3
When the potential at the connection point with zero becomes equal to or higher than the Zener voltage,
A current flows through the photodiode of the photo bidirectional thyristor 31, and the photo bidirectional thyristor 31 is turned on to bypass the saturable reactor.

The operation of stabilizing the output voltage by the master control system and the slave control system is the same as that of the conventional example. However, when the power is turned on without connecting the load to the master control system, as described above, the switching transistor 25 is controlled so as to be the narrowest. As a result, the output voltage of the rectifying / smoothing circuit of the slave control system falls below the set value even if the reset current is reduced.

When the output voltage decreases, the current flowing through the shunt regulator 30 decreases, and the terminal voltage increases. Thereby, the Zener diode 32
Is turned on, the photodiode of the photo bidirectional thyristor 31 emits light, and the photo bidirectional thyristor 31 is turned on, so that the saturable reactor 28 is bypassed. Therefore, the induced voltage of the second secondary winding 23 of the transformer 24 is rectified and smoothed by the rectifying and smoothing circuit composed of the diodes D3 and D4, the choke coil L2 and the capacitor C2. Become closer to That is, even if the no-load start is performed, a low-voltage alarm is not output from a low-voltage detection circuit (not shown). Therefore, the dummy resistor Rd can be omitted.

In the above-described embodiment, a photo bidirectional thyristor 31 is used as a bypass circuit. However, a switching element such as another bidirectional thyristor or a unidirectional turn-off thyristor can be used. In a configuration in which the secondary winding of the transformer 24 is further provided and a stabilized voltage is output by a plurality of slave control systems, a master control system is provided by providing a bypass circuit for each saturable reactor. It is possible to avoid the output of the low-voltage alarm also by the start-up due to no load.

[0016]

As described above, according to the present invention, the bypass circuit 11 for bypassing the saturable reactor 8 of the slave control system is provided, and the output voltage of the slave control system when the master control system is started with no load is provided. At the time of drop, the detection unit 1
2, the bypass circuit 11 is operated to bypass the saturable reactor 8 to prevent the output voltage of the slave control system from lowering, thereby preventing the output of the low-voltage alarm. Even if it is omitted, start-up without load is possible and dummy resistor 1
Even in the case where 6 is provided, there is an advantage that the power loss due to the dummy resistor 16 can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Primary winding 2 1st secondary winding 3 2nd secondary winding 4 Transformer 5 Switching transistor 6 Rectification smoothing circuit 7 Pulse width control circuit 8 Saturable reactor 9 Rectification smoothing circuit 10 Reset circuit 11 Bypass circuit 12 Detection Part 13 Transistor 14 Shunt regulator 15 Diode

Claims (1)

(57) [Claims] 1. A primary winding (1) and at least first and second windings
(4) having secondary windings (2) and (3) of
A switching transistor (5) connected in series to the primary winding (1); a rectifying / smoothing circuit (6) connected to the first secondary winding (2); and the rectifying / smoothing circuit (6). A pulse width control circuit (7) for controlling the ON time width of the switching transistor (5) so that the output voltage of the saturable reactor (3) is connected to the second secondary winding (3). 8), a rectifying / smoothing circuit (9) for rectifying the output via the saturable reactor (8), and the saturable reactor (8) so that the output voltage of the rectifying / smoothing circuit (9) becomes a set value. And a reset circuit including a transistor for supplying a reset current, a shunt regulator and a diode, wherein the pulse width control circuit (7) controls the switching transistor (5). A detection unit (12) for detecting that the output voltage of the rectifying / smoothing circuit (9) has decreased below a set value due to a narrowing of the ON time width, and the saturable reactor (8) based on a detection output of the detection unit (12); And a bypass circuit (11) for bypassing (1).