JP2817689B2 - High-speed integrated simulation method for multiple simulators - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated simulation system in which one simulation model is divided into a plurality of sub-blocks and assigned to a plurality of simulators for performing a simulation.

[0002]

2. Description of the Related Art In a conventional integrated simulation system using a plurality of simulators of this kind, a plurality of simulators are controlled by transmitting and receiving all result data processed for each simulator.

In Japanese Patent Application Laid-Open No. 5-258002, an event-driven simulator for processing different descriptions such as a hardware description language and a gate level circuit description is arbitrarily connected, and various descriptions are mixedly expressed. As a synchronous execution control method for heterogeneous simulations applicable to simulating a circuit description, the conventional synchronous execution control method executes data transmission and reception by inter-process communication, so the execution speed by function calls in the process All the simulators are synchronized at the minimum time unit, so that the synchronization process is wasted at the time when no event occurs. The functions equivalent to data transmission / reception and management are performed by function calls, and the simulator Synchronization Control Method of heterologous simulator comprising realized by integrating in one process has been proposed.

[0004]

The above-described integrated simulation system using a plurality of simulators is as follows.
Since all the simulation data processed for each simulator is transmitted and received between the simulators, a large number of transmissions and receptions between the simulators occur. Of the total simulation time, the time spent for transmitting and receiving the simulation data between multiple simulators Is large, and simulation cannot be performed at high speed.

On the other hand, even in the synchronous execution control method for different types of simulators proposed in the above-mentioned Japanese Patent Application Laid-Open No. 5-258002, the number of transmitted and received simulation data between different types of simulators does not change.

Further, in the conventional method proposed in the above-mentioned Japanese Patent Application Laid-Open No. 5-258002, it is essential that a function corresponding to data transmission / reception and management between simulators is performed by a function call. When integrating an existing simulator, it is necessary to modify the simulator at the source code level, which increases development man-hours and makes it difficult to modify the simulator (for example, when the source code of a logic simulator is unavailable, etc.) If it is not possible to modify it, this conventional method cannot be applied.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above-mentioned problems of the prior art, and it is possible to use a plurality of simulators by making it possible to reduce the transmission and reception of simulation data generated between simulators to a minimum. It is an object of the present invention to provide an integrated simulation method for achieving high speed of integrated simulation.

[0008]

In order to achieve the above object, the present invention provides an integrated simulation in which one simulation model is divided into a plurality of sub-blocks and a simulation is performed using a plurality of simulators corresponding to each sub-block. , It is unnecessary to extract signals that are not logically used in the top block or signals that do not observe simulation results from the interface signals of each sub-block from the top block model in which connection information between the sub-blocks is described. From the signal extracting means and the signal information extracted by the unnecessary signal extracting means, the interface signals of each sub-block which is not logically used in the top block or whose simulation result is not observed are output from each sub-block to the outside. Unnecessary processing A simulation is performed by integrating a plurality of simulations corresponding to each sub-block with the internal processing means and the simulation model processed by the unnecessary signal internal processing means and in which the connection between unnecessary sub-blocks in the top block is deleted. And a high-speed integrated simulation method in a plurality of simulators, comprising:

[0009]

According to the present invention, based on the above structure, a new simulation model is created by removing the extracted unnecessary signal from the interface signal of each sub-block. By performing a simulation using a plurality of simulators corresponding to the above, the number of transmission and reception of simulation data generated between the simulators is reduced, and the speed of the integrated simulation using the plurality of simulators is increased.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

Here, an embodiment of the present invention will be described based on a simulation model as shown in FIG.

Referring to FIG. 2, a behavioral level description sub-block BE using signals A to F as interface signals and a gate level description sub-block GA using signals G to L as interface signals are combined into a top block. And (AG), (BH), (CI), (D-
J) and (EK) connect the signals to each other.

As shown in FIG. 2A, as the specification description of the behavior-level sub-block BE, inputs A, B,
C, outputs D, E, and F are described in the interface description (declaration) column. For these interface signals,
The configuration of the sub-block shown on the left side of FIG. 2A is described at the behavior code level, and more specifically, D <= A +
1 (incrementer adding 1 to input A and output D),
E <= A + B (the output of the adder of inputs A and B is E), F <
= B-C (inputs B and C are subtracters and the output is F).

The syntax in the behavioral level, gate level, and top level circuit description shown in FIG. 2 shows the main part for easy explanation, and it is based on the syntax of a specific hardware description language. Not exactly compliant.

On the other hand, as shown in FIG. 2B, in the sub-block GA of the gate level description, the first and second input terminals registered as a basic unit in a library or the like are output as IN1 and IN2. AND gate (A), OR gate (B), inverter gate (C)
And an inverter (D), and an AND gate (A)
The first input terminal of the OR gate (B) and the first input terminal of the OR gate (B) are connected to the signal J, and the second input terminal of the AND gate (A) and the second input terminal of the OR gate (B) are connected to the signal J. K and the output of the AND gate (A) is the inverter (C)
And the output of the OR gate (B) is connected to the input of the inverter (D) and the signal H, and the output of the inverter (C) is connected to the signal I. And the output of the inverter (D) is the signal L
Connected to.

As shown in FIG. 2C, in the top block, the signal F of the behavior-level description sub-block BE is a signal that is not used logically, and the signal L of the gate-level description sub-block GA is a simulation result. Is not observed.

An example of performing an integrated simulation on such a simulation model using a behavior-level simulator and a gate-level simulator will be described below.

Referring to FIG. 1, sub-block storage means 1
Stores, for example, sub-blocks of behavior level description using the signals (A to F) shown in FIG. 2 as interface signals, and the sub-block storage means 2 stores, for example, (G to L) shown in FIG. ) Stores a sub-block of a gate level description using a signal as an interface signal. The top block storage means 3 stores the sub-blocks stored in the sub-block storage means 1 and the sub-block storage means 2 in respective signals, for example, (AG), (BH) as shown in FIG. ), (C-I), (D-
J) and (EK), a signal (F) not used logically and a signal (L) not observing the simulation result
Indicates a top block model that has not been connected.

The unnecessary signal extracting means 4 is based on the information stored in the sub-block storing means 1, the sub-block storing means 2 and the top-block storing means 3. The sub-block interface signal (F) stored in the sub-block storage unit 2 and the sub-block interface signal (L) stored in the sub-block storage unit 2 that does not observe the simulation result are unnecessary as unnecessary signals. The signal is stored in the signal storage unit 5. FIG. 3 shows each sub-block (behavior level, behavior level,
FIG. 4 is a diagram illustrating an example of an unnecessary signal extracted from a (gate level) interface signal. Preferably, information including correspondence between an unnecessary signal name, a sub-block name, and a type is stored in the unnecessary signal storage unit 5.

The unnecessary signal internal processing means 6 deletes the signal (F) from the interface signal with respect to the behavior level description sub-block stored in the sub-block 1 based on the information stored in the unnecessary signal storage means 5. The model obtained, specifically, as shown in FIG.
Is the description that declares the interface (OUTPUT D, E,
F) (the signal F is deleted from the declaration column of the interface in the circuit description of the behavior level BE sub-block in FIG. Connected subtraction block (BC)
To a global signal (GN
D (ground) is stored in the sub-block storage means 7 (GND <= BC).

For the sub-block GA of the gate level description stored in the sub-block storing means 2, a model in which the signal (L) is deleted from the interface signal, specifically, as shown in FIG. , The signal (L) is deleted from the declaration of the interface, and the output signal (OUT) of the inverter D [NOT] which is output as the signal (L) is a global signal having no logical meaning. Model (JOIN OUT (D), GND) assigned to (GND)
Are stored in the sub-block storage means 8 and unnecessary signals are deleted.
Is stored in the top block storage means 9 (see FIG. 4 (c)).

Based on the top block information stored in the top block storage means 9, the integrated simulation execution means 10 performs the behavior level simulation execution means for the sub-block of the behavior level description stored in the sub-block storage means 7. In step 11, the simulation is integrated and executed by the gate-level simulation executing means 12 for the sub-block described in the gate-level description stored in the sub-block storing means 8, and the simulation result is stored in the simulation result storing means 1.
3 is stored.

According to the above embodiment of the present invention, one simulation model is divided into a plurality of sub-blocks,
When simulating by assigning to multiple simulators, among the interface signals of each sub-block,
A signal that is not logically used in the top block or a signal for which the simulation result is not observed is extracted, and a new simulation model in which the extracted signal is deleted from the interface signal of each sub-block is automatically created. By using a plurality of simulators corresponding to each sub-block to simulate a simple simulation model, the number of transmission and reception of simulation data generated between simulators can be reduced to the minimum necessary. There is a remarkable operation and effect that the speed of the integrated simulation using a plurality of simulators can be increased.

[0025]

As described above, according to the present invention,
A signal that is not logically used in the top block or a signal that does not observe a simulation result is extracted, and a simulation model is created in which the extracted signal is deleted from the interface signal of each sub-block. By performing a simulation on this simulation model using a plurality of simulators corresponding to each sub-block, the number of transmission and reception of simulation data generated between the simulators can be reduced to the minimum necessary. Can speed up the integrated simulation using.

According to the present invention, the simulation model itself is optimized for speeding up the simulation.
No modification to the simulator required by the method proposed in Japanese Patent Publication No. 2 is required at all, and it can be applied to the case where any simulator is used.
It is needless to say that the present invention can be applied to a simulator that adopts a method proposed in Japanese Patent No. 58002 to transmit and receive data by function call.

In the method proposed in Japanese Patent Application Laid-Open No. Hei 5-258002, transmission and reception of data between simulators and management of event occurrence times are performed by function calls. If the simulator is difficult to modify at the source code level due to copyright or the like, this method cannot be applied.

On the other hand, according to the present invention, since the simulation model itself is optimized for speeding up the simulation, the simulator does not need to be modified at all, and even if any simulator is used. Can be applied.

According to the present invention, since the simulation model is optimized for speeding up the simulation, data transmission and reception etc. proposed in the above-mentioned Japanese Patent Application Laid-Open No. 5-258002 are called by a function call. Needless to say, the present invention can be applied to a simulator employing the method performed in the above.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIGS. 2A and 2B are diagrams referred to in the description of an embodiment of the present invention, in which FIG. 2A is a behavior-level sub-block, and FIG.
FIG. 3 is a diagram illustrating an example of a gate-level sub-block, and FIG.

FIG. 3 is a diagram for explaining an embodiment of the present invention, in which each of the sub-blocks (behavior level, gate level) not logically used in the top block in FIG. 2 or not observing a simulation result; FIG. 5 is a diagram illustrating an example of an unnecessary signal from which an interface signal is extracted.

4 is a diagram referred to in the description of an embodiment of the present invention, in which the unnecessary signals shown in FIG. 3 are applied to the sub-block (behavior level), the sub-block (gate level), and the top block in FIG. It is a figure showing an example which processed so that it might not go outside from a subblock.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Sub-block storage means (behavior level) 2 Sub-block storage means (gate level) 3 Top block storage means 4 Unnecessary signal extraction means 5 Unnecessary signal storage means 6 Unnecessary signal internal processing means 7 Sub-block storage means (behavior level) 8 Sub Block storage means (gate level) 9 Top block storage means 10 Integrated simulation execution means 11 Behavior level simulation execution means 12 Gate level simulation execution means 13 Simulation result storage means

Claims (3)

(57) [Claims] 1. A simulation method in which one simulation model is divided into a plurality of sub-blocks and assigned to a plurality of simulators for performing a simulation, wherein a top block model describing connection information between each of the plurality of sub-blocks. Unnecessary signal extracting means for extracting a signal not logically used in the top block and / or an unnecessary signal whose simulation result is not to be observed from among the interface signals of the sub-blocks; Unnecessary signal processing means for removing the signal extracted by the means from the interface signal of each of the sub-blocks so as not to be output from the sub-block to the outside; and the top block created by the unnecessary signal processing means Not used in Signals and / or signals whose simulation results are not to be observed are excluded from the interface signal, and each of the sub-blocks and a top block describing connection information between the sub-blocks of the plurality of sub-blocks. Simulation execution processing means for performing simulation using a plurality of simulators corresponding to respective sub-blocks; and a high-speed integrated simulation method in a plurality of simulators. 2. The unnecessary signal processing means deletes a signal extracted by the unnecessary signal extracting means (referred to as "unnecessary signal") from a description declaring the interface signal, and an output is connected to the unnecessary signal. 2. The high-speed integrated simulation method for a plurality of simulators according to claim 1, wherein the output of the behavior-level circuit block or the output of the gate-level gate circuit is fixed to a signal level that is not logically significant. 3. The signal name of the signal not used in the top block and / or the signal whose simulation result is not observed is connected to the unnecessary signal extracting means as an interface signal. 2. A plurality of sub-blocks according to claim 1, wherein the sub-block name and a signal indicating whether the signal is a signal not used at the top level or a signal not to be observed are stored in a predetermined storage area. High-speed integrated simulation method in the simulator of the future.