JP2817233B2 - Integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit, and more particularly, to an integrated circuit including a differential circuit constituted by a Schottky junction type field effect transistor formed on a gallium arsenide substrate. .

[Conventional technology]

Conventionally, this type of integrated circuit is resistant to manufacturing variations in the threshold voltage of a Schottky junction field effect transistor (hereinafter referred to as MESFET) formed on a gallium arsenide substrate, is excellent in high speed, and uses a single power supply. In many cases, a differential circuit is used because it can be easily realized.

This conventional differential circuit will be described with reference to the drawings.

3 and 4 show a prior art differential inverter circuit (OR
FIG. 3 is a circuit diagram of first and second examples of a (/ NOR circuit).

In FIG. 3, R11 and R22 are load resistors of the differential logic section, and Q11 and Q12 are drive FETs forming a differential pair.

Transistor Q13, diode D11 and transistor Q1
The circuit portion composed of 4 and the diode D12 is a logic level conversion circuit (hereinafter referred to as a level shift circuit).

FETs Q35, Q36, and Q37 are current source FETs that specify the circuit current of each individual function circuit, and resistors R33, R14, and R35 act as source stabilizing resistors in each current source FET, helping to stabilize circuit current. Has a contributing effect.

Normally, the first current terminal 1 is a ground terminal and the second power supply terminal 2 is a ground terminal from the viewpoint of a single power supply in a logic circuit using a GaAs FET or power compatibility with an IC group using silicon. Often set to -4.5V or -5.2V.

An input signal is inputted from an input signal terminal 3, compared with a reference signal potential at a reference signal terminal 4, and subjected to logical processing.
, A negative output (referred to as NOR output) and an in-phase output (referred to as OR output) are output from the terminal 7.

A control voltage that defines the gate voltage of the current source FET group is externally applied to the current control terminal 5.

In the prior art shown in FIG. 3, the logical threshold value of the current source FET may be either positive or negative. In other words, there is an advantage that any type of enhancement or depletion type FET can be used.

FIG. 4 shows a second prior art differential circuit. An advantage of this circuit is that it is not necessary to supply a control voltage from outside.

On the other hand, from a practical point of view, there is a demand for a differential logic circuit to satisfy the following conditions.

(1) The power supply voltage is −5.2 V or less from the viewpoint of power supply voltage compatibility and low power consumption of the IC group using silicon.

(2) In FIGS. 3 and 4, a differential inverter will be described as an example. However, for a high-performance circuit such as a latch circuit, it is necessary to use a cascade circuit also in the differential circuit. Therefore, the logic gate connected to one current source has a multi-stage configuration, and usually needs to be configurable up to two to three stages.

(3) Summing up the above items (1) and (2), it becomes necessary for the FET constituting the differential logic circuit to operate with a small logic amplitude. Specifically, in the case of three stages of vertical product logic gates with a power supply voltage of 5.2 V, it is necessary to operate at a logic amplitude of 0.6 to 1 V.

(4) Therefore, the threshold voltage of the drive FET group constituting the logic gate cannot be set deeply, and specifically, it is almost always set in the range of +0.2 to -0.2V.

[Problems to be solved by the invention]

However, each of the above-described conventional differential circuits has the following problems.

First, in the conventional example shown in FIG. 4, a driving FET and a current source FET are used.
It is formed with a threshold voltage different from that of the group. As described above, even in a differential logic circuit, it is necessary to operate at a logic amplitude of 1 V or less.

Therefore, it is necessary to suppress the variation of the logic threshold value in the drive FET and the current source FET to 0.1 to 0.2 V or less.
Since the two types of FETs are assumed to vary in a non-correlation manner, there is a disadvantage that the threshold voltages of the two types of FETs need to be controlled with high accuracy, and the manufacturing conditions become severe.

On the other hand, in the conventional example of FIG. 3, the driving FET and the current source F
ET can be formed in the same process. However, when integrating by using a plurality of differential inverter circuits shown in FIG. 3, it becomes necessary to supply a current control power supply to all the element circuits, and the layout becomes complicated.

In addition, since the current control voltage and the power supply voltage (the power supply terminal in FIG. 3) are distributed through different paths and different power supply lines in the element differential circuit inside the highly integrated circuit, the wiring resistance of the power supply line is reduced. The influence of the resulting internal potential drop is separately and uncorrelated.

Basically, only a very small amount of current flows from the current control terminal power supply due to the gate bias control of the current source FET group, and therefore the potential drop is small over the entire surface of the integrated circuit. However,
Since a large current almost proportional to the number of gates flows through the power supply line, a potential drop always occurs.

Therefore, the difference between the gate potential of the current source FET Q36 and the potential of the power supply terminal in FIG. 3 can vary depending on the layout of the power supply line, the circuit current, and the degree of integration. The fluctuation of the potential difference directly leads to the fluctuation of the logic amplitude as it is.

As described above, an operation range of about 0.6 to 1.0 V is required as the logic amplitude. Therefore, it is necessary to control the power supply line potential drop amount to, for example, about 0.1 V or less. This imposes great restrictions on the circuit design of the integrated circuit and especially on the pattern layout and the like, and can be a factor of unknown performance variation.

As described above, from a practical point of view, it can be understood that the conventional circuit has disadvantages in controllability in manufacturing and facilitation of pattern design. These disadvantages have a significant effect, especially in the case of high integration.

[Means for solving the problem]

An integrated circuit according to the present invention is an integrated circuit including a Schottky junction type field effect transistor formed on a gallium arsenide substrate, wherein first and second loads each having one end connected to a first power supply terminal. An element, a first drive transistor connected to a gate for receiving an input signal and a drain connected to the other end of the first load element, and a second drive transistor connected to a gate for receiving a reference signal different from the input signal and receiving a drain from the second load element. A second drive transistor connected to the other end of the load element, a constant current source transistor having a source connected to each of the first and second drive transistors, and a drain connected to the common connection point; A differential logic circuit comprising: a source stabilizing element having one end connected to the source of the constant current source transistor and the other end connected to a second power supply terminal;
Alternatively, in an integrated circuit including a level conversion circuit for converting a level of an output signal generated at the other end of the second load element, a threshold value of the constant current source transistor and each of the first and second drive transistors And the level conversion circuit includes a reference potential generation circuit that generates a reference potential that is clamped at a predetermined potential difference with respect to a potential applied to the second power supply terminal, The reference potential is supplied to the gate of the constant current source transistor.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a differential inverter circuit according to a first embodiment of the present invention.

Since the basic functions are the same as those of the conventional example described with reference to FIG. 3, detailed description will be omitted.

The gate electrode of the differential logic section current source FET Q16 is connected to the anodes of the constant voltage generation diodes D13 and D14. The function of the source stabilizing resistor R14 is the same as that of the conventional example, but this embodiment also has a function for adjusting the voltage as described later. Further, diodes Q13 and Q14 for generating a constant voltage are connected in the forward direction between the sources of the level shift circuit current sources FET Q15 and Q17 and the power supply terminal.

 The function of the circuit of this embodiment will be described.

The FETs according to the present embodiment have the threshold voltage of +0.2 to -0.2 V in the same process according to the above-described requirements.
And a relatively shallow value. FET like this
Requires the gate-source voltages of the FETs Q15, Q16, Q17 to be set to +0.2 to + 0.5V.

In this embodiment, the gate electrodes of the FETs Q15 and Q17 are supplied with a potential 0.8V to 1.1V higher than the power supply voltage as a current control voltage.

The forward voltage of the constant voltage generation diodes D13 and D14 is 0.
Since the voltage is about 6 V, the gate-source voltage of the FETs Q15 and Q17 is set to 0.2 to 0.5V. The forward voltage variation of the diode is extremely small, and its anode potential is clamped to the power supply voltage (cathode potential), so that the anode electrode operates as a constant voltage terminal between the power supply terminal.

Further, the source stabilizing resistor R14 is set so that the voltage between both ends thereof is about 0.3V. Therefore, the gate-source voltage of the current source FET Q16 is about 0.3V.

In the circuit of this embodiment, the gate potential of the logic section current source FET Q16 is set to a value clamped to the power supply terminal, and need not be supplied from outside, but is supplied within a single gate. Therefore, as described above, even if a potential drop occurs in the power supply line due to the actual pattern design, a stable operation can be obtained without causing a current variation, that is, a logic amplitude variation in the conventional example.

In the circuit of this embodiment, the level shift circuit current source FE
Although it is necessary to supply the gate potentials of TQ15 and Q17 from the outside, OR and NOR complementary outputs are interlocked at all, and logic amplitude fluctuation does not occur. It is much improved.

In this embodiment, there is an advantage in process reduction that all FETs can be formed in the same process.

Further, since a constant voltage generating diode is inserted into a conventionally existing level shift circuit, power consumption does not newly increase.

Furthermore, since the output voltage of the constant voltage generation diode is linked to the power supply voltage, if a constant voltage generation circuit that is also linked to the power supply voltage is connected to the external current control terminal 5, the effect of improving the resistance to power supply voltage fluctuation is expected. it can.

In the present embodiment, an example is used in which the gate of the FET Q16 is connected to both anode electrodes of the constant voltage generating diodes D13 and D14. Obviously what you get.

FIG. 2 is a circuit diagram of a second embodiment of the present invention. In the present embodiment, the level shift circuit current sources FET Q25, Q27
Is a process different from that of the FETs Q11, Q12, Q13, Q14 and Q16, is set to a deep value of about -1 V to -2 V as a threshold voltage, and their gate electrodes are connected to a power supply terminal.

The basic function of this circuit and the device parameters other than Q25 and Q26 are qualitatively the same as in the first embodiment, and a detailed description thereof will be omitted. FE
Although the gate-source voltage of TQ25 and Q26 is about -0.6 V, the necessary circuit current can be obtained because the threshold voltage is -1 to -2 V as described above.

Also in this circuit, the gate bias of the FET Q16 is clamped at the power supply voltage, the logic amplitude is stabilized, and the high controllability of manufacturing variation for both types of FETs as in the conventional example is eased.

In this embodiment, the number of manufacturing steps is increased as compared with the first embodiment, but there is an advantage that a complete single power supply can be realized in a single gate circuit without requiring any external control potential.

[Effects of the Invention] As described above, according to the present invention, a constant voltage generation diode is added / inserted to a level shift circuit, and a constant voltage clamped to a power supply potential, which is an output of the diode, is applied to the gate of the logic unit current source FET By supplying the bias, it is possible to stabilize the operation of the logic portion of the differential logic circuit without increasing power consumption.

 Specifically, the effects of the present invention are summarized and shown below.

(1) Since the gate bias of the current source FET of the differential logic section can be generated internally from external supply, it is possible to eliminate the adverse effect of the power supply line potential drop due to the circuit design and the actual pattern design which could be a problem in the past. .

(2) Therefore, the constraints on the integrated circuit pattern design are eliminated, and CAD used for customization, standardization, etc.
Suitable for design.

(3) Since all the FETs of the differential circuit logic section can be formed in the same process, fluctuations in the output logic amplitude due to manufacturing process variations are reduced.

(4) Since the gate bias of the current source FET is interlocked with the second power supply potential by being clamped to the forward voltage of the diode, the fluctuation of the constant current value with respect to the fluctuation of the power supply voltage is reduced.

(5) In particular, when the circuit of the second embodiment is used in combination, there is no need for any external control voltage terminal, and there is an advantage that a completely single power supply is achieved and the effect of (4) is realized within a single gate. .

(6) In order to obtain the above effects, no increase in power consumption is particularly required.

As described above, it is considered that the effect of the present invention becomes more remarkable as the logic integrated circuit using the differential circuit has higher function, higher integration, and lower power.

In the description of the embodiments of the present invention, the simplest inverter circuit has been described as an example. However, it is clear that the effects of the present invention can be applied to circuits having higher functions than differential latch circuits. It is.

[Brief description of the drawings]

1 and 2 are circuit diagrams of first and second embodiments of the present invention, and FIGS. 3 and 4 are circuit diagrams of first and second examples of a conventional integrated circuit. 1 ... ground terminal, 2 ... power terminal, 3 ... input terminal, 4
... Reference input terminal, 5 ... Current control terminal, 6 ... NOR output terminal, 7 ... OR output terminal.

Claims (2)

(57) [Claims] 1. An integrated circuit comprising a Schottky junction field effect transistor formed on a gallium arsenide substrate, comprising: first and second load elements each having one end connected to a first power supply terminal; A first driving transistor connected to a gate for receiving an input signal and having a drain connected to the other end of the first load element, and a second load element receiving a reference signal different from the input signal to a gate and receiving a drain A second driving transistor connected to the other end of the first driving transistor, a source of each of the first and second driving transistors, and a constant current source transistor having a drain connected to the common connection point; A differential logic circuit comprising: a source stabilizing element having one end connected to the source of the current source transistor and the other end connected to the second power supply terminal; and the other end of the first or second load element. A level conversion circuit for level-converting the output signal generated in the above, wherein a threshold value of the constant current source transistor is equal to a threshold value of each of the first and second drive transistors, and The level conversion circuit includes a reference potential generation circuit that generates a reference potential that is clamped at a predetermined potential difference with respect to a potential applied to the second power supply terminal, wherein the reference potential is a constant current source transistor. An integrated circuit, which is supplied to a gate. 2. The integrated circuit according to claim 1, wherein said reference potential generating circuit includes a diode having a cathode connected to said second power supply terminal and an anode connected to a gate of said constant current source transistor.