JP2807246B2 - Simulation method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a potential distribution inside a device including a floating potential diffusion layer for evaluating a withstand voltage and the like of a semiconductor device by numerical calculation. A simulation method for determining

(Related Art) The breakdown voltage of a semiconductor device can be calculated by using an ionization integration method or the like, given the potential distribution of the device.
Conventionally, the potential distribution of an element having a floating potential diffusion layer has been obtained by the following two methods.

The first method is a method of solving a basic equation of a semiconductor using Newton's method. In this method, a virtual electrode is placed on a floating layer having a floating potential, and the potential of the electrode is determined so that the current flowing through the electrode becomes zero, thereby obtaining a desired potential distribution. The basic equation of a semiconductor is
It looks like this:

Where q is the elementary charge, p is the hole density, n is the electron density,
ψ is the potential, Dp is the diffusion constant of holes, Dn is the diffusion constant of electrons,
μp is the hole mobility, μn is the electron mobility, Nd is the donor impurity concentration, Na is the acceptor impurity concentration, ε is the dielectric constant of the semiconductor, Gp is the hole generation rate per unit time, and Gn is the same electron. Up is the hole annihilation rate per unit time, Un is the electron annihilation rate, Is the hole current density vector, Is the electron current density vector.

However, in the first method, the amount of calculation per Newton iteration is large, and the convergence is worse than when Poisson's equation is solved, and it is difficult to predict a virtually given electrode potential. There is a problem that the CPU time of the computer becomes longer as a result of having to find it by trial and error. In the calculation of a semiconductor device having a plurality of layers of floating potentials, these problems become more remarkable, and it is practically impossible to obtain the potential distribution by this method. If the floating potential layer is depleted near the virtual electrode, a different value from the actual value is calculated because the calculation indicates that depletion does not occur near the virtual electrode. is there. Even if this problem could be avoided, the convergence would be significantly worse.

The second method is to solve only Poisson's equation to obtain a potential distribution, and is proposed by, for example, MSAdler (MSAdier et al “Theory and Breakdown”).
Voltage for Planear Device with a Single Field-Li
In this method, the pseudo-Fermi potential of the majority carrier in the floating layer is given as follows: That is, the layer having the floating potential is given by the following formula: "mitting Ring" IEEE Trans. ED-24, No. 2, pp 107 (1977). In the case of the p-type, the pseudo-Fermi potential φp of the hole is equal to the minimum value of the potential at the boundary in the semiconductor of the layer of the floating potential. The pseudo-Fermi potential φn is given so as to coincide with the maximum value of the potential of the floating potential at the boundary between the layers.This method is simpler than the first method, but the floating layer is depleted to some extent. In such a case, or when a layer having a floating potential is formed due to the expansion of the depletion layer, the actual pseudo-Fermi potential greatly deviates from the above-described maximum value or minimum value, causing inconvenience.

FIG. 11 shows an example in which such an inconvenience occurs. The figure shows the main structure of the high breakdown voltage planar diode and the potential distribution on the surface of the silicon layer at the time of reverse bias. A p ⁺ -type layer 2 and a p ^-- type layer 3 are formed as an anode layer on the surface of a high-resistance n ⁻ -type silicon layer 1, and an anode electrode 5 is in contact with this. A cathode electrode 6 is formed on the back surface of the n ⁻ type layer 1 via an n ⁺ type layer. Around the anode layer, a floating potential p ^- type layer 4 used as a guard ring is formed at a predetermined distance. In order to evaluate the breakdown voltage when a large reverse bias is applied to this diode, it is necessary to obtain the floating potential of the p ⁻ -type layer 4. Now, it is assumed that the p-type region is depleted except for the neutral regions 7 and 8 shown by oblique lines. At this time, the quasi-Fermi potential of the neutral region 8 of the p ⁻ -type layer 4 is φp0, but according to the above-described second method, the point 9 where the potential is minimized on the boundary of the p ⁻ -type layer 4
Is obtained as a pseudo-Fermi potential.

(Problems to be Solved by the Invention) As described above, it is not easy to obtain the pseudo-Fermi potential of a layer having a floating potential in the conventional method of simulating a semiconductor device, particularly when the layer having a floating potential is depleted. Has a problem that an accurate potential distribution cannot be obtained.

The present invention has been made in view of such a point, and provides a simulation method that can easily and accurately obtain the pseudo-Fermi potential of a floating diffusion layer using only Poisson's equation. Aim.

[Constitution of the Invention] (Means for Solving the Problems) In the method of the present invention, the potential distribution of a semiconductor element including a floating layer of a floating potential is determined without using a current equation or a continuous equation. The pseudo-Fermi potential and the potential distribution of the layer of the floating potential are determined by simultaneously solving the relational expression between the saddle point or a feature point equivalent thereto and the floating potential with Poisson's equation.

More specifically, the trial value φf of the pseudo-Fermi potential of the floating layer of the floating potential is given to solve the Poisson equation, and the potential の_M of the saddle point of the potential distribution or a feature point equivalent thereto is obtained from the obtained potential distribution. , this potential [psi _M and trial value φf it is determined whether a predetermined relationship equation, solving the equation again Poisson correct the trial value φf if not satisfy the predetermined relationship, the process is called The process is repeatedly performed until the predetermined relationship is satisfied.

(Operation) According to the present invention, only Poisson's equation is solved without using the equation of current or the equation of continuity. Therefore, the amount of calculation per Newton iteration is small, and the convergence is improved. In addition, since the pseudo-Fermi potential of the floating potential layer is automatically obtained, the number of trials is small, and the calculation time is greatly reduced. Calculation of the potential distribution of a semiconductor element having a plurality of floating layers is also possible. In addition, even when the floating potential layer is depleted, an accurate potential distribution can be obtained without deteriorating the convergence.

(Example) Hereinafter, the details of the present invention will be described.

Generally, the internal potential distribution ψ of a semiconductor element is obtained by solving the following Poisson's equation (1).

div (ε · gradψ) = − q (pn + Nd−Na) (1) The hole density p and the electron density n are calculated by using the corresponding pseudo-Fermi potentials φp and φn in the following equations (2) and (3), respectively. ).

p = ni · exp [q (φ−φ) / kT] (2) n = ni · exp [q (φ−φn) / kT] (3) where ni is the carrier density of the intrinsic semiconductor. , K are Boltzmann's constants.

In general, when a reverse bias is applied to the pn junction of a semiconductor element, the pseudo-Fermi potentials φp and φn are regarded as constant in the region, and the values are given by the majority carrier side electrode potential, respectively, to obtain (1), ( By solving the equations (2) and (3), the potential distribution inside the element can be obtained. However, if there is a floating layer having a floating potential, the pseudo-Fermi potential there is not fixed, so this method cannot be used as it is. Therefore, in the present invention, the following method is used for determining the quasi-Fermi potential of majority carriers in a floating layer when the layer has a floating potential from the state of the potential distribution.

For convenience of explanation, the element model shown in FIG. 2 is considered assuming that the floating layer is a p-type diffusion layer. That is, the p-type layer 12 is formed on the surface of the n-type semiconductor layer 11, the electrode 13 is provided on the p-type layer 12, and the electrode 14 is also provided on the back surface of the n-type semiconductor layer 11. A p-type layer 15 that is not connected to an electrode is buried inside the n-type semiconductor layer 11. The electrode 13 and the ground potential, and a reverse bias between the p-type layer 12 and the n-type layer 11 gives V _R to the electrode 14 is applied. The quasi-Fermi potential in the region other than the floating p-type layer 15 is given as follows by ignoring minority carriers.

.phi.p = V _R potential at (n-type layer region of 11) φn = 0 (region of the p-type layer 12) p-type layer within 15 is not fixed, again quasi-Fermi potential .phi.p considers constant, .phi.f this Expressed by
In order to determine the pseudo-Fermi potential φf, the following two cases are required.

(I) a depletion layer formed by a pn junction between the p-type layer 12 and the n-type layer 11,
When the depletion layers formed by the pn junction between the p-type layer 15 and the n-type layer 11 do not interfere with each other.

(II) a depletion layer formed by a pn junction between the p-type layer 12 and the n-type layer 11,
When the depletion layers due to the pn junction between the p-type layer 15 and the n-type layer 11 interfere with each other.

When (I) is, when _{φf = V R ... (4)} (II) is .phi.f is consistent with the value of potential feature points equivalent to saddle point or a potential distribution [psi.

In the case of (I), there is no problem because the potential of the p-type layer 15 matches the potential of the n-type layer 11. How to set the pseudo Fermi potential φf in the case of (II) will be described in detail below.

Generally, in a pn junction, the reverse current is almost zero, and a large current flows in the forward direction with a slight bias. In the device model of FIG. 2, considering the withstand voltage when a reverse bias is applied between the p-type layer 12 and the n-type layer 11, the p-type layer 15 having a floating potential is considered.
Considering the moment when a current starts to flow through the pn junction between the p-type layer 15 and the n-type layer 11 by acting as a guard ring, most of the pn junction is reverse-biased and one point is forward-biased. This forward biased point is defined as F, and a curve AB of (hole) current passing through this point F is assumed as shown in FIG. At this time, the potential distribution on the curve AB is as shown in FIG. Assuming that the point on the curve AB where the potential ψ becomes maximum is M and the maximum value is _ＭM , the boundary condition at which the forward bias current starts to flow is that the pseudo Fermi potential φp of the p-type layer 15 is φp =
_Ｍ It becomes _M. In the present invention, this relation is generalized, and the following relational expression is introduced.

φf = ψ _M + α (5) Here, α is a correction term and is usually set to 0.

Introducing such a relational expression (5), when calculating the withstand voltage, iteratively solving Poisson's equation so as to satisfy the relational expression (5) while giving a trial value of φf.

Up to this point, one point of the pn junction between the p-type layer 15 and the n-type layer 11 has a forward bias, and the current curve AB including that point has been considered. The characteristic point M indicating the maximum value of the potential distribution there is considered. Is set according to the following conditions. That is, in the general element model, the place where the forward current starts to flow as described above (curve A
B) is not always known. Therefore, the characteristic point M of the potential distribution is defined by the following condition (a) or (b), and the maximum value potential _ＭM thereat is given.

(A) If there is a saddle point in the potential distribution,
And For example, in the element model of FIG. 2, the potential distribution in the plane of FIG. 2 at the time of reverse bias is represented as shown in FIG. The place where the forward current starts flowing between the p-type layer 15 and the n-type layer 11 is the saddle point M in the potential distribution in FIG.

(B) When the layer of the floating potential is on the boundary of the semiconductor region, a point on the boundary that satisfies the following condition is defined as the feature point M.

∂ψ / ∂n <0, ∂ψ / ∂σ = 0, ∂ 2 ψ / ∂σ 2 <0 where, ∂ / ∂n is an outward normal derivative of the boundary, ∂
/ ∂σ and ∂ ² / ∂σ ² are 1 in the tangential direction of the boundary.
Represents the first and second derivatives. This is, for example, the case where the p-type layer 15 is located on the surface of the n-type layer (that is, the Si / SiO ₂ interface) along with the p-type layer 12 in the device model of FIG. ₂ , and the potential distribution at that time is shown in FIG. Therefore, the point corresponding to the saddle point in (a) is a point M on the boundary of the n-type layer and satisfying the above equation.

In actual numerical calculations, the above (I) and (II)
The conditional expressions (4) and (5) in the case of
The following relational expression (6) is used.

_{φf = min (ψ M + α} , V R) ... (6) the aforementioned Poisson equation this equation (6) (1)
By simultaneously solving (2) and (3), the potential φf of the floating potential layer is obtained. Specifically, as shown in FIG. 1, a trial value of the pseudo-Fermi potential φf of the floating layer is first given together with the device parameters, and Poisson's equation (1)
(2) and (3) are solved, and the potential ψ at the saddle point position or a characteristic point position equivalent thereto is obtained from the potential distribution obtained by this.
_{Find M.} Given trial value φf and determined potential ψ _M
Whether or not satisfies the above-mentioned relational expression (6) is set as a condition for convergence determination. .phi.f is _{min (ψ M + α, V} R) is greater than the revised downward .phi.f, if small reversed revised given trial value of the new .phi.f, solving the equation again Poisson process is called Is repeatedly performed until the relational expression (6) is satisfied.

In the above description, it is assumed that the floating potential of the p-type layer pf is not depleted. However, even in the case of depletion, the range in which the potential φf is defined is defined as the region of the p-type layer pf where the carrier density is ni or more. By doing so, the calculation can be similarly performed.

The fact that the method of the present invention has no problem in accuracy as compared with the conventional method (first method) will be described below in the case where it is applied to some element structures. In the conventional method, in the case where the depletion layer may extend to the virtual electrode, the boundary condition at the electrode is given by the pseudo Fermi potential. In other words, solving the equation of the continuous and Poisson's equation is in the semiconductor region, virtual on electrodes, .phi.n, expression of two of Poisson given in electrode potential V _F equations and the following φp p = ni · exp [ q (V _F −ψ) / kT] n = ni · exp [q (ψ−V _F ) / kT]. Thereby, it is possible to prevent a boundary condition at an electrode which does not exist originally from limiting the carrier density around the electrode.

Four types of element models were compared, and the results are shown below.

For a planar diode with a general card ring structure. The calculation results are shown in FIG. 7 (a), and the element structure and element parameters are shown in FIG. 7 (b).

The case where the impurity concentration of the p-type layer 15 as the guard ring is lower. The calculation results are shown in FIG. 8 (a), and the device structure and device parameters are shown in FIG. 8 (b).

For a high voltage planar diode with a withstand voltage of about 1000V. The calculation results are shown in FIG. 9 (a), and the device structure and device parameters are shown in FIG. 9 (b).

P-type layer which is a guard ring layer in the above
15 is buried in the n-type layer 11 (the model in FIG. 2), that is, where it is not known where the forward current from the p-type layer 15 of the floating potential flows. The calculation results are shown in FIG. 10 (a), and the device structure and device parameters are shown in FIG. 10 (b).

As is clear from the above calculation results, the results obtained by the method of the present invention are almost the same as those obtained by the first conventional method, and thus the potential can be obtained with high accuracy. In the method of the present invention, the amount of calculation per Newton iteration is 1/3 to 1/9 as compared with the conventional method, and the convergence is greatly improved. In addition, since it is automatically determined by the pseudo-Fermi potential of the layer of the floating potential, the number of trials is small, and as a result, the calculation time is greatly reduced. According to the present invention, it is possible to calculate an element having a plurality of floating layers. The present invention can also be applied to a case where a layer having a floating potential is depleted or a layer having a floating potential is formed due to expansion of a depletion layer, and the inconvenience of the second conventional method can be solved. .

[Effects of the Invention] As described above, according to the present invention, a new relational expression is introduced and a Poisson equation is simultaneously solved to solve the relational expression, whereby the diffusion layer of a semiconductor element having a floating potential diffusion layer is obtained. The potential can be easily and accurately obtained by numerical calculation even when the potential is depleted.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic algorithm of numerical calculation according to the present invention, FIG. 2 is a diagram showing an element structure for explaining an embodiment of the present invention, and FIG. FIG. 4 is a diagram showing a curve along the directional current, FIG. 4 is a diagram showing a potential distribution on the curve, and FIG. 5 is a point showing a maximum value of the potential distribution on the curve is a saddle point of the potential distribution in the semiconductor region. FIG. 6 is a diagram showing an example of a potential distribution, and FIG. 6 is a diagram showing an example of a potential distribution in which a point showing a maximum value is at the boundary of the semiconductor region. FIGS. 7 (a) and 7 (b) show specific calculations for a certain element structure. FIGS. 8 (a) and 8 (b) are diagrams showing results and their element structures, and FIGS.
FIGS. 10A and 10B are diagrams showing calculation results for still another element structure and their element structures, and FIGS. 10A and 10B are diagrams showing calculation results for still another element structure and their element structures. No.
FIG. 11 is a diagram for explaining a problem with the conventional method. 11 ... n-type layer, 12 ... p-type layer, 13, 14 ... electrode, 15 ...
P-type layer with floating potential.

Claims (2)

(57) [Claims] When determining a potential distribution inside a semiconductor device including a floating layer having a floating potential, a maximum value ψ _M of a potential distribution along a forward bias current of a pn junction formed by the diffusion layer and a maximum value of the diffusion layer. Relational expression φ _f = ψ _M + with pseudo-Fermi potential φ _f
alpha (where, alpha is the correction term) was introduced, the simulation method of a semiconductor device characterized by solving the Poisson's equation to satisfy the relational expression while giving trial value of the phi _f iteratively. 2. A method for determining a potential distribution inside a semiconductor device including a diffusion layer having a floating potential, by applying a trial value φ _f of a pseudo-Fermi potential of the diffusion layer, solving Poisson's equation, and determining a potential from the obtained potential distribution. The saddle point position M of the distribution, or if the diffusion layer is on a boundary region, on the boundary, ∂
ψ / ∂n <0, ∂ψ / ∂σ = 0, ∂ ² ψ / ∂σ ² <0
(However, ∂ / ∂n is the derivative of the boundary in the outward normal direction, ∂ / ∂n
∂σ and ∂ ² / ∂σ ² represent the first and second order derivatives in the tangential direction of the boundary, respectively). The potential _Ｍ M of the feature point _M is obtained, and the obtained potential _{Ｍ M} and the trial value φ _f are obtained. Relational expression φ
_{f = min (ψ M + α} , V R) ( where, alpha is the correction term, V _R is the reverse bias voltage applied to the device) or not satisfied, said when not satisfy the relation Trial value φ _f
, And solve Poisson's equation again,
A method of simulating a semiconductor device, wherein the method is repeatedly performed until the relational expression is satisfied.