JP2806544B2 - Redundant bit elimination method for facsimile signal - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a facsimile signal redundant bit elimination method for eliminating redundant bits added to a facsimile signal.

2. Description of the Related Art In a facsimile signal, "0" is 3 immediately before an EOL signal.
The bits up to the bit are part of the MH code signal or the fill bit, and “0” of 4 bits or more is considered as the fill bit. Therefore, from the 15th “0” following the “1” immediately before the EOL signal, “0” to “0” immediately before the “1” of the EOL signal
Is considered to be the least fill bit added to this line.

Therefore, when "0" s continue, the fill bit can be removed by removing "0" until 15 or more "1" s appear.

Thus, the fill bit in the facsimile signal is
Normally, “0” is inserted, but in a G3 terminal, a terminal that adds white 0 + black 0 as redundant bits cannot be removed by the conventional method and is processed.

Problems to be Solved by the Invention According to the conventional method described above, it is possible to remove only when the fill bit is inserted as "0", and it is not removed at a terminal or the like to which white 0 + black 0 are added. And the signal amount is increased.

The present invention has been made in view of the above-mentioned conventional circumstances, and accordingly, an object of the present invention is to eliminate the above-mentioned disadvantages inherent in the above-mentioned conventional technology, to clarify the boundary between the encoded code and the fill bit, To provide a new facsimile signal redundant bit elimination method that can eliminate all redundant bits added immediately after EOL even when a terminal that adds white 0 + black 0 as redundant bits is used. is there.

Means for Solving the Problems In order to achieve the above object, a method for removing redundant bits of a facsimile signal according to the present invention uses an original image decoded while decoding an MH-coded facsimile signal input in synchronization with a reception clock. One-line end detecting means for counting the number of dots on the pattern and forcibly converting and outputting the final MH-coded facsimile signal at the time of reaching one line to "1";
EO is activated by the "1" signal of the line end detecting means,
The redundant bits of white 0 + black 0 added immediately after L are detected,
A redundant bit detecting means for stopping the receiving clock while the white 0 + black 0 redundant bits continue and thinning out the receiving clock corresponding to the redundant bits.

EXAMPLES Next, the present invention will be described with reference to a preferred embodiment thereof in the first embodiment.
This will be specifically described with reference to FIG. 2 and FIG.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes one-line end detecting means, 2 denotes a counter circuit, and 3 denotes a 5-input NAND circuit (3-input NA).
4 is an inverter circuit, 5 is a 2-input AND circuit, 6 is a 2-input OR circuit, and 7 is a means for detecting a redundant bit.

Referring to FIG. 1, the one-line end detection circuit 1
The encoded image signal is decoded to detect the end of the specified one line by the number of dots in the decoded pattern, and the last bit of the MH encoded code of all the decoded is forcibly fixed to "1". For this reason, the bits subsequent to the last bit are the fill bit and the EOL signal. The one-line end detection circuit 1 decodes the MH-coded image signal in real time. For example, in the case of A4 size, one line is 1728 bits. Has a function. The redundant bit detecting means 7 is a means for detecting a redundant bit, white 0 → 00110101 + black 0 → 0000110111, immediately after the MH-encoded EOL. The portion indicated by reference numeral 9 in FIG. 1 is connected to the portion denoted by the same reference numeral 9 in FIG. In FIG. 2, 10 is a counter circuit, 11 is an inverter circuit, 12
Is a two-input NAND circuit.

Referring to FIG. 2, if the data whose redundant bits are detected by the AND circuit 5 in FIG. 1 is 18 bits, the counter circuit 10 counts 18 times. Then, as long as the redundant fill bit continues, the counter circuit 10 continues counting.

Therefore, the output of the NAND circuit 12 remains "0", and at that time, the clock CLK1 is masked, and no clock is output for the redundant fill bit, and the redundant bit is removed.

Effect of the Invention As described above, according to the present invention, an effect is obtained in which all fill bits of a facsimile signal to which a redundant bit immediately after EOL detection is added can be removed.

[Brief description of the drawings]

FIGS. 1 and 2 are block diagrams showing an embodiment of a facsimile signal fill bit removal system according to the present invention. 1 ... 1 line detection circuit, 2,10 ... Counter circuit, 3 ...
... 5 input NAND circuits (3 input NAND circuits x 2), 4,11 ... inverter circuits, 5 ... 2 input AND circuits, 6 ... 2 input ORs
Circuit, 7 ... Redundant bit detection circuit, 8,12 ... 2 input NAND
Circuit 9, connection between FIG. 1 and FIG. 2, 13 clock mask signal in the present invention

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Tetsuya Fukuda 5-33-1, Shiba, Minato-ku, Tokyo NEC Corporation (72) Inventor Yoshio Yokoze 5-7-15 Shiba, Minato-ku, Tokyo NEC Inside Telecom System Co., Ltd. (72) Inventor Takeo Komiya 3-20-4 Nishi-Shimbashi, Minato-ku, Tokyo Japan Electric Engineering Co., Ltd. (58) Field surveyed (Int. Cl. ⁶ , DB name) H04N 1/41 -1/419

Claims (1)

(57) [Claims] The present invention decodes an MH-encoded facsimile signal input in synchronization with a reception clock, counts the number of dots on a decoded original picture pattern, and counts the number of dots on one line.
One-line end detecting means for forcibly converting the coded facsimile signal to "1" and outputting the signal, and white 0 + black 0 added immediately after EOL activated by the "1" signal of the one-line end detecting means. A redundant bit detecting means for detecting a redundant bit and stopping a received clock while the white 0 + black 0 redundant bit continues to thin out a received clock corresponding to the redundant bit. .