JP2806245B2 - Derivation method of wiring equivalent circuit - Google Patents

Derivation method of wiring equivalent circuit

Info

Publication number
JP2806245B2
JP2806245B2 JP6025831A JP2583194A JP2806245B2 JP 2806245 B2 JP2806245 B2 JP 2806245B2 JP 6025831 A JP6025831 A JP 6025831A JP 2583194 A JP2583194 A JP 2583194A JP 2806245 B2 JP2806245 B2 JP 2806245B2
Authority
JP
Japan
Prior art keywords
wiring
equivalent circuit
deriving
inductor
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP6025831A
Other languages
Japanese (ja)
Other versions
JPH07234884A (en
Inventor
宗司 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6025831A priority Critical patent/JP2806245B2/en
Publication of JPH07234884A publication Critical patent/JPH07234884A/en
Application granted granted Critical
Publication of JP2806245B2 publication Critical patent/JP2806245B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0005Apparatus or processes for manufacturing printed circuits for designing circuits by computer

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、配線の等価回路を導出
する方式に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for deriving an equivalent circuit of a wiring.

【0002】[0002]

【従来の技術】トランジスタ等の能動素子の高速化にと
もなって、配線を伝搬する信号の高周波成分が増大し、
配線を損失のある伝送線路として扱うばかりでなく、そ
の損失に周波数依存性をも考慮する必要が出始めてい
る。損失のある伝送線路を解析する手法の一つに、等価
回路を構築して解析を進める方法がある(CHU−SU
NYEN,et.al.,Proc. of the
IEEE,Vol.70,No.7,pp.750−7
59,July 1982、VIJAI K.TRIP
ATHI,et.al.,IEEE Trans.on
Microwave Theory and Tec
huniques,Vol.36,No.2,pp.2
56−262,February 1988)。その等
価回路を構築する手段として、有限要素解析により三次
元的に電磁場解析を行い電流密度分布を計算した後、合
わせ込みにより等価回路を導くという方法がある。(U
TTAM GHOSHAL,et.al.,Proc.
4th IEEE VLSIMultilevel I
nterconnection Conf.,pp.2
65−272,June 1987、CLAUDE H
ILBERT,et.al.,Proc.NEPCON
West,pp.1391−1403,1990)。
しかしこの方法では、電磁場解析及び合わせ込みの作業
に多大の労力と計算時間がかかってしまい、配線長、配
線幅、配線の膜厚、配線の抵抗率や絶縁体の膜厚や誘電
率等のパラメータのさまざまな組み合わせに対し毎回計
算を行っていては、膨大な解析時間がかかってしまうと
いう問題がある。
2. Description of the Related Art With the increase in the speed of active elements such as transistors, high-frequency components of signals transmitted through wirings increase.
In addition to treating the wiring as a lossy transmission line, it has become necessary to consider the frequency dependence of the loss. One method of analyzing a lossy transmission line is to construct an equivalent circuit and proceed with the analysis (CHU-SU
NYEN, et. al. Proc. of the
IEEE, Vol. 70, no. 7, pp. 750-7
59, July 1982, VIJA K. TRIP
ATHI, et. al. , IEEE Trans. on
Microwave Theory and Tec
huniques, Vol. 36, no. 2, pp. 2
56-262, February 1988). As a means for constructing the equivalent circuit, there is a method in which a three-dimensional electromagnetic field analysis is performed by finite element analysis to calculate a current density distribution, and then an equivalent circuit is derived by fitting. (U
TTAM GHOSHAL, et. al. Proc.
4th IEEE VLSIM Multilevel I
interconnection Conf. Pp. 2
65-272, June 1987, CLAUDE H
ILBERT, et. al. Proc. NEPCON
West, pp. 1391-1403, 1990).
However, this method requires a great deal of labor and calculation time for the electromagnetic field analysis and alignment work, and the wiring length, wiring width, wiring thickness, wiring resistivity, insulator thickness and dielectric constant, etc. If the calculation is performed every time for various combinations of parameters, there is a problem that it takes an enormous amount of analysis time.

【0003】[0003]

【発明が解決しようとする課題】本発明は、配線の等価
回路を配線パターンのパラメータのから簡単に導出する
ことを目的とするものである。
SUMMARY OF THE INVENTION An object of the present invention is to easily derive an equivalent circuit of a wiring from parameters of a wiring pattern.

【0004】[0004]

【課題を解決するための手段】本発明においては、配線
の等価回路を、抵抗素子およびインダクターが並列に結
合されたもの、及び非損失の伝送線路等が複数個直列に
接続されたはしご段構造の回路網によって表現する方法
を取る。すなわち、配線の膜厚が表皮効果によるスキン
デプスと等しくなるような周波数の等比数列を求め、そ
れらの平方根に比例した値からインダクターの値の組を
計算する。
According to the present invention, an equivalent circuit of a wiring has a ladder stage structure in which a resistance element and an inductor are connected in parallel, and a plurality of lossless transmission lines and the like are connected in series. Take the method of expressing by a network. That is, a geometric progression of frequencies at which the film thickness of the wiring becomes equal to the skin depth due to the skin effect is obtained, and a set of inductor values is calculated from a value proportional to their square root.

【0005】さらに、それに並列に接続される抵抗値を
周波数及びインダクターの値の積から計算することによ
って、効率よく等価回路を導出することを特徴とする。
以下にその具体的な計算方法を説明する。
Further, the invention is characterized in that an equivalent circuit is efficiently derived by calculating a resistance value connected in parallel thereto from a product of a frequency and an inductor value.
The specific calculation method will be described below.

【0006】まず、モデリングする配線を何分割するか
を定める。細かく分割すればするほどより正確に特性を
表現できるが、その分計算時間も長くなる。一般的にそ
の目安は分割した後の配線の長さが分布定数線路的な扱
いを必要としない程度とされる。信号の伝搬速度をv、
入力波の立ち上がり時間をTr 、信号伝搬遅延をTD
配線長を1、分割数をMとすると、まず、分布定数線路
的な扱いを必要としないためには、式1が成立しなけれ
ばならない。
First, how many divisions of the wiring to be modeled
Is determined. The finer the division, the more accurate the characteristics
It can be expressed, but the calculation time becomes longer. Generally,
The rule of thumb is that the length of the wiring after splitting is
Is not necessary. Let the propagation speed of the signal be v,
The rise time of the input wave is TrAnd the signal propagation delay is TD ,
Assuming that the wiring length is 1 and the number of divisions is M, first, a distributed constant line
Equation 1 must be satisfied in order not to require
Must.

【0007】 Tr >2.5・TD ・・・式1 TD は式2で表されることから、分割数Mは式2′を満
たす必要がある。
Tr > 2.5 × T D Equation 1 Since T D is represented by Equation 2, the number of divisions M must satisfy Equation 2 ′.

【0008】 TD =1/(v・M) ・・・式2 M>2.5・1/(v・Tr ) ・・・式2′ ここでvはT D = 1 / (v · M) Formula 2 M> 2.5 · 1 / (v · T r ) Formula 2 ′ where v is

【0009】[0009]

【数2】 (Equation 2)

【0010】で求められる値であり、c0 は真空中の光
速、
Where c 0 is the speed of light in a vacuum,

【0011】[0011]

【外1】 [Outside 1]

【0012】は比誘電率、μr は透磁率(磁性体でない
場合は1)である。
Is the relative permittivity, and μ r is the magnetic permeability (1 if not a magnetic material).

【0013】次に損失の周波数依存性を表現するはしご
段回路を求める。まず、一段目の抵抗R0 は配線膜厚t
0 、配線長lM (=l/M)、配線幅W、配線の抵抗率
ρから R0 =ρ・lM /(W・t0 ) ・・・式4 として計算する。次に、Skin−depth(σ)が
ちょうど配線t0 の膜厚と等しくなるような周波数f0
を次式から求める。
Next, a ladder circuit expressing the frequency dependence of the loss is obtained. First, the first-stage resistance R 0 is equal to the wiring film thickness t.
0 , the wiring length l M (= l / M), the wiring width W, and the wiring resistivity ρ are calculated as R 0 = ρ · l M / (W · t 0 ) (Equation 4). Then, Skin-depth (σ) exactly wiring t 0 thickness becomes equal such frequency f 0
Is calculated from the following equation.

【0014】 f0 =ρ/(π・μ・t0 2 ) ・・・式5 等価回路を表現したい周波数領域の最大値fM は、立ち
上がり時間Tr から次式のように計算される。
F 0 = ρ / (π · μ · t 0 2 ) Equation 5 The maximum value f M in the frequency domain where an equivalent circuit is desired to be expressed is calculated from the rise time Tr as follows.

【0015】 fM =2.2/(2・π・Tr ) ・・・式6 fM に対し周波数の等比数列fi を次式7で求める。F M = 2.2 / (2 · π · T r ) Equation 6 A geometric progression f i of frequencies for f M is determined by the following equation 7.

【0016】 fi =4-1+i・f0 /2(i=1,2,・・・,N) ・・・式7 ここでNの値は、式8を満足するような最小の整数であ
る。
F i = 4 −1 + i · f 0/2 (i = 1, 2,..., N) Expression 7 where the value of N is a minimum value that satisfies Expression 8. It is an integer.

【0017】 4-1+N・f0 /2>4・fM ・・・式8 しかる後、各fi を用いて、[0017] 4 -1 + N · f 0/ 2> 4 · f M ··· formula 8 Then, using each of the f i,

【0018】[0018]

【数3】 (Equation 3)

【0019】よりLi を求める。次に、 Ri =2・π・fi ・Li /ai ・・・式10 ai =K・21-i ・・・式11 からRi を計算する。ここでKは配線形状に関係するパ
ラメータである。
[0019] seek from L i. Next, calculate the R i from R i = 2 · π · f i · L i / a i ··· formula 10 a i = K · 2 1 -i ··· formula 11. Here, K is a parameter related to the wiring shape.

【0020】このようにして得られた抵抗とインダクタ
ーの回路網に非損失の伝送線路を接続したものをM個直
列に結合したものが、損失の周波数依存性を考慮した配
線の等価回路となる。表皮効果による損失の増大をこの
ような等価回路で表現しようとするとRi はiが大きく
なるにつれてだんだん大きくなり、逆にLi は小さくな
っていく必要がある。これを等比数列的に表現するため
に周波数の等比数列を計算する。ここで非損失の伝送線
路のパラメータである特性インピーダンスZ0はマイク
ロストリップラインの形状によって異なるが、グランド
層上に誘電体を介して形成されたマイクロストリップラ
インの場合、次式のような近似式を用いればよい。
A circuit obtained by connecting M lossless transmission lines to the resistor and inductor network obtained in this way and connecting them in series becomes an equivalent circuit of wiring in consideration of the frequency dependence of loss. . If an increase in the loss due to the skin effect is to be expressed by such an equivalent circuit, R i must increase gradually as i increases, and conversely, L i must decrease. To express this in a geometric progression, a geometric progression of frequencies is calculated. Here, the characteristic impedance Z 0, which is a parameter of the lossless transmission line, varies depending on the shape of the microstrip line. In the case of a microstrip line formed on a ground layer via a dielectric, an approximate expression such as May be used.

【0021】[0021]

【数4】 (Equation 4)

【0022】 d=0.536・W+0.67・t0 ・・・式13 εeff =(0.475・εr +0.67)・ε0 ・・・式14 ここでhは誘電体の膜厚、μは透磁率、ε0 は真空の誘
電率、εr は誘電体の比誘電率である。また、伝送線路
のもう一つのパラメータである遅延時間は式2を用いれ
ばよい。
D = 0.536 · W + 0.67 · t 0 Equation 13 ε eff = (0.475 · ε r +0.67) · ε 0 Equation 14 where h is a dielectric film The thickness, μ is the magnetic permeability, ε 0 is the dielectric constant of vacuum, and ε r is the relative dielectric constant of the dielectric. Expression 2 may be used for the delay time, which is another parameter of the transmission line.

【0023】この方法においてはKの値は定まらない
が、電磁場解析等から求められた周波数に対するSパラ
メータ特性や実際の測定によって得られたSパラメータ
特性のデータ等を参照して合わせ込みによって定める。
ただし、合わせ込みの作業は一つの配線形状パターンの
みに対してやれば、同種の配線パターンに対しては予測
することができるため、等価回路を導出する効率は大幅
に向上する。
In this method, the value of K is not determined, but is determined by fitting with reference to the S-parameter characteristics with respect to the frequency obtained from the electromagnetic field analysis or the like or the data of the S-parameter characteristics obtained by actual measurement.
However, if the matching operation is performed for only one wiring shape pattern, it can be predicted for the same type of wiring pattern, so that the efficiency of deriving an equivalent circuit is greatly improved.

【0024】即ち本発明によれば、配線の等価回路を効
率よく速やかに導出することを可能とする。
That is, according to the present invention, it is possible to efficiently and quickly derive an equivalent circuit of a wiring.

【0025】[0025]

【実施例】次に、本発明の実施例について説明する。図
1は配線の等価回路を導出する本方式のアルゴリズムを
示したものである。
Next, an embodiment of the present invention will be described. FIG. 1 shows an algorithm of the present system for deriving an equivalent circuit of a wiring.

【0026】図8はマルチ・チップ・モジュール(MC
M)と呼ばれるICチップの実装方式の構造を示した図
である。図9はプリント配線基板を用いた実装方式の構
造を示した図である。MCMによる実装はプリント配線
基板による実装と異なり、ICチップ80をパッケージ
ングせずに、信号パッド82,83をバンプ84を介し
て直接配線基板82に実装している。こうすることによ
り、チップ間の配線長を短くするとともに、パッケージ
に寄生するインダクタンスや容量の影響を除去し、高速
のシステムを狙おうというものである。しかしその反
面、MCMの配線基板では、配線の密度が高くなり配線
の抵抗が信号伝搬特性に及ぼす影響を無視できなくなっ
ている。しかも配線長としてはチップの一辺程度すなわ
ち数cmのオーダーであるため、配線を伝送線路として扱
う必要がある。このような損失を考慮した伝送線路にお
ける信号伝搬特性を解析するためには、配線の等価回路
を構築する必要がある。
FIG. 8 shows a multi-chip module (MC
FIG. 2 is a diagram showing a structure of an IC chip mounting method called M). FIG. 9 is a diagram showing a structure of a mounting method using a printed wiring board. Unlike the mounting using the printed wiring board, the mounting by the MCM is such that the signal pads 82 and 83 are directly mounted on the wiring board 82 via the bumps 84 without packaging the IC chip 80. By doing so, it is possible to shorten the wiring length between chips, remove the influence of inductance and capacitance parasitic on the package, and aim at a high-speed system. However, on the other hand, in the wiring board of the MCM, the density of the wiring is increased and the influence of the resistance of the wiring on the signal propagation characteristics cannot be ignored. Moreover, since the wiring length is about one side of the chip, that is, on the order of several cm, it is necessary to treat the wiring as a transmission line. In order to analyze the signal propagation characteristics in the transmission line in consideration of such a loss, it is necessary to construct an equivalent circuit of the wiring.

【0027】図2及び図3はMCMの配線基板におい
て、配線の特性を評価するための配線TEG(Test
Element Group)の断面構造及び上部か
ら見た形状を示したものである。信号を入出力するため
のパッドが、GND−signal−GNDという配置
になっているのは、入力容量が非常に低いウェーハ・プ
ローブ・ヘッドという高周波用のプローブの針先に合う
ようにするためである。
FIGS. 2 and 3 show a wiring TEG (Test) for evaluating wiring characteristics on an MCM wiring board.
3 shows a cross-sectional structure of the element group (Element Group) and a shape viewed from above. The pads for inputting and outputting signals are arranged as GND-signal-GND in order to match the tip of a high-frequency probe such as a wafer probe head having a very low input capacitance. is there.

【0028】この構造において、配線幅W=20μm ,
配線長l=6cm,配線膜厚t0 =2μm ,誘電体の比誘
電率εr =3.5,誘電体の膜厚h=20μm の配線に
おけるS21パラメータの特性の実測データと、本方式を
用いて導出された等価回路のシミュレーション結果を同
じグラフ上に示したものが図4である。測定データとシ
ミュレーション結果がよく一致していることがわかる。
図5が求められた等価回路の概略図である。この等価回
路検出にあたっては、パラメータKを決める際に、 K=4・h/d ・・・式15 を用いた。
In this structure, the wiring width W = 20 μm,
Wiring length l = 6 cm, the wiring film thickness t 0 = 2 [mu] m, the dielectric constant epsilon r = 3.5 the dielectric, the measured data of the characteristic of the S 21 parameter in the thickness h = 20 [mu] m of the wiring of the dielectric, the method FIG. 4 shows a simulation result of an equivalent circuit derived by using FIG. It can be seen that the measured data and the simulation result agree well.
FIG. 5 is a schematic diagram of the obtained equivalent circuit. In detecting the equivalent circuit, K = 4 · h / d (Equation 15) was used to determine the parameter K.

【0029】この式15及び式1〜11を用いて、配線
幅、配線長及び配線膜厚の異なったパターンにおけるS
パラメータ特性を予測することができる。
Using this equation (15) and equations (1) to (11), S in a pattern having a different wiring width, wiring length and wiring film thickness is obtained.
Parameter characteristics can be predicted.

【0030】図6は図4で測定したパターンに対して、
配線幅のみがW=40μm となったパターンにおける、
21特性の測定データと等価回路によるシミュレーショ
ン結果を同じグラフ上に示したものである。図6から、
特性の実測データとシミュレーション結果がよく一致し
ていることがわかる。図7が求められた等価回路の概略
図である。
FIG. 6 shows the pattern measured in FIG.
In a pattern where only the wiring width is W = 40 μm,
Shows the simulation result by the measurement data and the equivalent circuit of the S 21 characteristics on the same graph. From FIG.
It can be seen that the measured data of the characteristics and the simulation result agree well. FIG. 7 is a schematic diagram of the obtained equivalent circuit.

【0031】なお本発明はLSIの配線,プリント基板
の配線にも同じように適用できる。ただしLSIの配線
の場合GNDがSi等の半導体であるためGND面での
抵抗を考慮する必要があると思われるが、合わせ込みを
することによって調整できる。
The present invention can be similarly applied to LSI wiring and printed circuit board wiring. However, in the case of LSI wiring, since GND is a semiconductor such as Si, it may be necessary to consider the resistance on the GND plane, but it can be adjusted by matching.

【0032】[0032]

【発明の効果】以上説明したとおり本発明は、配線の等
価回路を効率よく速やかに導出することを可能とする。
As described above, the present invention makes it possible to efficiently and quickly derive an equivalent circuit of a wiring.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明である等価回路導出方法におけるアルゴ
リズムの実施例を示す図である。
FIG. 1 is a diagram showing an embodiment of an algorithm in an equivalent circuit deriving method according to the present invention.

【図2】本発明を適用して等価回路を導出した配線基板
の構造を示す断面図である。
FIG. 2 is a sectional view showing a structure of a wiring board from which an equivalent circuit is derived by applying the present invention.

【図3】本発明を適用して等価回路を導出した配線基板
のパターンを示す上面図である。
FIG. 3 is a top view showing a pattern of a wiring board from which an equivalent circuit is derived by applying the present invention.

【図4】本発明を適用して得られた等価回路によるシミ
ュレーション結果と実測データを比較した配線幅20μ
m ,配線長6cmの配線におけるS21パラメータ特性図で
ある。
FIG. 4 shows a wiring width of 20 μm obtained by comparing a simulation result of an equivalent circuit obtained by applying the present invention with measured data.
FIG. 9 is a S 21 parameter characteristic diagram for a wiring having a wiring length of 6 cm and a wiring length m.

【図5】本発明を適用して得られた配線幅20μm ,配
線長6cmの配線の等価回路を表した図である。
FIG. 5 is a diagram showing an equivalent circuit of a wiring having a wiring width of 20 μm and a wiring length of 6 cm obtained by applying the present invention.

【図6】本発明を適用して得られた等価回路によるシミ
ュレーション結果と実測データを比較した配線幅40μ
m ,配線長6cmの配線におけるS21パラメータ特性図で
ある。
FIG. 6 shows a wiring width of 40 μm obtained by comparing a simulation result of an equivalent circuit obtained by applying the present invention with measured data.
FIG. 9 is a S 21 parameter characteristic diagram for a wiring having a wiring length of 6 cm and a wiring length m.

【図7】本発明を適用して得られた配線幅40μm ,配
線長6cmの配線の等価回路を表した図である。
FIG. 7 is a diagram showing an equivalent circuit of a wiring having a wiring width of 40 μm and a wiring length of 6 cm obtained by applying the present invention.

【図8】マルチ・チップ・モジュールの構造を示す図で
ある。
FIG. 8 is a diagram showing a structure of a multi-chip module.

【図9】プリント配線基板を用いた突出方式を示す図で
ある。
FIG. 9 is a diagram illustrating a projection method using a printed wiring board.

【符号の説明】[Explanation of symbols]

80 ICチップ 81 配線基板 82,83 信号パッド 90,91 ICパッケージ 92 信号ピン 100 プリント配線基板 Reference Signs List 80 IC chip 81 Wiring board 82, 83 Signal pad 90, 91 IC package 92 Signal pin 100 Printed wiring board

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) G06F 17/50 JICSTファイル(JOIS)──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) G06F 17/50 JICST file (JOIS)

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】配線の等価回路を、抵抗素子、抵抗素子と
インダクターが並列接続されたもの、非損失の伝送線路
が複数個直列に接続された単位はしご段構造が直鎖状に
並ぶ回路網によって表現する配線の等価回路導出方法に
おいて、配線の膜厚が表皮効果によるスキンデプスと等
しくなる周波数を基準とする等比周波数列を求め、その
周波数列により各単位はしご段構造内のインダクタンス
成分を求め、次いでそれぞれのインダクターに並列に接
続される抵抗の値を周波数の数列及びインダクターの値
の積から求めることを特徴とする等価回路導出方法。
1. An equivalent circuit of a wiring is formed by a circuit network in which a resistance element, a resistance element and an inductor are connected in parallel, and a plurality of lossless transmission lines are connected in series, and a unit ladder stage structure is arranged in a straight line. In the method of deriving the equivalent circuit of the wiring to be expressed, an equivalent frequency sequence based on the frequency at which the film thickness of the wiring is equal to the skin depth due to the skin effect is obtained, and the inductance component in each unit ladder step structure is obtained from the frequency sequence, Next, an equivalent circuit deriving method, wherein a value of a resistor connected in parallel to each inductor is obtained from a product of a sequence of frequencies and a value of the inductor.
【請求項2】配線を分布定数線路とみなす必要がない程
度に計算機上で短く分割し、等価回路の一段目の抵抗の
値を求め、配線の等価回路を、抵抗素子、抵抗素子とイ
ンダクターが並列接続されたもの、非損失の伝送線路が
複数個直列に接続された単位はしご段構造が直鎖状に並
ぶ回路網によって表現する配線の等価回路導出方法にお
いて、配線の膜厚が表皮効果によるスキンデプスと等し
くなる周波数を基準とする等比周波数列を求め、その周
波数列により各単位はしご段構造内のインダクタンス成
分を求め、次いでそれぞれのインダクターに並列に接続
される抵抗の値を周波数の数列及びインダクターの値の
積から求めることを特徴とする等価回路導出方法。
2. A wiring is divided on a computer so that it is not necessary to regard the wiring as a distributed constant line, a resistance value of a first stage of an equivalent circuit is obtained, and an equivalent circuit of the wiring is formed by a resistance element, a resistance element and an inductor. In a method for deriving an equivalent circuit of a wiring represented by a circuit network in which a plurality of non-lossy transmission lines connected in parallel and a plurality of non-loss transmission lines are connected in series, the wiring thickness is a skin due to a skin effect. A sequence of equal frequencies based on the frequency equal to the depth is determined, the inductance component in each unit ladder structure is determined from the frequency sequence, and the value of the resistance connected in parallel with each inductor is determined by the frequency sequence and the inductor. A method for deriving an equivalent circuit, wherein the equivalent circuit is obtained from a product of values of:
【請求項3】配線の膜厚が表皮効果によるスキンデプス
と等しくなる周波数f0 をf0 =ρ・lM /(W/
0 )(ただしρは配線の抵抗率、lM は配線長、Wは
配線幅、t0 は配線膜厚)で求める請求項1または2に
記載の等価回路導出方法。
3. The frequency f 0 at which the thickness of the wiring becomes equal to the skin depth due to the skin effect is represented by f 0 = ρ · l M / (W /
t 0) (provided that ρ wiring resistivity, l M is the line length, W is the wiring width, t 0 is the equivalent circuit deriving method according to claim 1 or 2, obtained by wiring film thickness).
【請求項4】等比周波数列をfi =4-1+N・f0 /2
(ただしi=1、2、3、・・・N、Nは4-1+N・f0
/2>4・fM を満足する最小の整数、fM は等価回路
を表現したい周波数領域の最大値で、立ち上がり時間を
r として、fM =2.2/(2πTr )である)で求
める請求項3に記載の等価回路導出方法。
4. An iso-frequency sequence is defined as f i = 4 -1 + N · f 0/2.
(However, i = 1, 2, 3,... N, N is 4 −1 + N · f 0
/ 2> 4 · f M , f M is the maximum value in the frequency domain where an equivalent circuit is desired to be expressed, and f M = 2.2 / (2πT r ), where R r is the rise time. 4. The method for deriving an equivalent circuit according to claim 3, wherein
【請求項5】インダクターLi は 【数1】 により求める請求項4に記載の等価回路導出方法。5. The inductor L i is given by: The method for deriving an equivalent circuit according to claim 4, wherein 【請求項6】抵抗Ri はRi =2・π・fi ・Li /a
i (ただしai =K・21-i 、Kは配線に関するパラメ
ータ)により求める請求項5に記載の等価回路導出方
法。
6. The resistance R i is R i = 2 · π · f i · L i / a
6. The method for deriving an equivalent circuit according to claim 5, wherein i is obtained by using i (where a i = K · 2 1-i , K is a parameter relating to wiring).
【請求項7】実測データとの合わせ込みにより、Kを求
めそれによってRi を求める請求項6に記載の等価回路
導出方法。
7. The method for deriving an equivalent circuit according to claim 6, wherein K is obtained by combining the measured data with the measured data, thereby obtaining R i .
JP6025831A 1994-02-24 1994-02-24 Derivation method of wiring equivalent circuit Expired - Fee Related JP2806245B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6025831A JP2806245B2 (en) 1994-02-24 1994-02-24 Derivation method of wiring equivalent circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6025831A JP2806245B2 (en) 1994-02-24 1994-02-24 Derivation method of wiring equivalent circuit

Publications (2)

Publication Number Publication Date
JPH07234884A JPH07234884A (en) 1995-09-05
JP2806245B2 true JP2806245B2 (en) 1998-09-30

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP6025831A Expired - Fee Related JP2806245B2 (en) 1994-02-24 1994-02-24 Derivation method of wiring equivalent circuit

Country Status (1)

Country Link
JP (1) JP2806245B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5946211A (en) * 1997-02-28 1999-08-31 The Whitaker Corporation Method for manufacturing a circuit on a circuit substrate

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
工藤潤一、外3名、"超高速GaAs集積回路における配線の信号伝送特性の解析"、北海道大学工学部研究報告、北海道大学、1988年、No.140、P.121〜131

Also Published As

Publication number Publication date
JPH07234884A (en) 1995-09-05

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