JP2805768B2 - Satellite communication transceiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Industrial application field] The present invention relates to a transceiver device for satellite communication. 2. Description of the Related Art Conventionally, as this type of satellite communication transmitting / receiving apparatus, there is, for example, one shown in FIGS. FIG. 3 is a block diagram showing a conventional transmitting / receiving apparatus for satellite communication having an error correction function.
, A redundant bit for error correction is added to the input signal 210, and a signal 211 having a transmission speed N times (N> 1) the input signal 210 is modulated by a modulator 202 to a modulated signal 212, and an upconverter The transmission / reception splitter 20 receives the transmission frequency signal 213 at 203 and the transmission signal 214 through the high power amplifier 204.
From 5, an antenna feed signal is transmitted from an antenna (not shown). On the other hand, on the receiving side, the signal 216 from the antenna is sent to the low noise amplifier 206 through the transmission / reception splitter 205, and the low noise amplifier 20
The output of 6 is downconverter 20 as reception frequency signal 217
7, is input to the demodulation circuit 208 as a reception intermediate frequency signal 218 by the down converter 207, becomes a demodulation signal 219 through the demodulation circuit 208, is decoded by the decoding circuit 209, and is output as an output signal 220. . FIG. 4 is a block diagram showing a conventional transmitting / receiving apparatus for satellite communication having no error correction function.
308 is modulated by a modulator 301 to produce a modulated signal 309, an up-converter 302 is produced as a transmission frequency signal 310, and the high power amplifier 30
A transmission signal 311 is transmitted from the transmission / reception splitter 304 as an antenna supply signal through an antenna (not shown) through 3. On the other hand, on the receiving side, the signal 313 from the antenna is sent to the low noise amplifier 305 through the transmission / reception splitter 304, and the low noise amplifier 30
The output of 5 is the downconverter 30 as the reception frequency signal 314.
6 and the received intermediate frequency signal
315 is input to the demodulation circuit 307 and output as an output signal 316. [Problem to be Solved] The conventional satellite communication apparatus shown in FIG. 3 described above performs error correction coding and decoding regardless of the quality of the satellite communication circuit. Therefore, even in a favorable state of the communication line, redundant bits for error correction are added, and the throughput is reduced by the amount of the redundant bits. In other words, there is also a drawback that a transmission speed of N times the information speed is required even in a good line condition where no error correction is required. On the other hand, in the case of the transmitting / receiving device for satellite communication having the configuration shown in FIG. 4 having no error correction function, information can be transmitted at a transmission speed exactly equal to the information speed. The error rate is higher than that of the satellite communication apparatus shown in FIG. 3, and there is a problem that a problem arises in practicality. The present invention has been made in view of the above-described problems, and has as its object to provide a satellite communication transmitting / receiving apparatus having an error correction function and capable of selecting execution or non-execution of error correction. Means for Solving the Problems In order to achieve the above object, a satellite communication transmitting and receiving apparatus according to the present invention includes a first combining circuit for combining two data signal inputs in a time-division manner, and an error in one of the data signals. A coding circuit for performing correction coding, a selecting circuit for selecting and outputting one of an output of the combining circuit and an output of the coding circuit, a bit error rate measuring circuit for measuring a bit error rate of a received signal, A second combining circuit for combining the output of the circuit with the measurement result output of the bit error rate measuring circuit and the detection signal of an encoding / non-coding command detection circuit described below; A modulation circuit that outputs a frequency signal, an upconverter that converts the intermediate frequency signal into a transmission frequency signal, a large power amplifier that amplifies the output of the upconverter, a transmission / reception splitter, and a transmission / reception splitter. hand A low noise amplifier that receives and amplifies the received signal; a down converter that converts an output signal of the low noise amplifier into an intermediate frequency signal; a demodulation circuit that demodulates an output of the down converter; and a demodulation signal that is output by the demodulation circuit. , An encoded / unencoded command detection circuit for detecting an encoded / unencoded command for a transmission signal and outputting the result, and determining whether to decode or undecode a received signal from the demodulated signal. A decoding / non-decoding determination circuit, a decoding circuit for decoding the demodulated signal, a distribution circuit for distributing the demodulated signal synthesized in a time-division manner, an output of the decoding circuit and an output of the distribution circuit And a selection circuit for selecting and outputting one of the signals, so that information is carried in a redundant time slot for encoding without performing error correction encoding of transmission / reception signals according to line conditions. It is constituted. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of one embodiment of the present invention, and FIG. 2 is an explanatory diagram showing a configuration of a satellite communication system using the apparatus of the embodiment of FIG. As shown in FIG. 1, the transmitting side has two input signals,
That is, a first synthesizing circuit 1 for synthesizing the main input signal 19 and the sub input signal 20 in a time division manner, an encoding circuit 2 for performing error correction encoding of the sub input signal 20, an output 21 of the synthesizing circuit 1 and the encoding circuit 2, It comprises a selection circuit 3 for selecting one of the signals 22 and outputting it as a selection output signal 23, a second synthesis circuit 4, a modulation circuit 5, an up-converter 6, and a high power amplifier 7. On the other hand, the receiving side receives the signal 29 from the antenna through the transmission / reception splitter 9, and outputs the reception frequency signal 30. The low noise amplifier 10 receives the reception frequency signal 30 and receives the reception intermediate frequency signal.
Downconverter 11 for outputting as 31; demodulation circuit 12 for outputting received intermediate frequency signal 31 as demodulated signal 32; demodulated signal
A decoding circuit 13 that decodes 12 and outputs a decoded signal 33, a distribution circuit 14 that also receives the demodulated signal 32 and outputs a distributed main signal 34 and a sub output signal 36, and a decoded signal 33 and a distributed main signal 34 It comprises a selection circuit 15 which inputs and selects one of them and outputs it as a main output signal 35. In the figure, reference numeral 16 denotes a bit error rate measurement circuit,
And the state of the satellite communication line is measured, and if the bit error rate is equal to or less than a predetermined threshold, the combining circuit 4 combines the measurement result 37 with the selected output signal 23 to obtain the transmission information and the bit error. The composite output signal 24 including the measurement result of the ratio is output. In the figure, reference numeral 17 denotes an encoded / uncoded command detection circuit for detecting a line state signal received by the other station from the demodulated signal 32. If the detection signal is a status signal indicating that the line status is better than a predetermined threshold, the selection circuit 3 outputs the output 21 from the first synthesis circuit 1 to the selection output signal.
Send a control signal 39 to be output as 23 and select output signal 23
Then, a coded / uncoded state signal 38 indicating that the signal is not error correction coded is synthesized to obtain a synthesized output signal 24 which is an input signal of the modulation circuit 5. Further, in the figure, a decoding / non-decoding determination circuit 18 detects information indicating that the received signal is a non-error-correction coded signal from the demodulated signal 32, and outputs to the selection circuit 15 an output signal from the distribution circuit 14. It outputs a control signal 40 instructing to output 34 as a main output signal 35. In FIG. 2, reference numeral 401 denotes a satellite transponder, which includes a station A402 and a station B403.
It relays satellite communications between them. The stations A402 and B403 each have the transmitting / receiving device shown in FIG. Next, the operation of the present embodiment will be described. The station A402 is notified of the line state of the signal 404 via the signal 405 from the station B403 received via the satellite repeater 401. That is, the signal 28 from the antenna is transmitted to the low noise amplifier 10 through the transmission / reception splitter 9, and the output of the low noise amplifier 10 becomes the demodulated signal 32 through the down converter 11 and the demodulation circuit 12, and the bit error rate measurement circuit 16 The error rate is measured. When the bit error rate is equal to or less than a predetermined threshold value, the combining circuit 4 combines the measurement result 37 with the selection output signal 23 of the selection circuit 3 to obtain a combined output signal including the transmission information and the measurement result of the bit error rate. Outputs 24. Synthetic output signal 24
Is modulated by the modulation circuit 5 to become an intermediate frequency signal 25, which is transmitted to the transmitting / receiving antenna (not shown) through the up-converter 6, the high power amplifier 7, and the transmitting / receiving duplexer 9. Based on the demodulated signal 32, the coding / non-coding command detection circuit 17 detects a line state signal received by the partner station, and if the detected signal is a state signal that the line state is better than a predetermined threshold. In this case, the selection circuit 3 causes the synthesis input signal 21 output from the synthesis circuit 1 to be output as the selection output signal 23. A signal 38 indicating to the synthesizing circuit 4 that the selected output signal 23 is a signal not subjected to error correction coding.
Are combined, and the combined output signal 24 is input to the modulation circuit 5. At this time, the combined output signal 24 of the station A402 is
The information on the satellite link (404 in FIG. 4) has the transmission speed of the sum of the sub input signal 19 and the main input signal 20. The transmission information rate increases from the period during which the coding was being performed, and is sent to the partner station B403. On the other hand, the station B403 that has received the signal that has not been subjected to the feed correction encoding, the decoding / non-decoding determination circuit 18 outputs information 40 indicating that the received signal in the received signal is a non-error correction encoded signal. Detected from the demodulated signal 32 and instructs the selection circuit 15 to use the output signal 34 from the distribution circuit 14 as the output of the selection circuit 15. When the stations A402 and B403 are in the above state, the station A4
The sub input signal 19 of 02 is output as the sub output signal 36 of station B403, and the main input signal 20 of station A402 is
Is output as the main output signal 35. Therefore, station A402
When the line quality of the signal sent from the terminal to the station B403 is good, the sub input signal 19 and the main input signal 20 are transmitted at the same time without increasing the transmission speed of the satellite circuit. Further, when the bit error rate of the received signal at the station B 403 increases and exceeds a preset threshold, the station B 403 notifies the station A 402 via the satellite link 405 that the line condition has deteriorated. The coding / non-coding command detection circuit 17 of the station A 402 detects this notification from the received signal, and controls to select the error correction coding signal 22 from the coding circuit 2 as an input signal of the synthesis circuit 4. . At the same time, a signal 38 indicating that the selected output signal 23 which is an input signal to the synthesizing circuit 4 is an error correction coded signal is output.
To produce a composite output signal 24 to the modulation circuit 5. The combined output signal 24 input to the modulation circuit 5 is modulated, frequency-converted, and power-amplified and sent to the station B403 as the output signal 404 of the station A402. The station B403, which has received the signal 404 from the station A402,
The decoding determination circuit 18 determines from the decoded signal 32 that the received signal of the station B403 is an error correction coded signal, and outputs the signal 33 from the decoding circuit 13 to the selection circuit 15 as an output signal 35 of the selection circuit 15. The control signal 40 instructing the selection circuit 18 to output as is output. [Effects of the Invention] As described above, the present invention measures the bit error rate of a satellite circuit, stops error correction coding based on the measurement result, and places information on error correction code redundant bits, If the signal quality deteriorates, control is performed so that error correction coding is performed, so that the quality of the information signal transmitted at a constant transmission rate on the satellite is always kept at a certain level or higher, and the line condition is good. In such a case, it is possible to improve the average information transmission speed by enabling the transmission of the sub information signal.

[Brief description of the drawings]

FIG. 1 is a block diagram according to an embodiment of the present invention, and FIG.
FIG. 3 is a block diagram showing a conventional satellite communication transceiver having an error correction function, and FIG. 4 is a block diagram showing a configuration of a satellite communication system using the apparatus of the embodiment shown in FIG.
It is a block diagram which shows the conventional transmitting / receiving apparatus for satellite communication which does not have an error correction function. 1: Synthesis circuit, 2: Encoding circuit 3: Selection circuit, 4: Synthesis circuit 5: Modulation circuit, 6: Up converter 7: High power amplifier, 9: Tx / Rx 10: Low noise amplifier, 11: Down converter 12: Demodulation circuit, 13: Decoding circuit 14: Distribution circuit, 15: Selection circuit 16: Bit error rate measurement circuit 17: Encoding / unencoding command detection circuit 18: Decoding / non-decoding judgment circuit 19: Main Input signal 20: Sub input signal, 23: Select output signal 24: Synthetic output signal, 30: Receive frequency signal 31: Receive intermediate frequency signal 32: Demodulated signal, 33: Decoded signal 34: Distribution main signal 36: Sub output signal , 35: Main output signal 37: Measurement result, 39: Control signal 38: Coded / uncoded status signal 40: Control signal, 401: Satellite repeater 402: Station A, 403: Station B

Claims (1)

(57) [Claims] A first synthesizing circuit for synthesizing two data signal inputs in a time-division manner; an encoding circuit for error correction encoding one of the data signals; an output of the synthesizing circuit and the encoding; A selection circuit for selecting and outputting one of the outputs of the circuit,
A bit error rate measuring circuit for measuring a bit error rate of a received signal, and a measuring result output of the bit error rate measuring circuit and a detection signal of an encoding / non-coding command detection circuit described later are combined with an output of the selection circuit. A second combining circuit, a modulation circuit that modulates an output of the second combining circuit and outputs an intermediate frequency signal, an upconverter that converts the intermediate frequency signal into a transmission frequency signal, and amplifies an output of the upconverter. A high power amplifier, a transmission / reception splitter, a low noise amplifier for receiving and amplifying a received signal via the transmission / reception splitter, a down converter for converting an output signal of the low noise amplifier into an intermediate frequency signal, and a down converter. A demodulation circuit for demodulating an output of the converter, and an encoding / decoding circuit for detecting an encoded / unencoded command for a transmission signal from a demodulated signal output by the demodulation circuit and outputting the result. An uncoded command detection circuit, a decoding / non-decoding determination circuit for determining whether to decode or non-decode a received signal from the demodulated signal, and a decoding circuit for decoding the demodulated signal; A distribution circuit for distributing the demodulated signal combined in a time-division manner, and a selection circuit for selecting and outputting one of an output of the decoding circuit and an output of the distribution circuit; A transmitter / receiver for satellite communication, characterized in that information is carried in redundant time slots for encoding without performing error correction encoding.