JP2805667B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a so-called MNOS, M
The present invention relates to a semiconductor memory device having an electrically erasable split gate nonvolatile memory cell called ONOS.

[0002]

2. Description of the Related Art Conventionally, electrically erasable split gate nonvolatile memory cells called MNOS and MONOS have been known. This memory cell is provided with two gate electrodes, an address gate electrode and a memory gate electrode. This memory cell injects electrons into a predetermined layer constituting the memory gate electrode among the two gate electrodes. A voltage (threshold voltage) applied to a memory gate electrode required to turn on a transistor forming the memory cell in accordance with whether to write (write) or to emit (erase) electrons in the predetermined layer. ) Changes. Therefore, the digital value of "0" or "1" is stored depending on whether writing or erasing is performed on this memory cell, and at the time of reading, the difference between the threshold voltages is detected, so that the memory cell is in a write state. Or the erased state, that is, whether the content stored in the memory cell is '0' or '1'.

FIG. 3 is a partial circuit diagram of a semiconductor memory device using the above-mentioned nonvolatile memory cell, and FIG. 4 is a layout diagram on a semiconductor chip corresponding to the partial circuit diagram shown in FIG. For simplicity, corresponding elements in these figures are given corresponding numbers. 3 and 4 show four memory cells 10, 20, 3
0,40 is shown. These memory cells 10, 2
Of the memory cells 0, 30, 40, the drain electrodes 11, 31 of the memory cells 10, 30 are bit lines B _i extending in the vertical direction in FIG.
And the drain electrodes 2 of the memory cells 20 and 40
1, 41 are connected to the bit line B _{i + 1} . The source electrode 1 of each of the memory cells 10, 20, 30, 40
2, 22, 32 and 42 are grounded. Each of the address gate electrodes 13 and 23 of the memory cells 10 and 20 is connected to the address gate line X1, and the memory gate electrode 1
4 and 24 are connected to the memory gate line W1.
Similarly, the address gate electrodes 33 and 43 of the memory cells 30 and 40 are connected to the address gate line X2, and the memory gate electrodes 34 and 44 are connected to the memory gate line W2.

In the memory configured as described above,
When writing to the memory cell 10, for example, 9 V is applied to the memory gate line W1, and writing is performed by setting the bit line _Bi to the ground potential. At this time, the substrate is also set to the ground potential. For example, when erasing is performed on the memory cell 10, the memory gate line W
1 grounded, it is performed by applying 9V to the bit line B _i. Also when reading the stored contents of the memory cell 10, for example by applying a predetermined positive voltage to the address gate line X1, and connect it to the sense amplifier of the current-driven (not shown) the bit line B _i, thereby By detecting whether a current flows from the drain electrode 11 to the source electrode 12 of the memory cell 10 (ON state) or not (OFF state), whether the content stored in the memory cell 10 is “0” or “1” Is determined.

[0005]

The split gate type non-volatile memory cell such as the MONOS described above has a write / erase rewrite operation count (rewrite count) of about 10 ⁷ times and has two gates. Is about two orders of magnitude higher than a stack gate type memory cell having a vertically stacked structure, which is very advantageous in this respect.
Since the address gate electrode and the memory gate electrode are arranged side by side in the memory cell, when the structure shown in FIG. 4 is designed according to, for example, a 1 μm design rule, one memory cell shown by a one-dot chain line in FIG. The area around is about 1
7.2 μm ² , for example, when a memory cell having the same capacity as that of a stacked gate type memory cell designed by using the same design rule has a large cell area of, for example, about 20%, and therefore has a low integration degree. There is a problem that the chip size becomes large.

Here, as one of the layouts applied to a ROM or the like of a semiconductor memory for improving the degree of integration, X is
Type-structured memories are known. FIG. 5 shows the R of the X-type structure.
FIG. 3 is a circuit diagram illustrating a part of the OM. A number of bit lines,..., B _i−1 , B _i , B _{i + 1} ,... Extend in the vertical direction of the figure, and a direction connecting the upper left and lower right and a direction connecting the upper right and lower left. The memory cells 110, 130, 12 arranged one by one between bit lines adjacent to each other
A memory cell column consisting of 0,140 extends. In this figure, three bit lines B _i−1 , B _i , B _{i + 1} and two memory cells 110 forming one memory cell row extending in the direction connecting the upper left and lower right of the figure are shown. , 140 and two memory cells 120, 130 forming one memory cell column extending in the direction connecting the upper right and lower left of the figure.

The memory cells 110, 120, 13
0, 140 each two source / drain electrodes 111, 1
12; 121, 122; 131, 132; 141, 14
Each whereas 112,122,131,141 of 2 at a predetermined point 160 on the bit line B _i, are connected to each other, and the bit line B _i. Also, the memory cell 11
0, 130 each other source / drain electrode 111, 1
32 is a predetermined point on the bit line B _{i- 1} ,
20, 140 each other source / drain electrode 121,
142 is connected to each predetermined point on the bit line _{Bi + 1} . The gate electrodes 113 and 123 of the memory cells 110 and 120 are connected to a gate line W1 extending left and right in the figure, and the gate terminals 133 and 143 of the memory cells 130 and 140 are connected to a gate line W2. .

In the case of a ROM, for example, as shown in the memory cell 110, information "1" and "0" is stored depending on whether or not a part 115 of the wiring is equivalently disconnected. When the information stored in the memory cell 110 is read, the bit line B _i-1 is grounded, the bit line B _i is connected to the sense amplifier, and when a predetermined positive voltage is applied to the gate line W1, For example, “1” is detected when no current flows. For example, when information stored in memory cell 120 is read, bit line B _i is grounded, bit line B _{i + 1} is connected to a sense amplifier, and a predetermined positive voltage is applied to gate line W1. An electric current flows through 120, and thus, for example, “0” is detected.

In the case of a memory cell having only one gate, such as a ROM, as described above, by forming the memory cell into an X-type, the density of the memory cells on a semiconductor chip is increased, thereby achieving high integration. In the case of a split gate type memory cell, an X-type structure cannot be simply adopted as described below. FIG. 6 is a circuit diagram in which split gate type memory cells are arranged in an X type.

As in the case of the ROM of FIG. 5, a number of bit lines..., B _{i -1} , B _i , B _{i + 1} ,. The memory cells 210 and 23 arranged one by one between bit lines adjacent to each other in a direction connecting the lower part and a direction connecting the upper right part and the lower left part.
0; a memory cell column consisting of memory cells consisting of 220 and 240 extends. FIG. 6 shows one memory cell extending in the direction connecting the three bit lines B _i−1 , B _i , B _{i + 1} and the upper left and lower right of the figure, as in the case of FIG. Two memory cells 210 and 240 forming a column and two memory cells 220 and 230 forming one memory cell column extending in the direction connecting the upper right and lower left of the figure are shown.

These memory cells 210, 220, 23
0, 240 each two source / drain electrodes 211,
12; 221, 222; 231, 232; 241, 24
Each whereas 212,222,231,241 of 2 at a predetermined point 260 on the bit line B _i, are connected to each other, and the bit line B _i. Also, the memory cells 210 and 23
0, the other source / drain electrodes 211 and 232 are connected to respective predetermined points on the bit line B _i-1 and the memory cells 220 and 2
40 other source / drain electrodes 221 and 242
Are connected to respective predetermined points on the bit line B _{i + 1} . The address gate electrodes 213 and 223 of the memory cells 210 and 220 are connected to an address gate line X1 extending left and right in the figure, and the memory gate electrodes 214 and 224 are similarly connected to a memory gate line W1 extending left and right in the figure. It is connected to the. Also, like this,
Each address gate electrode 23 of the memory cells 230 and 240
3, 243 are connected to the address gate line X2, and each memory gate electrode 234, 244 is connected to the memory gate line W2.

Here, for example, a case where writing is performed on the memory cell 230 will be considered. In this case, for example, 9 V is applied to the memory gate line W2 and the bit line _Bi is grounded, so that the memory gate electrode 234 of the memory cell 230 is implanted (writing is performed). for the memory gate electrode 244 of the memory gate electrode 234 and the memory cell 240 are both connected to the memory gate line W2, these are applied 9V simultaneously to the memory gate electrode 234 and 244, also to the bit line B _i is These memory cells 23
Since both of the source / drain electrodes 231 and 241 of the 0,240 is connected, the source / drain electrodes of the memory cell 240 at the same time the source / drain electrode 231 is OV of the memory cell 230 by grounding the bit line B _i 241 also becomes OV, and therefore the memory cell 23
At the same time that data is written to 0, data is also written to the memory cell 240, and these two memory cells 230 and 240 cannot be changed to different states (written state and erased state). Will occur.

SUMMARY OF THE INVENTION In view of the above circumstances, it is an object of the present invention to improve the degree of integration of a semiconductor memory device using split gate type electrically erasable memory cells as compared with the prior art.

[0014]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises two source / drain electrodes, an address gate electrode and a memory gate electrode for controlling the two source / drain electrodes. A semiconductor memory device comprising a large number of electrically erasable nonvolatile memory cells having a split gate structure, comprising: (a) a number of bit lines extending in parallel in the vertical direction; (b) an upper left and lower right Nonvolatile memory cells are arranged one by one between bit lines adjacent to each other and extend in parallel to each other in a direction connecting the adjacent nonvolatile memory cells at predetermined points on a bit line sandwiched between the nonvolatile memory cells adjacent to each other. A large number of first memory cell columns (c) to which one source / drain electrode of each of the non-volatile memory cells is connected, Extend parallel to each other in the direction,
Non-volatile memory cells are arranged one by one between bit lines adjacent to each other, and one source / source of each of the non-volatile memory cells adjacent to each other at the predetermined point on the bit line sandwiched between the non-volatile memory cells adjacent to each other. A plurality of second memory cell columns to which drain electrodes are connected,
(D) 2 arranged in the left-right direction with each bit line interposed
The address gate electrode of one of the two nonvolatile memory cells is provided on the bit line side between the two nonvolatile memory cells with respect to the memory gate electrode of the one nonvolatile memory cell. The memory gate electrode of the other nonvolatile memory cell of the two nonvolatile memory cells is closer to the bit line between the two nonvolatile memory cells than the address gate electrode of the other nonvolatile memory cell. It is characterized by being provided.

[0015]

According to the semiconductor memory device of the present invention, the address gate electrode of one of the two nonvolatile memory cells arranged in the left-right direction with each bit line interposed therebetween is connected to the other nonvolatile memory cell. Is provided on the bit line side sandwiched between these two nonvolatile memory cells with respect to the memory gate electrode, and the memory gate electrode of the other nonvolatile memory cell of the two nonvolatile memory cells is connected to the other nonvolatile memory cell. The structure described above is provided on the bit line side between these two nonvolatile memory cells rather than the address gate electrode of the non-volatile memory cell. Therefore, the problem described with reference to FIG. Despite its existence, the X-shaped structure is adopted,
The area occupied by one memory cell is reduced, and high integration is possible. Here, when the design rule of 1 μm is adopted, the area per one memory cell can be about 13.3 μm ² by adopting the X-type structure, and the occupied area is smaller than the conventional one (see FIGS. 3 and 4). Is reduced by about 23%, which makes it possible to achieve almost the same degree of integration as a stacked gate type memory cell when designed according to the same design rule. The lowness is overcome, so that the advantages of the split gate type memory cell can be more effectively utilized.

[0016]

Embodiments of the present invention will be described below. FIG. 1 is a partial circuit diagram of a semiconductor memory device according to one embodiment of the present invention, and FIG. 2 is a layout diagram on a semiconductor chip corresponding to the partial circuit diagram shown in FIG. Again, for simplicity, corresponding elements in these figures are given corresponding numbers.

Four memory cells 310, 320 330, and 340 are arranged in the transistor arrangement region 300 shown in FIG. These four memory cells 310, 32
0, 330, and 340, memory cells 310 and 340
Constitutes a part of a memory cell string connecting the upper left and lower right of the figure, and memory cells 320 and 330 constitute a part of a memory cell string connecting the upper right and lower left of the figure. In this case, three bit lines B _i-1 and B
_i , B _{i + 1} are shown.

The memory cells 310, 320, 330, 34
0 each of two source / drain electrodes 311, 312; 3
21,322; 331,332; each other hand 312,322,331,341 of the 341 and 342 at a predetermined point 360 on the bit line B _i, are connected to each other, and the bit line B _i. Also, the memory cells 310 and 330
The other source / drain electrodes 311 and 332 of the memory cell 320 and the other source / drain electrodes 32 of the memory cells 320 and 340 are provided at predetermined points 361 and 362 on the bit line Bi _-1.
1, 342 is a predetermined point 363 on the bit line B _{i + 1}
364.

Here, the address game of the memory cell 310 is performed.
The gate electrode 313 is more visible than the memory gate electrode 314.
Line B_i Memory cell 320
Address gate electrode 323 is connected to its memory gate electrode
Bit line B than 324 _{i + 1} It is provided on the side.
Therefore, these address gate electrodes 313, 323
And an address gate line X1 connecting these memory gates.
Memory gate line W connecting gate electrodes 314 and 324
1 cross each other. Also the memory cell
The address gate electrode 333 of the memory gate 330
Bit line B rather than electrode 334_i-1 Prepared for the side
And the address gate electrode 343 of the memory cell 340
Indicates that the bit line B is higher than the memory gate electrode 344.
_i It is provided on the side. Therefore, these address games
Address gate line X connecting electrodes 333 and 343
2 and these memory gate electrodes 334, 344
The memory gate lines W2 also cross each other.

Here, a case where data is written to the memory cell 320 will be described. In this case, as an example, a voltage (V) shown in Table 1 below is applied to each line.

[0021]

TABLE 1 _{───────────────────────────────── B i-1 B i B} i + 1 W1 X1 W2 X2 substrate 9 0 9 9 0 0 0 0 0 In this case, the memory cell 320 Memory gate electrode 324
Is applied to the memory cell 320, and the opposite surface 324 'is at 0V, thereby writing to the memory cell 320. In this case, the other memory cells 310, 33
For 0,340, no problem occurs as described below.

First, with respect to the memory cell 310, 9 V is applied to the memory gate electrode 314. When writing has already been performed on the memory cell 310, 0 V of the substrate is applied to the opposing surface 314 'of the memory gate electrode 314. Is applied and rewriting is performed. When the memory cell 310 is in the erased state, 9 V of the bit line Bi _-1 is applied to the opposite surface 314 ', and neither writing nor erasing is performed.

[0023] With respect to the memory cell 330, the and the memory gate electrode 334 0V is applied, because also the bit line B _i substrate is also 0V, the memory cell 3
Regardless of whether 30 is in the written state or the erased state, the opposing surface 334 'of the memory gate electrode 334 is at 0 V, so neither writing nor erasing is performed. Further, with respect to the memory cell 340, 0 V is applied to the memory gate electrode 344, and when writing has already been performed on the memory cell 340, 0 V of the substrate is applied to the opposing surface 344 'of the memory gate electrode 344. When the memory cell 340 is in the erased state, the voltage is applied to the surface facing the memory gate electrode 344 at 9 V, and the erase operation is performed again.

As described above, when writing to one memory cell, no problem occurs in other memory cells.
Although the case of writing has been described here, the case of erasing and reading also operates normally.

[0025]

As described above, according to the semiconductor memory device of the present invention, the address gate electrode of one of the two nonvolatile memory cells arranged in the horizontal direction with each bit line interposed therebetween. Is provided on the bit line side between the two nonvolatile memory cells with respect to the memory gate electrode of the one nonvolatile memory cell, and the other nonvolatile memory cell of the two nonvolatile memory cells is Since the memory gate electrode is provided on the bit line side between the two nonvolatile memory cells with respect to the address gate electrode of the other nonvolatile memory cell, the memory gate electrode is a split gate type memory cell. The X-type structure is adopted, and the occupation area per memory cell is reduced. The extent or degree of integration can be achieved. This overcomes the low degree of integration when compared with the stacked gate type memory cell, and thus makes it possible to make more effective use of the advantages of the split gate type memory cell.

[Brief description of the drawings]

FIG. 1 is a partial circuit diagram of a semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is a layout diagram on a semiconductor chip corresponding to the partial circuit diagram shown in FIG. 1;

FIG. 3 is a partial circuit diagram of a semiconductor memory device using nonvolatile memory cells.

FIG. 4 is a layout diagram on a semiconductor chip of a portion corresponding to the partial circuit diagram shown in FIG. 3;

FIG. 5 is a circuit diagram showing a part of a ROM having an X-type structure.

FIG. 6 is a circuit diagram in which split gate type memory cells are arranged in an X type.

[Explanation of symbols]

300 Transistor area 310, 320, 330, 340 Memory cell 311, 312, 321, 322, 331, 332, 3
41,342 Source / drain electrodes 313,323,333,343 Address gate electrodes 314,324,334,344 Memory gate electrodes 360,361,362,363,364 Predetermined points B _i−1 , B _i , B _{i + 1} Bit line X1, X2 Address gate line W1, W2 Memory gate line

Claims (1)

(57) [Claims] 1. An electrically erasable non-volatile memory having a split gate structure, comprising two source / drain electrodes, and an address gate electrode and a memory gate electrode for controlling the two source / drain electrodes. In a semiconductor memory device in which a large number of cells are arranged, a plurality of bit lines extending parallel to each other in a vertical direction, and one between the adjacent bit lines extending parallel to each other in a direction connecting upper left and lower right. A plurality of the non-volatile memory cells connected to each other and the source / drain electrodes of one of the non-volatile memory cells connected to each other at a predetermined point on the bit line sandwiched between the non-volatile memory cells adjacent to each other; Adjacent to each other, extending parallel to each other in a direction connecting the upper right and the lower left. The non-volatile memory cells are arranged one by one between the non-volatile memory cells and the source / source of one of the non-volatile memory cells adjacent to each other at the predetermined point on the bit line sandwiched between the non-volatile memory cells adjacent to each other. A plurality of second memory cell columns to which a drain electrode is connected, and the address gate electrode of one of the two nonvolatile memory cells arranged in the left-right direction with the respective bit lines interposed therebetween. Is provided on the bit line side between the two nonvolatile memory cells with respect to the memory gate electrode of the one nonvolatile memory cell, and the other nonvolatile memory of the two nonvolatile memory cells is provided. The memory gate electrode of the cell is more than these two address gate electrodes of the other non-volatile memory cell. A semiconductor memory device provided on the bit line side sandwiched between nonvolatile memory cells.