JP2804702B2 - Clock line optimization design method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock line optimizing design method, and more particularly, to quickly evaluate a clock skew generated in a clock line of a large-scale semiconductor integrated circuit and optimize the design of the clock line. And

[0002]

2. Description of the Related Art In recent years, as the scale and speed of a semiconductor integrated circuit (hereinafter referred to as "LSI") increases, how to reduce clock skew has become an important issue in the design of ASICs and the like. Hereinafter, the problem of the clock skew will be briefly described with reference to FIGS. Now, in the circuit shown in FIG.
There should be no deviation of the clock CLK supplied to 2. However, when the circuit shown in FIG. 5 is formed into an LSI, as shown in FIG. 6, a parasitic resistance R and a parasitic capacitance C of the wiring exist, and therefore, a shift occurs between the clocks CLK1 and CLK2. This shift is called clock skew.

Next, let us consider the problem of clock skew with reference to the timing chart of FIG. (1) When there is no clock skew (normal operation) The change of the input (IN1) of the DFF1 is caused by the output O at time t1.
This is a change of 1. Then, the change of O1 becomes D at time t2.
The data is captured by the FF2 and output as the output O2 of the DFF2 at time t3. (2) When there is a clock skew (malfunction) If the output O1 of the DFF1 reaches the input IN2 of the DFF2 earlier than the time t1 '(although it should have been taken into the DFF2 at the time t2). During the clock skew (t1 to t1 '), the data is taken into the DFF2 and output as an output O2 at time t1'. In other words, the signal is lost. This is a malfunction due to clock skew.

The above malfunction does not occur if the clock skew is small or the time when the signal of DFF1 is transmitted from O1 to IN2 is larger than the clock skew. Therefore, a pattern layout method that minimizes clock skew has been studied. For example, as shown in FIG. 1, a main clock line (MCL) extends on a semiconductor chip (CHP), and a clock driver (CD) for driving the main clock line (MCL) is provided. From the main clock line (MCL), a plurality of subsidiary clock lines (BCL)
1 to BCLn), and a number of flip-flops (FF) are connected to each of the subsidiary clock lines (BCL1 to BCLn).

In the above pattern layout configuration,
By increasing the line width of the main clock line (MCL) and using a low-impedance clock driver (CD), clock skew and clock delay can be reduced. This type of pattern layout method is described in, for example, "IEEE 1990 CUSUTOM INTEGRATEDCIRC
UITS CONFERENCE, page 16.4.1.

[0006]

However, when an LSI is actually designed based on the above pattern layout, the following problems arise. First, in an actual LSI, there are a very large number of flip-flops (FF) of several hundred to several thousand, and the connection relationship with the sub clock lines (BCL1 to BCLn) is complicated. It has been extremely difficult to simulate clock skew for this LSI. For this reason, quantitative evaluation was not sufficient, and malfunctions due to clock skew frequently occurred particularly in large-scale LSIs.

Second, for individual LSIs, SPIC
If a detailed equivalent circuit by a circuit simulator such as E is manually configured by input, it requires a great deal of human labor, and the balance of equivalent circuit constants is poor.
There was a problem in the convergence of the clock skew calculation result.
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has been made in consideration of the above-described problems. It aims to provide a generalized design method.

[0008]

According to the present invention, a main clock line (MCL), a clock driver (CD) for driving the main clock line (MCL), and a branch from the main clock line (MCL) are provided. A clock line optimization design method in a semiconductor integrated circuit having a plurality of sub clock lines (BCL1 to BCLn) and a plurality of flip-flops (FF) connected to the plurality of sub clock lines (BCL1 to BCLn). Then, an equivalent CR time constant distribution circuit is automatically generated by a computer in accordance with the number of the sub clock lines (BCL1 to BCLn) and the number of flip-flops (FF), and the equivalent circuit is solved by a circuit simulator. Is used to evaluate the clock skew at each node.

Further, according to the present invention, in the above-mentioned equivalent circuit, the number of flip-flops (FF) connected to each of the sub clock lines (BCL1 to BCLn) is the same,
In addition, the same CR time constant distribution is set.

[0010]

According to the present invention, firstly, an equivalent circuit is automatically formed simply by inputting the number of clock lines (BCL1 to BCLn) and the number of flip-flops (FF). In addition, the clock skew can be quantitatively evaluated.

Second, in the equivalent circuit, the number of flip-flops (FF) connected to each of the sub clock lines (BCL1 to BCLn) is set to be the same and the same CR time constant distribution is set so that the input is made equal. There is an advantage that the operation becomes easy, the balance of the equivalent circuit is improved, and the calculation result of the clock skew is stably converged.

[0012]

Next, an embodiment of the present invention will be described with reference to FIGS. The clock line optimization design method of the present invention is based on a pattern layout as shown in FIG. That is, a semiconductor chip (C not shown)
HP), a main clock line (MCL) is extended,
A clock driver (CD) for driving the main clock line (MCL) is provided. A plurality of sub clock lines (BCL1 to BCLn) are branched from the main clock line (MCL), and a large number of flip-flops (FF) are connected to each sub clock line (BCL1 to BCLn). ing.

Here, the main clock line (MCL) and the supporting clock lines (BCL1 to BCLn) are formed of the same metal layer, and the clock driver (CD) is
It is composed of a MOS type inverter. In FIG. 1, the supporting clock lines (BCL1 to BCLn) are branched only in one direction, but may be branched to both sides of the main clock line (MCL).

The following parameters are used to generate an equivalent circuit from the above layout.
The specific values of the parameters are only examples. <Sheet resistance of metal layer> rsh: 0.05226 [ohm / square] <Unit capacitance of metal layer> area: 5.16e-05 [pf / um2] <Fan out> fanout: 200 <Input capacitance of FF> cin: 0.024 [ pf / fanout] <Clock driver (CD) size> pch w: 100 [um] pch l: 1 [um] nch w: 100 [um] nch l: 0.8 [um] <Main clock line (MCL)> Length Trunc l: 4000 [um] width trunc w: 1.2 [um] <supported clock lines (BCL1 to BCLn)> number of lines tri num: 10 length tril: 2000 [um] width tri w: 1.2 [um] and A CR distributed constant circuit as shown in FIG. 2 is automatically generated by a computer based on the above pattern layout and the above parameter designation. Thereafter, this equivalent circuit is connected to a circuit simulator such as SPICE and automatically solved to obtain each node (n 0 0,
clock skew at n 0 k, n 1 k, etc.). Then, by optimizing the above parameters (in particular, trunc w tri w) based on the result, optimization of the clock line design can be achieved.

In the embodiment, the number of flip-flops (FF) connected to each of the sub clock lines (BCL1 to BCLn) is set to be the same, and the same CR time constant distribution is set. It is only necessary to specify the number of lines of the supporting clock lines (BCL1 to BCLn) and the fanout (same as the number of FFs) among the above parameters. Therefore, there is an advantage that the task of inputting parameters can be saved and the convergence of the circuit simulation can be improved.

Next, FIGS. 3 and 4 show an example of the result of solving the equivalent circuit of FIG. 2 configured as described above with a circuit simulator. Note that the above specific values are used for the parameter values. FIG. 3 shows the time change of the potentials of the nodes (n 0 1) and (n 1 10) when the input voltage Vin of the clock driver (CD) changes from the L level to the H level. FIG. 4 shows a clock driver (C
D) shows the time change of the potentials of the nodes (n 0 1) and (n 1 10) when the input voltage Vin changes from the H level to the L level. As is clear from the configuration of the equivalent circuit, the node (n) closest to the clock driver (CD)
0 1) responds fastest, and at the farthest node (n1 10)
Will respond the slowest.

Therefore, generally, the farthest node (n 1
In order to keep the clock skew in 10) below a certain value,
By adjusting the parameter values, it is possible to design an LSI without malfunction due to clock skew.

[0018]

As described above, according to the present invention,
By simply inputting the number of supporting clock lines (BCL1 to BCLn) and the number of flip-flops (FF), an equivalent circuit is automatically formed, so that the clock skew can be quantitatively evaluated very easily. As a result, an LSI that does not malfunction due to clock skew
Can be quickly designed.

Further, in the equivalent circuit, the number of flip-flops (FF) connected to each of the sub clock lines (BCL1 to BCLn) is set to be the same, and the same CR time constant distribution is set, so that the parameter input can be performed. In addition to the labor saving, there is an advantage that the balance of the equivalent circuit is improved and the calculation result of the clock skew converges stably.

[Brief description of the drawings]

FIG. 1 is a pattern layout diagram according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram according to the embodiment of the present invention.

FIG. 3 is a graph showing calculation results of clock skew according to a conventional example.

FIG. 4 is a graph showing calculation results of clock skew according to a conventional example.

FIG. 5 is a circuit diagram for explaining the problem of clock skew.

FIG. 6 is a circuit diagram for explaining the problem of clock skew.

FIG. 7 is a timing chart for explaining the problem of clock skew.

[Explanation of symbols]

 CD clock driver MCL main clock line BCL1 ~ BCLn support clock line FF flip-flop

Claims (2)

(57) [Claims] A main clock line; a clock driver for driving the main clock line; a plurality of sub clock lines branched from the main clock line; and a plurality of flip-flops connected to the plurality of sub clock lines. A clock line optimization design method in a semiconductor integrated circuit having: a computer automatically generates an equivalent CR time constant distribution circuit according to the number of the sub clock lines and the number of flip-flops; such equivalent circuit circuit simulator
A clock line optimizing design method, wherein a clock skew at each node is evaluated by solving the clock skew. 2. The clock line according to claim 1, wherein in the equivalent circuit, the number of flip-flops connected to each of the sub clock lines is set to be the same, and the same CR time constant distribution is set. Optimization design method .