JP2797833B2 - Parallel instruction execution control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel instruction execution control system for controlling respective operation units of a processor having a plurality of operation units in parallel.

[0002]

2. Description of the Related Art In a processor as described above, the dependency of instructions and data is analyzed when a compiler generates a target program, and an assembly instruction is arranged based on the result of analysis. The generated assembly instruction sequence, which is a target program, is a sequence of parallel assembly instructions.Each of the parallel assembly instructions includes the same number of assembly instructions as the number of operation units. In a cycle that does not exist, a null instruction indicating that nothing is to be executed is placed at a corresponding position in the parallel assembly instruction. At the time of execution, one parallel assembly instruction, that is, a group of assembly instructions equal in number to the operation units, is extracted from the assembly instruction sequence as the target program and decoded for each cycle, and each operation unit is controlled based on the result. .

[0003]

However, in the prior art, it is often impossible to actually execute an assembly instruction for all arithmetic units in each cycle, and in particular, a program having a low parallelism is often used. In this case, the target program will include many empty instructions. As means for solving such a problem, for example, Crowell R. et al.
P., Nix R. P., O'Donnell J. J., P
apporth D. B. and Rodman P.S.
K. : “A VLIW architecture f
or atrace scheduling comp
iler ", IEEE Trans. Computer
s, 37, 8 pp. 967-979 (1988-0)
8), a method is proposed in which the target program is compressed by adding the position information of the expanded instruction, and the compressed target program is expanded on a cache memory using dedicated hardware at the time of execution. However, this method has a drawback that the configuration of the deployment hardware becomes very complicated.

[0004] Further, since the above-mentioned problem is caused by the fact that the compiler statically allocates the target program, as a means of controlling parallel execution from a completely different aspect, dynamically executing an instruction at the time of execution is performed. A method called superscalar, which analyzes the dependency of a computer and executes execution control of a processor having a plurality of arithmetic units based on the analysis, is disclosed by McGeady S.S. : “The i960
CA superscalar implementa
Tion of the 80960 archite
cure ", Compcon Spring 90
digestof papers, pp. 232-24
0, IEEE (1990) and the like. However, this superscalar method has a drawback in that it requires complicated and enormous hardware for analyzing instruction dependencies and resource availability, and the analysis of instruction dependencies is limited to a narrow range. Was.

An object of the present invention is to solve the above-mentioned problems,
It is an object of the present invention to provide a parallel instruction execution control method capable of easily performing the above-described parallel execution control of a processor by using a small-sized target program that does not include unnecessary empty instructions without using complicated hardware. .

[0006]

Parallel instruction execution control method of the present invention According to an aspect of the parallel by Tei Ru each assembly instructions included in parallel assembly instruction sequence is an object program operations of each of the processors having a plurality of operation portions In the parallel instruction execution control method, the parallel assembly instruction
In one cycle of the processor in the field of
Set a flag to indicate the break of parallel assembly instructions,
During execution of the processor, the previous
From the end position to the assembly instruction with the flag set.
Are executed in parallel by the respective operation units.
You .

[0007]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a target program based on the parallel instruction execution control method of the present invention. Hereinafter, the procedure of the embodiment of FIG. 1 will be specifically described. It should be noted that the target processor here uses two integer operation instructions (or load / store instructions) in one cycle.
, One floating-point operation instruction and one branch instruction at the same time, and no delay occurs for simplicity.

In FIG. 1, 11.12.13.14 indicates parallel assembly instructions to be executed simultaneously in one cycle. This parallel assembly instruction includes a variable number of assembly instructions. For example, the eleven parallel assembly instructions include assembly instructions 111 and 113 to be executed in each integer arithmetic unit. Here, 111 represents adding the integer 10 to the contents of the register r8 and placing the result in r8, and 113 represents subtracting the integer 1 from the contents of the register r10 and placing the result in r10. Also, 11
Numerals 2 and 114 are flags indicating whether the instructions 111 and 113 are the end of the parallel assembly instruction. 112 is a flag that is not set, and 114 is a flag that is set. Similarly, the twelve parallel assembly instructions are r8
121, r8 and r10 for storing the contents of
, And puts the result in r8. The 13 parallel assembly instructions include an instruction 131 for branching to the address indicated by the label "label" if the contents of r8 are equal to 0, and the 14 parallel assembly instructions load the contents of a into the register r9.
Is included.

In FIG. 1, four assembly instructions, ie, 111, 113, 121 and 122, are first read. However, since the flag 113 is set in the instruction 113, in this cycle, 111 and 113, ie, the parallel assembly instruction 11 is read. Are executed, and 121 and 122 do not execute until the next cycle. In the next cycle, since the flag is set in 122, 121 and 122, that is, the parallel assembly instruction 12 is executed. Similarly,
In subsequent cycles, parallel assembly instructions 13 and 14 are executed. Here, the instruction 131 has no flag, because it is assumed that a parallel assembly instruction is always separated in a branch instruction.

FIG. 2 shows an example of a target program according to a conventional method for comparison. In FIG. 2, 21, 22, 23, and 24 indicate parallel assembly instructions. In this case, one parallel assembly instruction always includes four assembly instructions. The four instructions may include one or more empty instructions represented by NOP. For example, the parallel assembly instruction 21 includes 211, 212, 213, and 214 assembly instructions, and 213 and 214 are empty instructions.
In the conventional method, the instructions are read and executed in the order of 21, 22, 23, and 24 in each cycle. In this case, more than half are empty instructions, and resources such as memory and buses which are about twice as large as those of the present invention are used. You will waste it.

[0011]

According to the present invention, as described above ,
One size of the processor in the field of the column assembly instruction
Flag indicating the break of parallel assembly instructions
Is set, and when the processor is executed,
Assembly flagged from the end of the run
Up to the instruction is executed in parallel by each operation unit, so the target program
Unnecessary free instructions can be eliminated from the program,
Parallel execution control without wasting resources such as buses
It can be done easily .

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a target program based on a parallel instruction execution control system of the present invention.

FIG. 2 is a diagram showing a target program according to a conventional method.

[Explanation of symbols]

11 to 14 Parallel assembly instructions 111, 113, 121, 122, 131, 141 Assembly instructions to be executed in each arithmetic unit 112, 114 Flag

Claims (1)

(57) [Claims] 1. A parallel instruction execution control method for controlling in parallel by each of the arithmetic unit the assembly instructions Ru Tei included in parallel assembly instruction sequence is an object program for a processor having a plurality of operation portions, the parallel assembly
One cycle of the processor in the field of the instruction
Flag that indicates the break of parallel assembly instructions
When executing the processor, the previous
From the end position of the assembly
A parallel instruction execution control method, wherein the instructions are executed in parallel by the respective operation units .