JP2787852B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a DRAM type semiconductor memory device having a sense amplifier for amplifying a signal between a pair of bit lines.

[0002]

2. Description of the Related Art In a dynamic random access memory (DRAM), one memory cell usually comprises one capacitor and one switching MOS transistor, and the charge stored in the capacitor is reduced. Information is recorded in such a manner that the amounts correspond to “0” and “1”. In order to read the information, it is necessary to detect a small change in potential appearing on the bit line connected to the capacitor via the switching transistor, so that the influence of external noise on the bit line is minimized. Although it is necessary to eliminate it, a folded bit line configuration is effective for this purpose.

In reading information from a DRAM, a potential difference between a bit line to which a memory cell to be read is normally connected and another bit line to which a dummy cell is connected is differentially amplified by a sense amplifier. However, it is a folded bit line configuration that these two bit lines are arranged so as to run adjacent to each other, and most of the external noise can be eliminated as a common mode.

On the other hand, a configuration in which these two bit lines extend to opposite sides of the sense amplifier is called an open bit line configuration.

Although the folded bit line configuration has the remarkable advantages as described above, in order to realize this, each bit line runs so as to cross all the word lines (the bit lines and the switching transistors of the memory cells). Since it is necessary to arrange a cell that couples with only half of the bit line (connected to the gate), there is a disadvantage that the occupied area is increased as compared with the open bit line configuration.

FIGS. 5A and 5B are a layout diagram and an equivalent circuit diagram showing a first example of a conventional semiconductor memory device having a folded bit line configuration.

In this example, a plurality of word lines 2 provided on a substrate and arranged in parallel to each other and at a predetermined interval, and insulated from these word lines 2 to be orthogonal to each other and arranged in parallel to each other at a predetermined interval are provided. A plurality of bit lines 3 and one of a source and a drain commonly connected to a predetermined one of the bit lines 3, and the other of the source and drain is connected to a predetermined two adjacent ones of the word lines, respectively. First and second transistors Tr1 and Tr2, and first and second capacitance elements 11 that connect one end to the other of the source and drain of the first and second transistors Tr, respectively. Each of the memory device regions 1 having a plurality of memory device regions 1 connected to the same bit line 3 is provided every two and adjacent memory device regions 1.
Each memory element region 1 connected to two word lines 2 and two bit lines adjacent to each other has one bit line 3
The two word lines 2 connected to the memory element region 1 are arranged so as not to be connected to the memory element region 1 of the other bit line 3.

FIG. 6 shows a second example of the conventional folded bit line configuration.
FIG. 4 is a layout diagram showing an example of the above.

In this example, the arrangement of the memory element region 1 is slightly different from that of the first example shown in FIG. In this example, each memory element region 1 connected to two bit lines 3 adjacent to each other is a second transistor of the memory element region 1 of the bit line 3 closer to the origin when the origin is at the lower left corner of the drawing. The word line 2 connected to the connection point of the capacitor is connected to the connection point of the first transistor and the capacitor of the memory element region 1 of the bit line 3 farther from the origin.

In these first and second examples, there is a useless area 5 between adjacent memory element areas 1 where no memory element area is formed and the word line 2 can pass through.

FIG. 7 is a layout diagram showing an example of a conventional semiconductor memory device having an open bit line configuration.

In this example, the memory element region 1 is separated only by a region necessary to separate them, and there is no useless region 5 in which a word line passes.

In these examples, the capacitance element 11
Is assumed to be a stack-type capacitor formed by electrodes deposited above the word line 2 or a trench-type capacitor using a wall surface of a hole dug in a substrate. Further, in order to make the drawing easier to see, only the connection relationship of the bit lines 3 is shown by one straight line. Also, as described above, in the folded bit line configuration, half of all the word lines 2 are
In order to allow the bit line 3 to pass through without being coupled to the open bit line configuration, an extra area (a useless area 5) is required as compared with the open bit line configuration. Assuming that all the designable minimum dimensions are all equal to a certain value F and ignoring the alignment margin, the minimum value of the area per cell that can be achieved by the conventional arrangement is 6F ² in the open bit line configuration. On the other hand, it is 8F ² in the folded bit line configuration.

[0014]

In the conventional semiconductor memory device described above, all word lines 2 are used in a folded bit line configuration.
Half pass through the bit line 3 without being coupled to the memory element region 1, so that a wasteful region 5 exists and the chip area increases. In an open bit line configuration, the wasteful region 5 disappears, but the bit is located on both sides of the sense amplifier. Since the line 3 extends, there is a disadvantage that it is vulnerable to external noise.

An object of the present invention is to be resistant to external noise,
It is another object of the present invention to provide a semiconductor memory device capable of reducing a chip area.

[0016]

According to the semiconductor memory device of the present invention, an origin is set at one corner on a substrate and an X axis and a Y axis which intersect each other through the origin are determined .
The area on the substrate which is also a positive Re, a plurality of word lines parallel and arranged at a predetermined distance from each other and the Y-axis, and wherein each word line and each other at predetermined intervals parallel to the X axis A plurality of bit lines arranged so as to intersect and intersect with each other, and one of a source and a drain is connected to a predetermined one of the bit lines.
A switching first connection common to the word lines and connecting the gates to two adjacent predetermined word lines, respectively.
And a second transistor, and a plurality of memory element regions each including a first and a second capacitance element, one end of which is connected to the other of the source and the drain of the first and the second transistor, respectively. And each memory element area
In the region, the first transistor and the first capacitor are at the origin.
On the side closer to the second transistor and the second capacitive element
Each of the plurality of word lines is arranged on a side closer to the origin.
And each of the plurality of bit lines is linear, and each of the plurality of memory element regions is connected to the same one of the bit lines, and each of the plurality of memory element regions is connected to every two adjacent word lines. Each memory element region connected to the two bit lines adjacent to each other is connected to a word line connected to a connection point of the second transistor and the capacitor in the memory element region of the bit line closer to the origin. A fold disposed to connect the connection point of the first transistor and the capacitor in the memory element region of the bit line far from the origin
In the semiconductor memory device having a bit line configuration , the X-axis
And the angle at which the Y axis intersects is an angle smaller than 90 degrees.
Each memory element area connected to the same bit line is
Source / drain connection in each memory element area
The intersection of the perpendicular drawn from the part to the Y axis and the Y axis
It corresponds to the memory element area far from the origin along the bit line.
The more the intersection, the farther from the origin
The capacitance element in the memory element area is a bit connected to the memory element.
The first capacitive element is farther from the origin
The second capacitive element is arranged and arranged on the side closer to the origin .

[0017]

According to the present invention, by shifting the angle formed between the word line (2) and the bit line (3) from 90 degrees, the area of the useless region (5) in the folded bit line configuration can be reduced. Since the chip area can be reduced and an area corresponding to the reduced useless area (5) can be allocated to the memory element area (1), the memory capacity can be increased while suppressing an increase in the chip area. it can.

[0018]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a layout diagram showing a first embodiment of the present invention.

This embodiment is different from the conventional semiconductor memory device shown in FIG. 6 in that each bit line 3 and each memory element region 1 are different from each other in that the memory element region 1 on the word line 2 closest to the origin is The bit lines 3 adjacent to the word lines 2 are fixed in the direction of the bit lines 3 farthest from the origin, so that the moving amounts gradually increase as the distance from the origin to the running direction of the bit lines 3 increases. Is arranged so that the memory element regions 1 are moved until they are aligned on a straight line.

By arranging each bit line 3 and each memory element region 1 in this manner, the useless region 5 shown in FIGS. 5 and 6 is completely eliminated, and the area per cell is reduced as shown in FIG.
6F ^2, which is equal to the limit of the open bit line configuration shown in FIG.
This area is reduced by about 25% as compared with the cases of FIGS.

FIG. 2 is a layout diagram showing a second embodiment of the present invention.

In the second embodiment, the amount of movement of the bit line 3 and the memory element region 1 is smaller than in the first embodiment, and the effect of reducing the chip area is smaller than in the first embodiment. By increasing the amount of movement of the bit line 3 and the memory element region 1, there is an advantage that the pitch of the bit line 3 can be prevented from being reduced.

Therefore, in the design, it is preferable to select an amount to move these according to factors such as a achievable bit line pitch and a desired memory element region width. Usually, it is necessary to make the width of the short side of the memory element region 1 larger than the minimum design size in consideration of the margin for alignment with the contact hole. In this case, the conventional example has a margin in the bit line pitch. Therefore, the amount of movement may be selected so that the pitch of the bit lines is the minimum value that can be realized, and an area reduction effect can be obtained according to the amount of movement.

FIG. 3 is a layout diagram showing a third embodiment of the present invention.

This embodiment is an example in which the capacitance element 11 of the memory element region 1a is protruded in the direction in which the word line 3 runs when the movement amount is smaller than the first example shown in FIG. When using a stack type capacitor in a high-density DRAM,
Forming the memory capacitance element above the bit line is advantageous in manufacturing, but for that purpose, it is necessary to prevent the connection (13) with the word line 2 from overlapping with the bit line 3. is there. In this example, the connection part (12) is shifted from the bit line 3 by extending the memory element area toward the remaining useless area in a state where the movement amount is small and the useless area does not completely disappear. ing.

FIG. 4 is a layout diagram showing a fourth embodiment of the present invention.

In this embodiment, the same effect as in the third embodiment is realized by changing the shape of the memory element region 1b obliquely.

[0029]

As described above, according to the present invention, each bit line and each memory element area are sequentially moved from the origin in the direction in which the bit line runs, so that the amount of movement is gradually increased. By disposing the semiconductor memory device in the direction parallel to each word line, the semiconductor memory device having the folded bit line structure has a feature of being resistant to external noise and exists in the conventional semiconductor memory device having the folded bit line structure. There is an effect that a useless area can be reduced and a chip area can be reduced.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing a first embodiment of the present invention.

FIG. 2 is a layout diagram showing a second embodiment of the present invention.

FIG. 3 is a layout diagram showing a third embodiment of the present invention.

FIG. 4 is a layout diagram showing a fourth embodiment of the present invention.

FIG. 5 is a layout diagram and an equivalent circuit diagram showing a first example of a conventional semiconductor memory device.

FIG. 6 is a layout diagram showing a second example of a conventional semiconductor memory device.

FIG. 7 is a layout diagram showing a third example of a conventional semiconductor memory device.

[Explanation of symbols]

 1, 1a, 1b Memory element area 2 Word line 3 Bit line 5 Useless area 11 Capacitance element 12 Source / drain connection 13 Gate connection Tr transistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 27/108 H01L 21/8242

Claims (5)

(57) [Claims] 1. An origin is set at one corner on a substrate, and an X axis and a Y axis passing through the origin and intersecting with each other are determined .
A plurality of word lines parallel to the Y-axis and arranged at a predetermined interval from each other in a region on the substrate where Y is all positive; A plurality of bit lines arranged so as to intersect and intersect with each other, and one of a source and a drain is commonly connected to a predetermined one of the bit lines, and gates are respectively connected to predetermined two adjacent to the word lines. First and second switching transistors connected correspondingly, and first and second capacitive elements connected one end to the other of the source and drain of the first and second transistors, respectively. and a plurality of the memory device region having, each memory
A first transistor and a first capacitor in the element region;
The second transistor and the second capacitor are on the side closer to the origin.
The quantity elements are respectively arranged on the side close to the origin, and the plurality of
The word line and the plurality of bit lines are each linear.
Ri, wherein the plurality of memory device regions, each memory element region connecting the same said bit line is connected to two of said word lines in and adjacent two intervals, and two of said bit lines adjacent to each other Each memory element region to be connected is connected to a word line connected to the connection point of the second transistor and the capacitor in the memory element region of the bit line closer to the origin, and to the memory element region of the bit line farther from the origin. In the semiconductor memory device having the folded bit line structure arranged to connect the connection points of the first transistor and the capacitor,
The angle at which the X axis and the Y axis intersect is smaller than 90 degrees
Angle of each memory element area connected to the same bit line.
Area in each memory element area.
Intersection of the perpendicular drawn from the IN connection part to the Y axis and the Y axis
Memory element area whose point is far from the origin along the bit line
The intersection corresponding to is located farther from the origin,
In addition, the capacitance element in each memory element area is connected to the memory element.
The first capacitive element is far from the origin for the bit line
The semiconductor memory device according to claim 1, wherein the second capacitor is disposed on a side closer to the origin . 2. A memory element located at an outermost periphery as viewed from said origin.
An arbitrary memory element area other than the area is assigned to the first memory element area.
Area, connected to the bit line connected to the first memory element area
Only One farther from the origin than the first memory element area
A memory element area adjacent to the second memory element area,
Whether the first memory element region is connected to the bit line and the origin
Memory device area connected to adjacent bit line on the far side
Wherein said second transistor in said memory element region
Gate of the first memory element region
Note connected to word line connected to transistor gate
When the memory element region is a third memory element region, the second
From the source / drain connection of the memory element area to the Y axis
The position of the point where the perpendicular line drawn and the Y axis intersect is the first
From the source / drain connection of the memory element area to the Y axis
Farther from the origin than the point where the perpendicular drawn and the Y axis intersect
In the third memory element area.
The perpendicular drawn from the rain connection to the Y axis intersects the Y axis.
Be at the same position as the point to be inserted or near the origin
The semiconductor memory device according to claim 1, wherein: (3) The planar shape of the memory element region is rectangular.
And the longitudinal direction of the rectangle is orthogonal to the word line
The semiconductor according to claim 1 or 2, wherein
Body memory device. (4) The planar shape of the memory element region is rectangular.
Ends project parallel to word lines and in opposite directions
Shape, the longitudinal direction of the rectangle is orthogonal to the word line,
The first transistor-side rectangular end is away from the origin
Direction, the rectangular end on the second transistor side is at the origin.
Project in the direction of approach, and
Connected to the first and second capacitive elements.
3. The semiconductor memory device according to claim 1 or claim 2. (5) The memory device region is referred to as a memory device region.
The first transistor side is closer than when the word lines are orthogonal.
The direction in which the second transistor side moves away from the X axis and approaches the X axis
2. The device according to claim 1, wherein the device is disposed at an angle.
Item 3. A semiconductor memory device according to item 2.