JP2771067B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit provided with a fuse which can be cut by a laser trimmer or the like in order to correct a circuit formed by a semiconductor manufacturing process.

[0002]

2. Description of the Related Art For example, in a semiconductor memory device, a redundancy decoder is provided in a row decoder in case a defect occurs in a part of a large number of formed memory cells. The redundant decoder is a circuit capable of registering a specific address by cutting a part of a plurality of fuses formed therein by a laser trimmer. The redundant decoder activates the redundant word line activating signal when the registered address is accessed, and can cause the row decoder to select the redundant word line instead of the original word line. Therefore, if the address of the defective memory cell is registered in the redundant decoder, access to this address can be switched to access to the previously provided redundant cell. This can prevent the entire semiconductor memory device from becoming defective.

FIG. 2 shows a circuit configuration of the above-mentioned redundant decoder. An internal row address determination signal is input to the determination signal input terminal 1. This internal row address determination signal is a signal which is always at the L level but is switched to the H level (active) when the row address is determined internally. Furthermore, the six address input terminal 2 _{0-2 5,} each bit of the row address are inputted.

While the internal row address determination signal is at the L level, the P-channel MOSFET 3 is turned on.
The H level is output from the output terminal 4. When the internal row address determination signal is switched to H level, N
The channel MOSFET 5 turns ON. When the row address is input to the address input terminal 2 ₀ to 2 _5, N
Channel MOSFET 6 ₀ to 6 ₁₁ half always ON next, the output line 8 via a fuse 7 _{0-7 11} becomes L level, the output terminal 4 via the inverter 9, 10 to the L level is output Become. Thus, in the state in which the redundant decoder in the row address ₀ fuse 7 is not registered to 7 ₁₁ are all connected, the redundant word line internal row address determination signal is output from the output terminal 4 when switched to the H level Activation signal is L level (inactive)
Therefore, a row decoder (not shown) decodes the row address at that time and selects a word line.

[0005] The fuse 7 _{0-7 11,} fuse 7 _0,
Two sets, such as 7 ₁ and fuses 7 ₂ , 7 ₃ , form one set and the two sets in each set correspond to the H level and the L level in each bit of the row address. one fuses 7 _{0-7 1 1} can register an arbitrary row address by cutting respectively.
Therefore, six fuses 7 ₁ , 7 ₂ ,
Assuming that 7 ₄ , 7 ₆ , 7 ₉ , and 7 ₁₁ are cut off, the corresponding (0, 1, 1, 1, 0, 0) row address is registered. The row address is the address input terminal 2 ₀
When entered in to 2 _5, N-channel MOSFET 6 ₁ becomes ON, 6 _2, 6 _{4, 6} 6, 6 _9, 6 all fuses 7 connected to _{11 1,} 7 _2, 7 _4, 7 ₆ , 7 ₉ , and 7 ₁₁ are disconnected, so that the H level of the output line 8 remains at the N-channel MOSFET even if the internal row address determination signal is switched to the H level and the N-channel MOSFET 5 is turned on.
11, the redundant word line activating signal from the output terminal 4 remains at the H level (active). Therefore, when the H level of the redundant word line activating signal is maintained, the row decoder ignores the row address at that time and selects the redundant word line. Further, if the row address other than the above to the address input terminal 2 _{0-2 5} is input, a fuse 7 ₀ uncut, 7 _3, 7 _5, 7 _7, 7 _8, 7 N to connect to ₁₀ channel _{MOSFET6 0, 6 3, 6 5} , 6 7, 6 8, since any of the 6 ₁₀ always becomes ON, the redundant word line activating signal becomes L level, the row decoder, as a row address at that time Decoding is performed to select a word line.

As a result, when a row address is registered, the redundant decoder activates the redundant word line activation signal when the internal row address determination signal switches to the H level only when the row address is input. Becomes active, so that defective memory cells can be replaced.

[0007] shows the conventional layout on the chip of the circuit portion of the fuse 7 _{0-7 11} in the redundant decoder (region in FIG. 2 C) in FIG.

The fuses 70 to 711 are connected to the contact 12
Each of the wiring patterns is formed by a conductive polysilicon layer formed between _{0 to} 12 ₁₁ and the contact portions 13 _{0 to} 13 ₁₁ . In addition, one contact portion 12 ₀
12 ₁₁ are respectively connected to the respective drains of the N-channel MOSFET 6 ₀ to 6 ₁₁ in FIG. 2 through the metal wiring 14 _{0-14 11,} the other contact portion 13 _0-1
All 3 ₁₁ are connected to the output line 8. Further, the contact portion 12 _{0-12 11} in the fuse 7 _{0-7 11}
Near the center between the contact portions 13 _{0 to} 13 ₁₁ ,
It is surrounded by a guard ring 15 made of a metal layer. Then, the laser trimmer is used for the guard ring 15
It is adapted to cut each fuse 7 _{0-7 11} appropriately by irradiating a laser spot on the area shown in the drawing D of the inner.

[0009] Therefore, the circuit portion of the conventional fuse 7 _{0-7 11} shown in region C of FIG. 2, on the chip shown in FIG. 3, the guard ring 15 and 12 of the contact portion 1
3 _{0-13 11} regions to have a certain width around the E
Will occupy the range.

[0010]

[SUMMARY OF THE INVENTION However, in the conventional layout, the output line 8 by the other end 12 is drawn out from the guard ring 15 respectively contact portions 13 ₀ to 13 ₁₁ for each fuse 7 _{0-7 11} to be connected, the circuit portion of the fuse 7 _{0-7 11} becomes too wide area E occupied on the chip, a problem that becomes an obstacle to miniaturization of the semiconductor memory device has occurred. This problem is not limited to the semiconductor memory device, but is common to all semiconductor integrated circuits in which a plurality of fuses are formed.

In view of the above circumstances, the present invention reduces the area occupied by the circuit portion of the fuse by connecting the other end of the fuse having one end connected to each circuit to a common line in the guard ring. It is an object of the present invention to provide a semiconductor integrated circuit capable of performing the above.

[0012]

According to the present invention, there is provided a semiconductor integrated circuit in which a plurality of fuses having one end connected to each circuit and the other end having a common potential are formed in a region within a guard ring. A common line serving as a common potential is formed through a region in the guard ring,
The other ends of the plurality of fuses are integrally connected to the common line in the guard ring, thereby achieving the above object.

[0013]

One end of each fuse is connected to each circuit via a contact outside the guard ring. The other end of each of the fuses is integrally connected to a common line in a region within the guard ring. Therefore, it is sufficient to draw one end of this common line out of the guard ring and connect it to a circuit having a common potential via one contact portion.
For this reason, the circuit portion of the fuse is a guard ring and this 1
It is only necessary to occupy a region having a certain width around each of the contact portions.

As a result, according to the present invention, since the other end of the fuse is connected to the circuit of the common potential by one contact portion via the common line, the area occupied by the circuit portion of the fuse on the chip Can be reduced.

[0015]

The present invention will be described below with reference to examples.

FIG. 1 shows an embodiment of the present invention and is a diagram showing a layout of a circuit portion of a fuse on a chip. Components having the same functions as those of the conventional example shown in FIG. 3 are denoted by the same reference numerals. The circuit portion of the fuse in the redundant decoder of the semiconductor memory device shown in FIG. 2 will be described.

One common line 16 is formed on the chip by a conductive polysilicon layer. Further, from both sides of the common line 16, six wiring patterns of the same polysilicon layer are respectively drawn out to both sides, and 1
Two fuses 70 to 711 are formed.

[0018] One end side of the 12 fuses 7 _{0-7 11} is connected to the twelve contact portions 12 ₀ to 12 _11, respectively. Contact portion 12 _{0-12 11,} N-channel M to one end side of each fuse 7 _{0-7 11} in FIG. 2
OSFET6 ₀ ~6 ₁₁ is for connecting to metal interconnect 14 _{0-14 11} connected with drains of. The other end of the fuse 7 _{0-7 11,} as described above, will be connected to one common line 16 which is integrally formed as a wiring pattern of the same polysilicon layer. One end of the common line 16 is connected to one contact portion 13. The contact portion 13 is for connecting one end of the common line 16 to the output line 8 shown in FIG.

The vicinity of the connecting portion between the fuse 7 _{0-7 11} of the single common line 16 and 12 is surrounded by a guard ring 15 forming a pattern of one metal layer to a square ring. Accordingly, the fuse 7 _{0-7 11} connected to one end of each of the contact portions 12 _{0-12 11} outside of the guard ring 15, the other end guard rings 1
The common line 16 extends to a region inside the common ring 16, and one end of the common line 16 extends to the outside of the guard ring 15, and is connected to the contact portion 13 here. The guard ring 15 is intended to protect the fuse 7 _{0-7 11} to be cut by the laser trimmer, an insulating layer (not shown) between the layers of the polysilicon layer of the fuse 7 _{0-7 11} and the common line 16 It is formed.

The circuit portion of the fuse 7 _{0-7 11} configured as described above, on the chip, occupying a range of regions illustrated A which gave a certain width around the guard ring 15 and one contact portion 13 Will be. Further, laser trimmer, each fuse 7 _{0-7 1} by irradiating a laser spot on the area shown in the drawing B of the guard ring 15
₁ is appropriately cut. That is, as the fuse 7 _0, 7 ₁ and the fuse 7 _2, 7 one set of two and so _3, the registration of the row address by cutting one fuse 7 _{0-7 11} either for each set Will do. Therefore, when the registered row address to the address input terminal 2 _{0-2 5} of the redundancy decoders in FIG. 2 is input, the redundant word line from the output terminal 4 when the internal row address determination signal is switched to H level The activation signal can be at H level (active). As a result, the present embodiment, the other end of the fuse 7 _{0-7 11} common line 16
Since is connected to the output line 8 by a single contact portion 13 via the approximately than conventional region E shown a region A circuit portion of the fuse 7 _{0-7 11} occupies on the chip in FIG. 3 The size can be reduced to two thirds.

[0021]

As is apparent from the above description, according to the present invention, the area occupied on the chip by the circuit portion of the fuse cut by the laser trimmer or the like can be reduced, so that the size of the semiconductor integrated circuit can be reduced. Will be able to contribute to

[Brief description of the drawings]

FIG. 1, showing an embodiment of the present invention, is a diagram showing a layout on a chip of a circuit portion of a fuse in a redundant decoder.

FIG. 2 is a circuit diagram showing a configuration of a redundant decoder in the semiconductor memory device.

FIG. 3 shows a conventional example, and is a diagram showing a layout on a chip of a circuit portion of a fuse in a redundant decoder.

[Explanation of symbols]

7 _{0 to} 7 ₁₁ Fuse 8 Output line 14 _{0 to} 14 ₁₁ Metal wiring 15 Guard ring 16 Common line

Claims (1)

(57) [Claims] In a semiconductor integrated circuit in which a plurality of fuses having one end connected to each circuit and the other end having a common potential are formed in a region within a guard ring, a common line having a common potential is formed within the guard ring. And the other end sides of the plurality of fuses are integrally connected to the common line in the guard ring.