JP2770902B2 - Convolution arithmetic circuit with feedback and systematic encoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to a field.
Feasible function on F (realizablefunction)
a convolutional operation circuit with feedback and a systematic encoder represented by ion), which are used particularly for circuits for digital signal processing, such as an encoder / decoder in a communication device. The present invention relates to an arithmetic circuit and a systematic encoder having a circuit configuration for reducing the number of gate stages in a simple circuit as a whole.

[0002]

2. Description of the Related Art Here, a field F is an original set in which four arithmetic operations of addition, subtraction, multiplication and division can be defined. Body (fi
eld) An F having a finite number of elements is called a Galois Field, and is written as GF (p). Here, p is a prime number, and the element of GF (p) is {0,
1, ..., p-1}. The realizable function is a function that can be realized by a linear system, and is a function given by a fractional expression using a polynomial including a constant term as a denominator.

Conventionally, various circuits constituting such a function have been proposed, but no measures have been taken with respect to the large number of parts and the accompanying delay in signal transmission. FIG. 3 is a configuration diagram of a conventional convolution arithmetic circuit with feedback representing a Galois field G, and FIG. 4 is a configuration diagram of the convolutional systematic encoder.
In the figure, α is a convolution operation circuit with feedback, β is a convolutional encoder with feedback, 1A, 1B, 7
A, 7B, 7C are XOR circuits as gate circuits, 1C, 7
D is an XOR circuit as a final output gate circuit, 2A, 2B,
8A, 8B and 8C are shift registers as time delay output circuits, 3 and 6 are feedback signals, 4A, 5A and 5B are primary input signals, 4B and 5E are final output signals, 5C and 5D.
Is a primary output signal, and S1 and T1 are branch output points.

A conventional convolution arithmetic circuit α with feedback represented by a realizable function on a Galois field GF (2) is shown in FIG. 3 and described below. As an example, consider the following function G: G = (1 + D ² ) / (1 + D + D ² ) Here, the symbol D means a delay of one unit time, and the delay of n unit time is represented by a power D of D. FIG. 3 shows an arithmetic circuit with feedback for realizing the function G.

The XOR circuits 1A, 1B and 1C in FIG.
This is a circuit that performs addition on GF (2) (in this case, XOR
Is represented by (+), X + X = 0, X + 0 = X, 0+
Since 0 = 0, X (+) X = 0, X (+) 0 =
X, 0 (+) 0 = 0, etc.), and a gate circuit that outputs an exclusive OR of the input signals. The shift register is timed delay output circuit for outputting delayed one unit time the input signal, representative of the D ⁿ by continuous input. Feedback signal 3 and final output signal 4B in FIG.
Have the same contents. The number of shift registers is the maximum order of the integer polynomial included in the realizable function, and is 2 in this example.

The basic connection structure of the convolution operation circuit α is composed of XOR circuits 1A and 1B and shift registers 2A and 2B
Is connected continuously by repeating the order twice, and finally XOR
The circuit 1C is connected, and the final output signal 4B and the feedback signal 3 are extracted therefrom. Also, regarding the primary input signal 4A and the feedback signal 3, there are three XOR circuits 1
Where A, 1B, and 1C are connected is determined as follows.

The primary input signal 4A is applied to the XOR circuits 1A, 1
B0 and C are connected to C0 and C respectively.
It is represented by 1, C2, and is 1 when connected, and 0 otherwise. At this time, the numerator of the function G, 1 + D ² and C
0 + C1 * D + C2 * D 2 is connected to be equal. That is, C0 = 1, C1 = 0, and C2 = 1. Therefore, the primary input signal 4A is input-connected to the XOR circuit 1A and the XOR circuit 1C.

[0008] The feedback signal 3 is similarly considered, and
When it is expressed by E0, E1, and E2 whether or not the circuit is connected to the R circuits 1A, 1B, and 1C, respectively, the denominator of the function G, 1
+ D + D ² and E0 + E1 * D + E2 * D 2 is connected to be equal. That is, E0 = 1, E1 = 1, E2 = 1
Becomes Therefore, the feedback signal 3 is connected to the XOR circuit 1A, the XOR circuit 1B, and the XOR circuit 1C. The feedback signal 3 is connected to the output of the XOR circuit 1C at the output branch point S to take out the output signal 4B, and the other connections are connected back to the inputs of the XOR circuits 1A and 1B, respectively.

As shown in FIG. 4, a conventional convolutional systematic encoder with feedback β is applied to a convolutional systematic encoder having a coding rate of 2/3 and a constraint length of 4 as an example. The rate 2/3 convolutional systematic encoder β has three primary and final output signal bits for two primary input signal bits. The primary output signals 5C and 5D are the primary input signals 5A and 5B, respectively, and the final output signal 5E is also called a parity signal and is represented by a fraction of the following polynomial. (Parity signal 5E) = ((1 + D + D 3) * ( primary input signal ^{5A) + (1 + D 3} ) * ( primary input signal 5B))
/ (1 + D ² + D ³ )

That is, the parity signal 5E is described by a feasible function relating to the symbol D representing a delay of one unit time. Therefore, an arithmetic circuit for realizing this function includes the primary input signals 5A and 5A.
A parity signal can be generated from B. The number of shift registers is a realizable function (realizable f
The maximum degree of the integer polynomial included in the (unction), which is 3 in this example.

In order to realize the conventional systematic encoder β, the primary input signals 5A and 5B and the feedback signal 6
To which XOR circuit is connected is realized by the connection shown in FIG. 4 in the same manner as described above. First of all,
Three sets of XOR circuits 7A and shift registers 8A, 7B and 8
B, 7C and 8C are connected in series in a multi-stage sequence, and finally, an XOR circuit 7D as a final output gate circuit is connected to output
Extract E (parity signal). Individual primary input signal 5
Expressions for A and 5B and the parity signal 5E are determined as follows.

The polynomial of D relating to the primary input signal 5A, D ³
From the coefficients (0 or 1) of + D + 1 = 1 × D ³ + 0 × D ² + 1 × D + 1, the primary input signal 5A and the XOR circuit 7
A, 7B, 7C, 7D are determined. That is, the primary input signal 5A is connected to the XOR circuit 7A, the XOR circuit 7C and the XO circuit 7C.
Input connected to R circuit 7D.

The polynomial of D relating to the primary input signal 5B, D ³
+ 1 = 1 × D ³ + 0 × D ² + 0 × D + 1 (0
Or 1), the primary input signal 5B and the XOR circuit 7A,
The connection with 7B, 7C, 7D is determined. That is, the primary input signal 5B is input-connected to the XOR circuits 7A and 7D.

The denominator in the function of the parity signal 5E, D
³ + D ² + 1 = 1 × D ³ + 1 × D ² + 0 × D + 1 From the respective coefficients (0 or 1), the feedback signal 6 and XO
The connection to the R circuits 7A, 7B, 7C, 7D is determined. Therefore, the parity signal 5E is connected to the output of the XOR circuit 7D and taken out, and is fed back to the XOR circuit 7A and the XOR circuit 7B.

[0015]

Focusing on the feedback signal 3 of the convolution circuit α according to the prior art shown in FIG. 3 as described above, the shift register 2B has a secondary output signal d and a primary input signal 4A. The feedback signal 3 is generated through the XOR circuit 1C. Further, the XOR circuit 1A is obtained from the feedback signal 3 and the primary input signal 4A.
And the feedback signal 3 and the secondary output signal b of the shift register 2A through the XOR circuit 1B.
Until the secondary input signal c is generated, the signal has passed through a total of two XOR circuits 1A and 1B.
An output signal d is output. Passing through the XOR circuits 1C and 1A until the secondary input signal a is determined and passing through the XOR circuits 1C and 1B until the secondary input signal C is determined requires two stages of passage time.

Similarly, in FIG. 4, the XOR circuit 7D passes the secondary output signal j of the shift register 8C, the primary input signal 5A, and the primary input signal 5B from the XOR circuit 7D to generate the feedback signal 6 and the final output signal 5E. Further, the feedback signal 6, the primary input signal 5A, and the primary input signal 5B are XO
A shift register 8A secondary input signal e is generated from the R circuit 7A. The XOR circuit 7B passes the feedback signal 6 and the secondary output signal f of the shift register 8A to generate a secondary input signal g of the shift register 8B. The secondary output signal h and the primary input signal 5A of the shift register 8B are converted to an XOR circuit. 7C, the secondary input signal i of the shift register 8C is reproduced.

For this reason, the shift registers 8A, 8B, 8
To determine the C secondary input signal e, XOR circuits 7D and 7A
The XOR circuit 7D
And 2B, and two stages of the XOR circuit 7C are required to determine the secondary input signal i. This is one of the factors that hinders the speeding up of the arithmetic circuit β. Furthermore, this X
If the number of OR circuits can be reduced, the same operation circuit can be realized with a small number of logic elements. Therefore, it is desired to increase the speed of the arithmetic circuit and reduce the number of logic elements. Here, the present invention reduces the number of parts in view of the problems of the related art,
An object of the present invention is to provide a high-speed convolution circuit with feedback and a systematic encoder with little delay.

[0018]

The above object can be attained by adopting the following novel characteristic constitution means of the present invention. That is, the first characteristic of the present invention is that each set represented by a feasible function G on a certain field F and composed of a gate circuit and a time delay output circuit is the maximum order of an integer polynomial included in the feasible function G. A final output gate circuit for a final output signal is connected to the timed delay output circuit of the final stage set in series multiple stages, and a primary input signal and a feedback signal having the final output gate circuit as a branch output point are realized as described above. In the convolution operation circuit with feedback that can be selectively input to the gate circuit in accordance with the respective expressions of the numerator and denominator of the possible function G, the relationship between the secondary input signal and the secondary output signal of the time delay circuit at each stage is represented by While maintaining the same, the feasible function G is equivalently transformed, and the primary input signal and the feedback signal corresponding to the respective expressions of the numerator and the denominator of the transform feasible function G. A tatami mat with feedback that reduces the number of necessary gate circuits in a signal generation process required for the feedback signal by a series of circuit connection changes in which the branch output point position of the feedback signal is shifted simultaneously with the selection input change to the gate circuit. Embedded arithmetic circuit.

A second feature of the present invention is a convolution operation circuit with feedback, wherein the feasible function G in the first feature is represented on a Galois field GF (p).

A third feature of the present invention is that the first or the second
The gate circuit and the time delay output circuit in the feature of (1) are a convolution operation circuit with feedback, which is an XOR circuit and a shift register, respectively.

A fourth feature of the present invention is that each set represented by a feasible function G on a certain field F and composed of a gate circuit and an on-time delay output circuit is a maximum order of an integer polynomial included in the feasible function G. And a final output gate circuit for a final output signal is connected to the final delay signal output circuit of the last stage, and a primary input signal and a feedback signal having the final output gate circuit as a branch output point are realized as described above. In the convolutional system encoder with feedback that can be selectively input to the gate circuit in accordance with the respective equations of the numerator and denominator of the possible function G, the secondary input signal and the secondary output signal of the time delay output circuit of each stage are provided. While maintaining the same relationship, the feasible function G is equivalently transformed, and the conversion feasible function G
In response to the respective equations of the numerator and denominator, the primary input signal and the feedback signal are selectively input to the gate circuit, and at the same time, the feedback is performed by a series of circuit connection changes for shifting the position of the branch output point of the feedback signal. A convolutional encoder with feedback, wherein the number of necessary gate circuits is reduced in a signal generation process required for a signal.

A fifth feature of the present invention is a convolutional system encoder with feedback, wherein the feasible function (G) in the fourth feature is expressed on a Galois field GF (p).

The sixth feature of the present invention is the fourth or fifth aspect.
The gate circuit and the time delay output circuit in the feature (1) are a convolutional encoder with feedback, which is an XOR circuit and a shift register, respectively.

[0024]

According to the present invention, the XOR circuit as a gate circuit in the middle of a shift register as a time delay output circuit is omitted in the convolution operation by taking the above-described means, and the primary input signal and the feasible function are used. Since the feedback signals are switched, the number of gates is reduced while maintaining the same relationship between the secondary input signal and the secondary output signal of the shift register.

[0025]

(Embodiment 1) A first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration diagram of a convolution operation circuit with feedback according to the present embodiment. In the figure, γ is a feedback convolution operation circuit of this embodiment, 9A and 9B are shift registers, 10A is an XOR circuit, 10B is an XOR circuit as a final output gate circuit, and S2 is a branch output point.

As shown in FIG. 1, the convolution operation circuit γ of this embodiment realizes the functions G and G = (1 + D ² ) / (1 + D + D ² ) as in the conventional circuit. This embodiment is obtained by converting the conventional circuit shown in FIG. 1 and is semantically equivalent, and shows how the circuit shown in FIG. 3 is converted.

Here, the basic configuration is such that two sets of shift registers 9A and XOR circuits 10A, 9B and 10B are connected in series in two stages according to the order of the feasible function G,
The primary input signal 4A is input to the circuit 10B, and the final output signal 4B is extracted. The feedback signal 3 connected to the XOR circuit 1C final output signal 4B in FIG. 3 is changed so as to be connected to the secondary output signal d of the shift register 2B. In the present embodiment, the feedback signal 3 is extracted from the secondary output signal d of the last set of the shift register 9B.

In order to make the secondary input signals a and c of the shift registers 9A and 9B equivalent to the secondary input signals a and c of the shift registers 2A and 2B of FIG. 3 according to the basic configuration of FIG. And the feedback signal 3 are respectively input to the XOR circuits 10A and 10B corresponding to the feasible function. When the XOR circuit is represented by (+), the secondary input signals a and c of the shift registers 2A and 2B in FIG.
Can be described by the following equations. (Signal a) = (primary input signal 4A) (+) (feedback signal 3) = (primary input signal 4A) (+) (shift register 2B secondary output signal d) (+) (primary input signal 4
A) = (Shift register 2B secondary output signal d)

(Signal c) = (secondary output signal b of shift register 2A) (+) (feedback signal 3) = (secondary output signal b of shift register 2A) (+) (primary input signal 4)
A) (+) (Shift register 2B secondary output signal d)

The relationship above is that in FIG. 1, the secondary input signal a of the shift register 9A is directly connected to the secondary output signal d of the shift register 9B, and the secondary input signal c of the shift register 9B is connected to the secondary input signal c of the shift register 9A. The next output signal b, the primary input signal 4A, and the secondary output signal d of the shift register 2B are fed back and connected through the XOR circuit 10A.

Paying attention to the feedback signal 3 of the convolution operation circuit γ in FIG. 1 of the present embodiment, the feedback signal 3 is generated from the secondary output signal d of the shift register 9B, and the feedback signal 3 is used to generate the secondary of the shift registers 9A and 9B. One XOR circuit 10 until the input signals a and c are generated
Since only A is passed, shift registers 9A and 9B
It can be seen that the time until the secondary input signals a and c are determined is reduced.

(Embodiment 2) A second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 2 is a configuration diagram of the systematic encoder with feedback according to the present embodiment. In the figure, δ is a systematic coding circuit with feedback, 11A, 11B and 11C are shift registers, 12A and 12B are XOR circuits, 12C is an XOR circuit as a final output gate circuit, and T2 is a branch output point. The systematic encoder δ with feedback of the present embodiment is shown in FIG.
This is equivalently converted from FIG. 4, and the conversion procedure is shown below.

As in the first embodiment, the basic configuration is as follows.
Shift register 11A and XOR circuit 12 according to the order
A, 11B and 12B, 11C and 12C are connected in three stages in series, a feedback signal 6 is extracted from the secondary output signal j of the last set of shift registers 11C, and the XOR circuit 1
The primary input signals 5A and 5B are input to 2C and the final output signal 5E (parity signal) is extracted.

XOR circuit 7D in FIG. 4 final output signal 5E
The feedback signal 6 is connected to the secondary output signal j of the shift register 11C and extracted. The secondary input signals e, g, i of the shift registers 11A, 11B, 11C are converted to the shift registers 8A, 8B,
8C, the primary input signals 5A and 5B and the feedback signal 6
Whether to input to the OR circuits 12A, 12B, and 12C is changed corresponding to each feasible function.

The signals e, g, and i are described in the same manner as in the first embodiment. (Signal e) = (Primary input signal 5A) (+) (Primary input signal 5B) (+) (Feedback signal 6) = (Primary input signal 5A) (+) (Primary input signal 5B) (+) (Shift register 8C secondary output signal j) (+) (primary input signal 5
A) (+) (primary input signal 5B) = (shift register 8
C secondary output signal j)

(Signal g) = (Shift register 8A secondary output signal f)
(+) (Feedback signal 6) = (shift register 8)
A secondary output signal f) (+) (secondary output signal j of shift register 8C) (+) (primary input signal 5A) (+) (primary input signal 5B) (signal i) = (primary input signal 5A) ( +) (Secondary output signal h of the shift register 8B)

Accordingly, the secondary input signal e of the shift register 11A is directly connected to the secondary output signal j of the shift register 11C, and the secondary input signal g of the shift register 11B is connected to the primary input signal 5A, the primary input signal 5B and the shift register 11B. 11
The A secondary output signal f and the shift register 11C secondary output signal j are connected through the XOR circuit 12A. The shift register 11C secondary input signal i is obtained by converting the shift register 11B secondary output signal h and the primary input signal 5B into an XOR circuit 12B.
Connect through. According to this, the connection shown in FIG. 2 is obtained.

When comparing FIG. 2 of the present embodiment with the conventional connection configuration of FIG. 4, focusing on the feedback signal 6 of the systematic encoder δ of FIG. 2, the secondary output signal j of the shift register 11C
, And the number of XOR circuits that pass from the feedback signal 6 until the shift register 11A, 11B secondary input signal e, g is generated is reduced by one stage as compared with FIG. 4 of the prior art. According to the present embodiment, it can be seen that the signal determination time is shortened and the logic elements are saved.

[0039]

According to the present invention, a certain body (fi)
eld) Realizable function on F
In the arithmetic circuit with feedback and the systematic encoder represented by the function, the number of gates can be reduced, the logic elements can be saved, and the arithmetic circuit can be speeded up. The present invention has excellent practicality and utility such as being applicable to a wide range of circuits for digital signal processing, such as an encoder / decoder in the communication apparatus shown in the embodiments.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of the present invention, G = (1 + D ² ) / (1)
+ D + D ² ) is a configuration diagram of a convolution operation circuit with feedback, representing + D + D ² ).

FIG. 2 is a configuration diagram of a convolutional system encoder having a coding rate of 2/3 and a constraint length of 4 according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a conventional convolution operation circuit with feedback that represents G = (1 + D ² ) / (1 + D + D ² ).

FIG. 4 is a configuration diagram of a conventional convolutional systematic encoder having a coding rate of 2/3 and a constraint length of 4;

[Explanation of symbols]

α, γ: Convolution operation circuit β, δ: Convolutional system encoder 1A, 1B, 1C, 7A, 7B, 7C, 7D, 10A, 10B, 12A, 12B, 12C: XOR circuit 2A, 2B, 8A, 8B , 8C, 9A, 9B, 11A,
11B, 11C shift register 3, 6 feedback signal 4A, 5A, 5B primary input signal 4B, 5E final output signal 5C, 5D primary output signal a, c, e, g, i secondary input signal b , D, f, h, j ... secondary output signals S1, S2, T1, T2 ... branch output points

Continuation of the front page (56) References JP-A-5-183448 (JP, A) JP-A-6-104942 (JP, A) IEICE Technical Report, Vol. 88, No. 59, p. 29-34 [IT88-13], "Syndrome Sequential Decoding Using Feedback Convolutional Tissue Codes" IEICE Technical Report, Vol. 89, No. 61, p. 31-36 [IT89-5], "Study of convolutional code with feedback", IEEE TRANSACTIONS ON INFORMATION THE EORY, VOL. IT-16, NO. 6, (NOV) 1970, p. 720-738, "CONVOLUTIONAL CODE S I: ALGEBRAIC Structure" IEEE TRANSACTIONS ON INFORMATION THE EORY, VOL. IT-28, NO. 1, (JAN) 1982, p. 55-67, "CHANNEL CODING WITH MULTILEVEL / PHASE SIGNALS" Proceedings of the 1988 IEICE Spring National Convention, Basic Boundary [Volume A-1] p. 1-182 [A-181] IEICE Transactions A, Fundamental Boundary, VOL. J73-A, NO. 2, pp. 306-313, “Syndrome Sequential Decoding Using Feedback Convolutional Codes” (58) Fields investigated (Int. Cl. ⁶ , DB name) H03M 13/12 H04L 1/00 H04L 25 / 00 H04L 27/00

Claims (6)

(57) [Claims] 1. A series represented by a feasible function G on a certain field F and composed of a gate circuit and an on-time delay output circuit is connected in series in a number corresponding to the maximum order of an integer polynomial included in the feasible function G. A final output gate circuit for a final output signal is connected to the time delay output circuit of the final stage, and a primary input signal and a feedback signal having the final output gate circuit as a branch output point are the numerator of the feasible function G. In the convolution operation circuit with feedback that can be selectively input to the gate circuit in accordance with each of the denominator equations, the relation between the secondary input signal and the secondary output signal of the time delay circuit of each stage is kept the same. The feasible function G is equivalently converted, and the primary input signal and the feedback signal are converted to the gate circuit in accordance with the numerator and denominator of the conversion feasible function G. Wherein the number of gate circuits required in the signal generation process required for the feedback signal is reduced by a series of circuit connection changes for shifting the position of the branch output point of the feedback signal simultaneously with the selection input change. Operation circuit. 2. The convolution operation circuit with feedback according to claim 1, wherein the realizable function G is represented on a Galois field GF (p). 3. The convolution operation circuit with feedback according to claim 1, wherein the gate circuit and the time delay output circuit are an XOR circuit and a shift register, respectively. 4. A series represented by a feasible function G on a certain field F and composed of a gate circuit and an on-time delay output circuit is connected in series in multiple stages of the maximum degree of an integer polynomial included in the feasible function G. A final output gate circuit for a final output signal is connected to the time delay output circuit of the last stage, and a primary input signal and a feedback signal having the final output gate circuit as a branch output point are a numerator and a denominator of the feasible function G. In the convolutional system encoder with feedback that can be selectively inputted to the gate circuit in accordance with the respective equations, the relation between the secondary input signal and the secondary output signal of the time delay output circuit of each stage is kept the same. The feasible function G is equivalently converted, and the primary input signal and the feedback signal are gated in accordance with the numerator and denominator of the conversion feasible function G. With the feedback, the number of necessary gate circuits in the signal generation process required for the feedback signal is reduced by a series of circuit connection changes that shift the position of the branch output point of the feedback signal at the same time as the selection input is switched to the circuit. Convolutional tissue encoder. 5. The realizable function (G) is a Galois field GF
5. The convolutional encoder with feedback according to claim 4, characterized in that: 6. The convolutional system encoder with feedback according to claim 4, wherein the gate circuit and the time delay output circuit are an XOR circuit and a shift register, respectively.