JP2754424B2 - Semiconductor integrated device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a semiconductor integrated device in which a MOS field effect transistor (MOSFET) is integrated, for example, a semiconductor integrated device for driving an LCD (Liquid Crystal Display). In the drawings, the same reference numerals indicate the same or corresponding parts. The logic or level “H”, “L” is simply H, L
Shall be written.

[Prior art]

FIG. 5 shows a configuration example for one scanning output point of a general circuit (scan driver) for driving the scanning lines of the simple matrix of the LCD. FIG. 6 shows a waveform example of each signal in FIG. 5 (that is, relating to the n-th scanning output point), and FIG. 7 shows a truth table for the common drive signal COMn in FIG. In FIG. 5, V0 to V5 and VEE are DC power supplies for driving the liquid crystal, and their potentials have a relationship of V0>V1>V5> VEE. In this case, it is assumed that V0-VEE = 24V and driving is performed at a duty of 1/200. If it is determined that ΔV = 24V / 15, V0−V1 = 1 · ΔV V1−V5 = 22 · ΔV V5−VEE = 1 · ΔV, which is generally in the relationship of V0, V1≫V5, VEE. In FIG. 5, 1 (1-0,1-1), 2 (2
−5, 2-E) are select P-channel MOSFETs and select N-channel MOSFETs as switches for selecting the respective power supply potentials and supplying them to the select lines SL and NSL. (Hereinafter, the MOSFET is also simply abbreviated as a transistor.) Here, a select potential V0 or VEE is supplied to the select line SL in accordance with the values of H and L of the AC signal DF, and the select line NSL is similarly supplied. Potential V1 or V when ratio is selected
5 is supplied. Next, 3 (3-1, 3-2) and 4 (4-1, 4-2) select output potentials of the selector line SL or NSL and output them as a common drive signal COMn.
This is an output N-channel MOSFET. 6 is data DT for sequentially selecting scanning lines (therefore, DT is selected data for the n-th scanning output point shown in FIG. 5).
and a level shift circuit 5 for converting selection data DTn as an output signal of (0,5V) of the shift register into (0,30V) selection data Qn, n suitable for driving the liquid crystal. It is. Next, the operation of FIG. 5 will be described with reference to FIG. 6 and FIG. When the AC conversion signal DF is L, the select transistors 1-1 and 2-E are turned ON (the other select transistors 1 and 2).
−0 and 2-5 are OFF), and the potentials VEE and V1 are supplied to the select lines SL and NSL, respectively. On the other hand, while the n-th scanning output point is not selected, the selection data DTn is L, and thus the selection data Qn output from the level shift circuit 5 is L (▲
▼ is H), which allows the output transistor 3
−2, 4-2 is ON (other output transistors 3-1 and 4-1 are
OFF), and the potential V as the common drive signal COMn
1 is output. Next, when the selection data DTn becomes H at the point of time t1 in FIG. 6, when the n-th scanning output point is selected, the selection data Qn output from the level shift circuit 5 becomes H (▲
▼ is L), and this time the output transistors 3-1 and 4-
1 turns ON (3-2, 4-2 turns OFF), and the potential VEE is output as the common drive signal COMn. On the other hand, when the AC signal DF is H, the select transistors 1-0 and 2-5 are turned on (1-1 and 2-E are turned off), and the potentials V0 and V5 are supplied to the select lines SL and NSL, respectively. Is done. In this case, when the selection data DTn and Qn are not selected (at L), as described above, the output transistors 3-2 and 4-4 are output.
Since −2 is ON (3-1 and 4-1 are OFF), the potential V5 is output as the common drive signal COMn, and the time t2 in FIG.
When the selection data DTn and Qn reach the selection level as shown in FIG.
), The output transistors 3-1 and 4-1 are ON.
(3-2, 4-2 are OFF) and the common drive signal CO
The potential V0 is output as Mn.

[Problems to be solved by the invention]

In the circuit shown in FIG. 5, a P-channel output transistor 3-1 and an N-channel output transistor 4 are provided so that the two fluctuating potentials V0 and VEE of the select line SL can both be output as a common drive signal COMn with low impedance. A switching circuit in parallel with -1 is used. This is because the gate of the P-channel transistor 3-1 is set to L and the gate of the N-channel transistor 4-1 is set to H
As a result, the transistors 3-1 and 4-1 are turned ON. At this time, if the potential of the select line SL is V0, P
The channel transistor 3-1 has a large and constant potential between its gate and source, and therefore has a low impedance. On the other hand, the N-channel transistor 4-1 has a gate-source voltage whose output voltage is equal to the output voltage to the load. Only lower,
If the potential of the select line SL is VEE, on the other hand, if the potential of the select line SL is VEE, the potential between the gate and the source of the P-channel transistor 3-1 may become high impedance depending on the load side voltage. , N-channel transistor 4-1 has a large and constant gate-source voltage and low impedance. For the same reason, the P-channel transistor 3-2 and the N-channel transistor 4-2 are connected in parallel so that the two fluctuating voltages V1 and V5 of the select line NSL can be output as the common drive signal COMn with low impedance. A switching circuit is used. However, using a parallel circuit of two transistors of P-channel and N-channel in one switching circuit in this way is contrary to the general requirements for IC circuits, such as a demand for reduction in chip size or an increase in driving capability. There is a need for improvement. Therefore, an object of the present invention is to provide a semiconductor integrated circuit that can solve this problem.

[Means for Solving the Problems]

In order to solve the above-mentioned problem, the circuit of the present invention has a “first
Of multiple potentials (V0, V1, etc.)
A first line (such as a select line SL1) to be selected and applied (via a channel transistor 1 or the like) and a second plurality of potentials (such as V5 and VEE) lower than any of the first potentials A second line (such as a select line SL2) to be selected and applied (via a select N-channel transistor 2 or the like) and a P-channel MO having a source connected to the first line.
An SFET (such as an output P-channel transistor 3) and an N-channel MO having a source connected to the second line
An SFET (such as an output N-channel transistor 4), and the drains of the P-channel and N-channel MOSFETs are connected in common to provide an output terminal (such as a common drive signal COMn); The respective gates of the MOSFETs are connected in common, and the common gate is driven such that one of the two MOSFETs is turned on and the other is turned off, and the first or second potential is taken out from the output terminal. ”.

[Operation]

The combination of the potential levels output to the select lines was changed, and for each scanning output point, a total of four P-channel transistors and one N-channel transistor were used in a total of four parallel circuits. In the present invention, only two transistors, one for each of the P-channel and the N-channel, are required in the present invention. And for this,
An EXOR circuit is added to the gate circuit that drives these two transistors.

【Example】

An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a circuit diagram showing a configuration of a main part of a scan driver as an embodiment of the present invention, corresponding to FIG. 5, and FIG. 2 shows an embodiment of a configuration of the EXOR circuit of FIG. FIG. 3 is a waveform diagram of each signal for explaining the operation of FIG. 1 and corresponds to FIG. In FIG. 1, the select lines are newly set to SL1 and SL2 as compared to FIG.
Potentials V0, V1 via channel MOSFETs 1-0, 1-1, respectively
And the potentials V5 and VEE are supplied to the select line SL2 via the select N-channel MOSFETs 2-5 and 2-E, respectively. The output transistor is a P-channel MOSF for one scanning output point.
It is composed of a total of two transistors, one ET3 and one N-channel MOSFET4. For this purpose, the shift register 6 is connected to the gate drive circuits of the two output transistors 3 and 4.
EXOR between the selection data DTn as the output of the inverter and the AC signal DF
An EXOR circuit 7 for obtaining a condition is added, and an output signal (selection data) 7a of the EXOR circuit 7 is level-shifted as it is by a level shift circuit 5 to obtain selection data Qn.
The gates of the output transistors 3 and 4 are commonly driven by Qn. The EXOR circuit 7 can be composed of, for example, two inverters 8 and two transmission gates 9 as shown in FIG. In this way, the selection data 7a (accordingly, Qn) corresponding to the selection data DTn in FIG.
In the range of L of DF, it is the same as that of FIG. 6, but in the range of H, the same data Qn of FIG. 6 is inverted. Next, the operation of FIG. 1 will be described with reference to FIG. When the AC conversion signal DF is L, the select transistors 1-1, 2-E are turned ON (1-0, 2-5 are turned OFF) as in FIG. V1 and VEE are supplied. Here, when the selection data DTn is not selected (when it is L), the selection data Qn is L, the output P-channel transistor 3 is ON (the output N-channel transistor 4 is OF
F), and the potential V1 is output as the common drive signal COMn. When the selection data DTn is selected (when it is H, the third
At the time point t1), the selection data Qn becomes H, so that the output transistor 4 turns ON (3 turns OFF), and the potential VEE is output as the common drive signal COMn. Next, when the AC signal DF is H, the select transistors 1-0, 2-5 are turned on (1-1, 2-E are turned off), and the potentials V0, V5 are applied to the select lines SL1, SL2, respectively. Supplied. Here, when the selection data DTn is not selected (when it is L), the selection data Qn is H, and the output transistor 4 is turned ON (3 is
OFF), and the potential V5 is output as the common drive signal COMn. However, when the selection data DTn is selected (when it is H, time t2 in FIG. 3), the selection data Qn becomes L, and the output transistor 3 is turned on. (4 is OFF), and the potential V0 is output as the common drive signal COMn. In this way, the relationship between the AC signal DF and the common drive signal COMn is exactly the same as in FIG. On the other hand, in this case, the driving of the output transistors 3, 4 can be always performed under the condition that the gate-source voltage VGS is large and almost constant, so that these transistors 3, 4 There is no need for a parallel transistor as shown in FIG.

【The invention's effect】

According to the present invention, the semiconductor integrated circuit is provided with a select line to which V0 and V1 as the first plurality of potentials are selected and applied via the select P-channel transistor 1, respectively.
A select line SL to which SL1 and V5 and VEE as second plurality of potentials lower than any one of the first potentials are selected and applied via the select N-channel transistor 2, respectively.
2, an output P-channel transistor 3 as a P-channel MOSFET having a source connected to the select line SL1
And an output N-channel transistor 4 serving as an N-channel MOSFET whose source is connected to the select line SL2, and the drains of the P-channel and N-channel MOSFETs 3, 4 are commonly connected to each other. Drive signal COMn
Output terminals of the P-channel and N-channel MOSFETs 3 and 4 are connected in common to form the two MOSFETs.
The common gate is driven by a circuit to which an EXOR circuit is applied so that one of the gates 3 and 4 is turned on and the other is turned off.
Alternatively, since the second potential is taken out from the output terminal, the drive circuit of the output transistors 3 and 4 has EXO
Although an R circuit 7 is added, the EXOR circuit 7 can be realized by a simple logic as shown in FIG. On the other hand, comparing the areas required for the layout of the high breakdown voltage section (stage after the level shift circuit 5) and the gate drive logic section, the high breakdown voltage section is much larger. EXOR to gate drive logic
Even if the circuit 7 is added, the chip area can be reduced by increasing the number of high breakdown voltage transistors (output transistors 3 and 4) from the conventional four to two according to the present invention. FIG. 4 shows a case where the output transistor is applied to a capacitive load such as a liquid crystal by using the transistors 3 and 4 of the present invention or a conventional P-channel transistor 3 (FIG. 5).
1 is set to L and the gate of the N-channel transistor 4-1 is set to H, thereby turning on the respective gates, and like the P-channel transistor 3-1 in the case where the potential V0 of the select line SL is output as the common drive signal COMn. FIG. 4A shows a case where the gate-source voltage VGS is driven constant (FIG. 4A) and a case where the gate is driven by a variable VGS like the conventional N-channel transistor 4-1 (FIG. 4B). FIG. 7 is a comparison diagram of the operation of FIG. First, the general driving capability (that is, output current) of such a P, N channel transistor can be expressed by a saturation current. Where K: drive capacity coefficient, W: channel length, L: channel width, WT
H: threshold voltage, VGS: gate-source voltage, On the other hand, since the load is a capacity, for example, when charging a capacitor from the lowest voltage to the highest voltage, the operating point of the P-channel transistor 3-1 is VGS = constant and the operating point of the arrow locus of FIG. Move with time, and a constant driving capability is maintained.
The operating point of -1 indicates that as charging progresses, VGS decreases and
Because it moves with time like the arrow trajectory in FIG.
Driving ability decreases. Therefore, the chip area of the two-channel transistors 3-1 and 4-1 is allocated to the single-channel (P-channel) transistor 3 of the present invention, and the chip area of the conventional two-channel transistors 3-2 and 4-2 is similarly calculated. Is applied to the single-channel (N-channel) transistor 4 of the present invention, it is possible to improve the driving capability while maintaining the same chip size as the conventional one.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a main part as one embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of a configuration of an EXOR circuit in FIG. 1, and FIG. FIG. 4 is a comparison diagram of the operation of the output transistor between the present invention and the conventional one, FIG. 5 is a conventional circuit diagram corresponding to FIG. 1, and FIG. FIG. 7 is a diagram showing a truth table of the common drive signal in FIG. 5 corresponding thereto. V0, V1, V5, VEE: LCD driving power supply, 1 (1-0, 1-1): P-channel transistor for selection, 2 (2-5, 2-)
E): N-channel transistor for selection, SL1, SL2: select line, 3: P-channel transistor for output, 4: N-channel transistor for output, COMn: common drive signal, 5: level shift circuit, 6: shift register, 7 : EXOR circuit, 8: Inverter, 9: Transmission gate, DTn,
Qn, 7a: Selection data, DF: Alternating signal.

Claims (1)

(57) [Claims] A first line to which a plurality of first potentials are respectively selected and applied; and a second line to which a plurality of second potentials lower than any of the first potentials are respectively selected and applied. And a P-channel MOSFET source connected to the first line
And an N-channel MOSF having a source connected to the second line.
ET, and the drains of the P-channel and N-channel MOSFETs are connected in common to form an output terminal. Similarly, the gates of the P-channel and N-channel MOSFETs are connected in common, and the two MOSFETs are connected together. A semiconductor integrated device wherein the common gate is driven so that one is turned on and the other is turned off, and the first or second potential is taken out from the output terminal.