JP2746082B2 - A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter having an improved S / N ratio for a minute input signal and improved conversion accuracy.

[0002]

2. Description of the Related Art There are various types of A / D converters for converting an analog signal into a digital signal. FIG. 2 is a diagram showing a basic configuration of a conventional successive approximation A / D converter.
As shown in this figure, in the successive approximation type A / D converter,
An input analog signal, which is a signal to be converted, is sampled in a sample and hold circuit 1, and its instantaneous value is input to a comparator 2. The comparator 2 compares the instantaneous value with a D / A conversion output (analog signal) output from the internal D / A converter 3. Digital values M0, M1, M2, M3 for D / A conversion by the D / A converter 3 (M0 is MS
B and M3 are generated by the successive approximation circuit 4 for LSB.

The successive approximation circuit 4 includes a 4-bit successive approximation register (SAR) and a control circuit. The control circuit outputs 4-bit outputs M0 and M1 of the successive approximation register according to 1/0 of the output of the comparator 2. , M2, M3 are changed as shown in FIG.
That is, at the first comparison time t1, the MSB M0 is set to 1 and a D / A conversion output of a substantially intermediate level is input to the comparator 2. In the example of FIG. 3, since the level of the D / A conversion output at t1 is larger than the analog input sampling value,
The control circuit determines that M0 = 1 is inappropriate. Then, based on the output 0 of the comparator 2 at this time, the control circuit returns M0 to 0 at the next timing t2, and simultaneously sets M1 to 1 to perform the comparison operation again. At this time, since the analog input sampling value is larger, the next timing t3
Then, the comparison operation is performed with M0 = 0, M1 = 1, and M2 = 1. When successive approximation is performed in this manner, a D / A conversion output closest to the analog input sampling value is finally obtained.
This is output as an A / D conversion value. In this example, 4
Since the bit A / D converter is shown, the A / D converter of t4
The converted output is the final output.

[0004]

The limitation of the conversion accuracy and S / N ratio of a normal A / D converter is not limited to the above-described successive approximation type A / D converter. Is determined. For example, if noise is mixed at the timing of comparison in the comparator, the converted output is affected by the noise. Such a problem is more likely to occur in a digital / analog mixed (monolithic) LSI in which an A / D converter is integrated with another digital circuit on the same substrate. The reason is that the noise from the digital system often dominate the noise in the A / D converter system.

An object of the present invention is to provide an A / D converter that solves the above-mentioned problems, improves the S / N ratio, and improves the conversion accuracy for a small signal. Another object of the present invention is to provide an A / D converter provided with a sample-hold type analog amplifier that does not cause a change in DC offset at the time of gain switching.

An A / D converter according to the present invention amplifies an input analog signal to be digital-converted with a gain designated to be greater than 1 when its level is smaller than a predetermined level. A sample-and-hold analog amplifier that outputs the intermediate analog signal as a first comparison signal as a signal, a D / A conversion unit that converts an input digital signal into an analog signal and outputs the analog signal as a second comparison signal, A comparator for receiving a first comparison signal from the sample-and-hold type analog amplifier and a second comparison signal from the D / A conversion unit and comparing the levels of both signals; and a comparison output from the comparator And generates a digital signal based on the D /
A successive approximation circuit that supplies the signal as an input to the A conversion unit and outputs the result as an intermediate digital signal to a subsequent stage, and that the product of the intermediate digital signal output from the successive approximation circuit and the designated gain of the sample-hold type analog amplifier is 1 Digital attenuating means for attenuating with a certain degree of attenuation and outputting as a final digital signal.

The sample-and-hold type analog amplifier includes an operational amplifier having a first input terminal connected to a first reference potential point and outputting the intermediate analog signal from an output terminal, and a second input terminal of the operational amplifier. A first capacitor connected between the input analog signal and an output terminal; a second capacitor for cutting a DC component of the input analog signal; and an input terminal to which the input analog signal is input via the second capacitor at one end. A plurality of first resistors, and one end of each of the plurality of first resistors is connected to the other end of the plurality of first resistors, and the other end is connected to an output terminal of the operational amplifier. A plurality of second resistors for determining a time constant; the plurality of first resistors and the plurality of second resistors;
A plurality of first switches each having one end connected to each connection point of the resistors of the first and second resistors, and a third capacitor connected between the other ends of the plurality of first switches and a second reference potential point. And a connection point between each of the plurality of first resistors and the plurality of second resistors and a second input terminal of the operational amplifier, and performs an exclusive switching operation with the first switch. A plurality of second switches, wherein the plurality of first switches are provided.
And a plurality of second resistors corresponding to each other have different ratios, and the plurality of first switches and the plurality of second switches are selectively switched based on the designated gain. The ratio of the intermediate analog signal to the input analog signal can be changed by arbitrarily connecting the plurality of first resistors and the corresponding plurality of second resistors to an operational amplifier.

[0008]

[0009]

[0010]

If the input analog signal is amplified by the gain A before the A / D conversion by the A / D conversion unit and the A / D conversion output is attenuated by 1 / A, the S / N ratio is maintained without changing the total gain. Can be improved, and the conversion accuracy for small signals can be improved. The gain A is given by the sample-and-hold type analog amplifier, and the attenuation degree 1 /
A is provided by a digital attenuator. The gain A increases as the level of the input analog signal decreases.

In particular, according to the present invention, the analog amplifier is constituted as a sample-and-hold type, and the second and third analog amplifiers are used for DC cutting.
, The amount of DC feedback in the operational amplifier in this amplifier is 100%. Since this feedback ratio is constant even if the ratio of the first and second resistors is set arbitrarily, the gain switching does not become a factor for generating noise.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. An A / D converter unit 10 is a conventional A / D converter having the configuration shown in FIG. 2, for example. In the present invention, an analog comparator 11, an analog amplifier 12, and a digital attenuator 13 are provided in addition to the A / D conversion unit 10.

The analog amplifier 12 amplifies an input analog signal with a gain of 1 or greater than 1, and inputs the amplified signal to the A / D conversion unit 10. The A / D conversion unit 10 converts the intermediate analog signal output from the amplifier 12 into 1 or 1
To an intermediate digital signal with a smaller attenuation. The digital attenuator 13 attenuates the intermediate digital signal output from the A / D conversion unit 10 to obtain a final digital signal. The analog comparator 11 determines to divide the level of the input analog signal into three levels. The relationship between the gain of the analog amplifier 12 and the degree of attenuation of the digital attenuator 13 is always one. The analog comparator 11 sets the gain of the analog amplifier 12 to be greater than 1 when the level of the input analog signal is so small that the influence of noise becomes a problem in A / D conversion in the A / D conversion unit 10 at the subsequent stage. Control to set to a large value.

As an example, the analog comparator 11
When the analog input Vi (amplitude value) as an AC signal is a large value exceeding the high level L2 with reference to the reference value zero (Vi> L2), the comparison output L0 is set to 0, and the analog input Vi is relatively small. When the value falls between the low level L1 and the high level L2, (L1 ≦ Vi ≦ L
2), the comparison output L0 is set to 1; The analog comparator 11 of this example is a kind of window comparator, and when the analog input Vi is smaller than the low level L1 (Vi <
L1) The comparison output L0 becomes 0 as in the case where the analog input Vi exceeds the high level L2.

The output L0 of the analog comparator 11 is used to control the gain of the analog amplifier 12 and the degree of attenuation of the digital attenuator 13. In this example, 2 corresponds to 1/0 of L0.
The switching is performed in stages. That is, when the analog input Vi is larger than the determination level, that is, when L0 = 0, the gain of the analog amplifier 12 is set to 1 and the attenuation of the digital attenuator 13 is also set to 1. In this case, this is equivalent to a state where neither the analog amplifier 12 nor the digital amplifier 13 is added. The reason for this is that when the analog input is large enough,
This is because it is hardly affected by noise.

On the other hand, when the analog input Vi is smaller than the judgment level, that is, when L0 = 1, the gain of the analog amplifier 12 is increased to A (A> 1), and the attenuation of the digital attenuator 13 is increased. Is set to 1 / A. In this case, the total gain, that is, the gain of the entire circuit from the analog signal input terminal to the digital signal output terminal is A × (1/1).
A) = 1, so it is not different from the case of L0 = 0,
Since the intermediate analog signal input to the A / D conversion unit 10 is amplified by A times, the influence of noise caused by a digital system inside the A / D conversion unit 10 is improved. The S / N ratio is also improved as a container body, and the conversion accuracy is improved.

In the above embodiment, the analog comparator 1
The level 1/0 of the output L0 of 1 may be reverse logic. Also,
If the analog comparator 11 determines the level more finely in multiple stages and switches the amplification / attenuation degree exponentially, the gain control of the analog amplifier 12 and the attenuation degree control of the digital attenuator 13 are performed more finely. be able to. Further, a generally known digital attenuator can be used. For example, if it is composed of a shift register and an adder, or if the attenuation is 24 dB,
It can be constituted only by a shift register capable of downshifting bits.

The A / D converter of the present invention amplifies a signal to be converted smaller than noise so as to be much larger than the noise, and amplifies the noise received by the small signal which is a problem in the conventional A / D converter. The effect can be ignored. That is, the amplification of the small signal is improved and the S / N ratio is improved by the amplification. However, since the output digital value becomes larger by the amplification alone, the output digital value is attenuated so as to cancel the amplification gain in the state of the digital value after the A / D conversion to obtain the final output. This attenuation has the effect of simultaneously attenuating noise.

For example, if the noise of the A / D converter system in the digital / analog mixed LSI described above is 75 dB in S / N ratio including the noise from the digital system, S To realize an A / D converter having a / N ratio of 99 dB, the following is performed. For example, an analog input of a minute level or less (for example, -66 dB or less) is connected to the amplifier 1.
Amplify by 24 dB with a gain A of 2. As a result of this amplification,
Since the level of the intermediate analog signal input to the A / D conversion unit 10 changes from −99 dB to −75 dB, the conversion accuracy falls sufficiently within the conversion accuracy of the A / D conversion unit 10. After the A / D conversion, the digital attenuator 13
, So that the level of the digital output returns to -99 dB, which is the same as the analog input.

Switching of the degree of attenuation in the digital attenuator 13 can be performed by bit shifting as described above. On the other hand, the gain switching in the analog amplifier 12 is performed by the following circuit configuration. For example, the analog amplifier 12 shown in FIG. 4 uses an operational amplifier A1 for amplifying an analog input Vi, and its feedback resistors R11, R12, R1.
By switching the combination of 3 with the switch S0,
In this type, the gain for the analog input Vi is switched in two stages.

In the analog amplifier 12 of this type, when the DC offset voltage generated by the operational amplifier A1 or the like is not 0, as shown in FIG. 5, since the DC offset amount also changes with the gain switching, this becomes a noise. You need to be careful. FIG. 7 shows a circuit example of the sample-and-hold type analog amplifier 12 in which such a DC offset does not matter. The analog signal Vi is introduced into the amplifier 12 through a low-pass filter (LPF) 14, but the basic arrangement is the same as that of FIG.

Before describing the circuit of FIG. 7, the basic configuration and operation of the sample and hold circuit will be described with reference to the circuit of FIG. 6. Resistors R1 and R2 are connected between the input terminal IN and the output terminal OUT. Are connected in series, and two switches S1 and S2 which operate exclusively are connected to the connection point N1.
Is connected. Turn on switch S2 (switch S1
Is turned off), the sampling capacitor C1 is charged with the time constant C1 · R2. At this time, the operational amplifier A1
The whole circuit including the above functions as an inverting amplifier circuit having a gain of -R2 / R1. Next, switch S1 is turned on (switch S2
Is turned off), the point N1 is grounded, and the output is held by the electric charge stored in the capacitor C1. By repeating this operation, a sample and hold operation corresponding to the input change is performed.

The sample-hold type analog amplifier 12 shown in FIG. 7 adds series resistors R3 and R4 in parallel with the series resistors R1 and R2 shown in FIG. 6 so that two kinds of gains can be selected. Exclusive operation 2 at connection point N2
One ends of two switches S3 and S4 are connected. The other end of the switch S3 is connected to the ground via a DC cut capacitor C3 together with the switch S1, and the other end of the switch S4 is connected to the sampling capacitor C1 together with the switch S2.
Connected to. The capacitor C2 in the input stage is for DC cut. With respect to the input terminal of the operational amplifier A1, the center value of the power supply voltage is basically input to the non-inverting input (+ input) terminal, but the center potential extracted from the center tap of the D / A converter 3 is used. Is preferably applied as the reference voltage Vref.

In the above configuration, R2 = R4 is set in order to make the two types of sampling time constants the same. R
If R1 = R and R3 = R / 4 when 2 = R4 = R, the gain A can be determined by selecting switches S3 and S4.
1 and A = 4 can be switched. That is, when the switches S1 and S2 are alternately turned on and off while the switch S3 is on and the switch S4 is off, the gain A becomes A =
R2 / R1 = R / R = 1. On the other hand, when the switches S3 and S4 are alternately turned on and off while the switch S1 is on and the switch S2 is off, the gain A becomes A = R
4 / R3 = R / (R / 4) = 4.

The amount of DC feedback from the output terminal of the operational amplifier A1 to the inverted input (-input) terminal is 100% because the DC cut capacitors C2 and C3 are used.
Since this feedback ratio is constant even if the ratio of the resistors R1 to R4 is arbitrarily set, there is no change in the DC offset accompanying the gain switching, and therefore, the gain switching does not become a noise generation factor. The configuration shown in FIG. 7 uses two sets of basic units corresponding to the switches S1 and S2 and the resistors R1 and R2, and
In this example, the gain is switched in stages. However, if three or more sets of the basic units are provided, the analog gain can be switched in more stages.

[0026]

As described above, according to the present invention, A /
Prior to the A / D conversion by the D conversion unit, the input analog signal is amplified by the gain A, and the A / D conversion output is attenuated by 1 / A, so that the S / N ratio is improved and the conversion accuracy for minute signals is improved. Can be provided. Further, when the analog amplifier is configured as a sample-and-hold type, there is no change in the DC offset due to the gain switching, and therefore, when the A / D converter of the present invention is realized, noise that lowers the A / D conversion accuracy is internally generated. Does not occur.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing a basic configuration of a conventional successive approximation A / D converter.

FIG. 3 is an operation explanatory diagram of a successive approximation A / D converter.

FIG. 4 is a circuit diagram showing a first specific example of the analog amplifier.

FIG. 5 is a switching characteristic diagram of the analog amplifier of FIG. 4;

FIG. 6 is a basic configuration diagram of a sample and hold circuit.

FIG. 7 is a circuit diagram showing a second specific example of the analog amplifier.

[Explanation of symbols]

10 ... A / D conversion unit, 11 ... Analog comparator,
12: Analog amplifier, 13: Digital attenuator, A1 ...
Operational amplifier, C1 ... Sampling capacitor, R1-R
4: gain setting resistors, S1 to S4: sampling switches.

Claims (1)

(57) [Claims] 1. An input analog signal to be digitally converted is amplified by a gain designated to be larger than 1 when the level thereof is smaller than a predetermined level to be an intermediate analog signal. A sample-and-hold type analog amplifier that outputs as a comparison signal, and a second digital signal that converts an input digital signal into an analog signal.
And a D / A conversion unit for outputting as a comparison signal, a first comparison signal from the sample-and-hold type analog amplifier, and a second comparison signal from the D / A conversion unit. A comparator for comparison, a digital signal is generated based on a comparison output from the comparator, the digital signal is supplied as an input to the D / A conversion unit, and a successive approximation circuit is output to a subsequent stage as an intermediate digital signal Digital attenuating means for attenuating the intermediate digital signal output from the successive approximation circuit with an attenuation degree such that the product of the specified gain of the sample-and-hold type analog amplifier becomes 1 and outputting the result as a final digital signal; A sample-and-hold type analog amplifier has a first input terminal connected to a first reference potential point, and an output terminal connected to the intermediate analog terminal. An operational amplifier for outputting the items, a first capacitor connected between the second input terminal and the output terminal of the operational amplifier, the second for cutting the DC component of the input analog signal
A plurality of first resistors to which the input analog signal is input via the second capacitor at one end, and one ends respectively connected to the other ends of the plurality of first resistors,
The other end is connected to an output terminal of the operational amplifier, a plurality of second resistors each of which determines a sample-and-hold time constant together with the first capacitor, the plurality of first resistors, and a plurality of second resistors. A plurality of first switches each having one end connected to each connection point of the plurality of first switches; a third capacitor connected between the other ends of the plurality of first switches and a second reference potential point; A plurality of switches connected between respective connection points of the plurality of first resistors and the plurality of second resistors and a second input terminal of the operational amplifier, and performing a switching operation exclusively with the first switch. A second switch, wherein ratios of the plurality of first resistors and the corresponding plurality of second resistors are respectively different, and the plurality of first switches and the plurality of second switches are designated. Each selectively based on the gain By performing the switching operation, the plurality of first resistors and the corresponding second
An A / D converter characterized in that the ratio of the intermediate analog signal to the input analog signal can be changed by arbitrarily connecting the resistor of (1) to the operational amplifier.