JP2743772B2 - Phase correction device and recording medium - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and a recording medium for correcting a phase of a pulse signal, and more particularly, to a method for correcting a recording pulse width when recording and reproducing data on an optical disk or the like in which intersymbol interference occurs. And a recording medium.

[0002]

2. Description of the Related Art As a conventional technique for correcting a pulse width when information is recorded on a recording medium by a light beam, there is an optical recording apparatus disclosed in Japanese Patent Publication No. 61-31507. This prior art focuses on the fact that the start and end of a light beam spot at the time of recording on a recording medium become semicircular, and data of a required length cannot be obtained during reproduction. (Or phase) to correct the reproduction data.

According to this conventional technique, the amount of correction of the pulse width is constant regardless of the arrangement of data, thereby eliminating the extension of the light beam spot. That is, according to this conventional technique, the correction is performed for the elongation of the spot caused by the thickness (spread) of the light beam spot.

[0004]

On the other hand, in a digital recording / reproducing system such as an optical disc, if the recording wavelength is shortened and used near or above the upper limit of the frequency band of the recording / reproducing system, adjacent data is read. A so-called intersymbol interference occurs in the reproduced waveform of each data at that time. The influence on adjacent data due to such intersymbol interference varies depending on the length of adjacent data.
It has the following properties.

In FIG. 1, the length of data to be recorded is used as a parameter, the horizontal axis represents the length of adjacent data, and the vertical axis represents the difference between the recorded data length and the adjacent data length. For example,
It is assumed that the recording data length is 3T for a predetermined unit T.
In this case, the difference between the recording data length and the adjacent data length is as shown in a graph GA. If there is no intersymbol interference, the difference between the recording data length and the adjacent data length is 0, -1T, -2T,-
3T,... Changes in proportion to the adjacent data length, but becomes as shown in a graph GA due to intersymbol interference. Similarly, when the recording data length is 4T, if there is no intersymbol interference, the difference between the recording data length and the adjacent data length is 1T, 0,
−1T, −2T, −3T,..., But the graph becomes GB due to intersymbol interference.

FIG. 6 illustrates a change in data length due to intersymbol interference. In the figure, (A) is a channel clock CK of a signal, and its cycle is T. Fig. (B)
Represents data WD to be recorded, and FIG. 4C shows a recording pit pattern WP corresponding thereto. However, the pit pattern is rectangular for ease of explanation. The reproduced waveform RW of such a pit string is as shown in FIG. 3D, and the reproduced data RD obtained based on the predetermined threshold level SL is as shown in FIG.
As is clear from the comparison between the reproduced data of (E) and the recorded data of (B), the data length of the reproduced data is affected by the intersymbol interference, and the original data length of FIG. Δt _n (n = 1, 2, 3,...) With respect to the recording data length
Has an error of

When such intersymbol interference occurs, an accurate data length is not reproduced, and as a result, a jitter margin with respect to disturbance of a medium driving device is reduced. Conversely, if the recording wavelength is lengthened so that intersymbol interference does not occur, that is, if the recording frequency is lowered, it is naturally difficult to increase the recording density. Further, the change in the data length due to the intersymbol interference is not a fixed amount but changes according to the preceding and following data lengths. For this reason, the technique of giving a fixed amount of correction as in the prior art disclosed in the above-mentioned publication cannot eliminate the influence of such intersymbol interference.

The present invention focuses on these points.
The data length of the data to be recorded, the data before and after the data, the data sequence, etc., as well as the amount of phase correction of the data adaptively variable, to obtain data of the correct length during playback even if there is intersymbol interference. It is therefore an object of the present invention to provide a phase correction apparatus and a recording medium which can improve the jitter margin.

[0009]

In order to achieve the above object, the present invention provides a phase correction apparatus for correcting the phase of pulse data that causes intersymbol interference when data is reproduced from a recording medium. Data alignment determining means for determining the alignment of data, and phase correction means for performing adaptive phase correction for each pulse of the pulse data in consideration of the degree of intersymbol interference occurring in the case of the data alignment determined thereby. It is characterized by having. Another invention is characterized in that a recording process on a recording medium is performed based on the pulse data phase-corrected by the phase correction device.

[0010]

According to the present invention, phase correction taking into account the pulse data and the degree of intersymbol interference is performed adaptively for each pulse. Then, recording processing such as formation of a pit row on a recording medium is performed based on the pulse data after the phase correction. When this recording medium is reproduced, good pulse data can be obtained even if intersymbol interference occurs.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a phase correction apparatus and a recording medium according to the present invention. FIG. 1A shows the configuration of the present embodiment.
And a phase correction circuit 30. The data arrangement determination circuit 20 is for determining the arrangement of the input data, and the phase correction circuit 30 is for performing the phase correction of the input data with a correction amount corresponding to the determination output of the data arrangement determination circuit 20. belongs to.

Next, the basic operation of this embodiment will be described with reference to FIG. Note that, similarly to the conventional example, the channel clock is CK and the original recording data is W.
D, WH for correction data, WP for recording pattern, RW for reproduction waveform, and RD for reproduction data. The channel clock CK in FIG. 6A is the same as that in FIG. The original recording data WD in FIG. 6B is indicated by a dotted line in FIG. In this embodiment, the rising and falling phases of the original print data WD are corrected by advancing or delaying as indicated by the solid line WH.

The correction amount in this case is determined in accordance with the result of the determination by the data arrangement determining circuit 20, that is, the data as well as the data. For example, the rising edge E1 in FIG.
The correction amount Δτ ₄ of WD1 and W
It is determined by the data length of D2. The correction amount Δτ ₅ of the falling edge E2 is represented by W
It is determined by the data length of D2 and WD3. This is because the degree of intersymbol interference changes correspondingly to data as shown in FIGS. 5 and 6 (E). Such phase correction is performed on the recording data WD (dotted line in FIG. 2B) by the phase correction circuit 30, and the correction data W
H (the solid line in FIG. 3B) is obtained.

The recording pit pattern WP corresponding to the correction data WH is as shown in FIG. 3C, and the reproduced waveform RW of such a pit row is as shown in FIG.
Then, the reproduced data RD obtained based on the predetermined threshold level SL is as shown in FIG. As is clear from the comparison between the reproduced data of (E) and the recorded data of (B), the data length of the reproduced data is affected by the intersymbol interference, and Δτ _n ( n = 1, 2, 3,...). As a result, the reproduction data RD matches the original recording data WD of FIG. 6B, as shown in FIG.

That is, in the present embodiment, the phase correction is performed so that the reproduced data having the intersymbol interference has the original data length, and the phase correction amount Δτ _n is ΔΔn in FIG.
t _n is set to 0. In other words, the pulse width correction is performed on the premise that intersymbol interference occurs, whereby the reproduction data RD matches the original recording data WD well.

Next, this embodiment will be described in more detail. In FIG. 1A, original recording data WD to be recorded on an optical disc (not shown) is input to an S / P (serial / parallel) converter 22 of a data alignment determination circuit 20 together with a channel clock CK. . This S
The parallel data output side of the / P converter 22 is connected to a ROM 24
The data read side of the ROM 24 is connected to a latch circuit 26 including D-flip-flops. The address A7 of the ROM 24 is connected to the latch timing clock terminal TC of the latch circuit 26.

The output side of the latch circuit 26 is connected to the phase correction circuit 30. As shown in FIG. 1B, for example, the phase correction circuit 30 opens and closes the delay line 32 including a number of serially connected delay circuits DL and a switch circuit S for extracting the outputs of the delay circuits DL, and the switch circuit S. And a decoder 34 for controlling according to the input. The output side of the latch circuit 26 is connected to the input side of the decoder 34,
Is connected to the input side of the delay line 32. The output side of the switch circuit S of the delay line 32 is connected in common, and this is the corrected data output side.

Of the above components, the S / P converter 22 includes:
This is for converting serial input data into parallel data in order to determine the arrangement of input recording data.
ROM24 is parallel data has become an address A0-A13, the correction data corresponding to the .DELTA..tau _n each address is stored previously obtained. Latch circuit 26
Is a circuit for latching the correction data read from the ROM 24. The phase correction circuit 30 has a function of performing phase correction by decoding the correction data latched by the latch circuit 26 and outputting data of a delay amount corresponding thereto.

Next, the operation of the phase correction apparatus according to the embodiment configured as described above will be described with reference to a time chart of FIG. The channel clock CK in FIG. 7A is as described above. The serial recording data WD input based on this clock is converted into parallel data by the S / P converter 22. That is,
Serial data is S / P for each channel clock CK.
The signals are sequentially output from the terminals of the converter 22 and supplied to the address terminals A0 to A013 of the ROM 24, respectively.

For example, pulse data d6 having a data length of 5T
Pay attention to. Referring to the hatched portion at time ta in FIG.
The first bit is address A1 (FIG. 10 (C)), the second bit is address A2 (FIG. 10 (D)), the next third bit is address A3 (FIG. 10 (E)), and the next bit is The fourth bit is supplied to the ROM 24 as an address A4 ((F) in the figure), and the last fifth bit is supplied as an address A5 ((G) in the figure). The same applies to other addresses.

As a result of the S / P conversion, the ROM 24
The parallel data as shown in FIGS. 8B to 8O are input to the addresses A0 to A13. Here, focusing on the pulse data d6, the pulse width of the pulse data d6 may be 5T by referring to the fact that the falling address is A1 and the rising address is A5. I understand. By utilizing such a relationship, the arrangement relationship of the data length of the input data, that is, the data arrangement can be determined from the relationship between the rising and falling edges of the addresses A0 to A13.

In the present embodiment, A7 to A13 are used for judging the preceding data of each edge with the addresses A6 and A7 as boundaries, and A0 to A13 are used.
.About.A6 are used for determination of post-data. Then, based on the data at the address A7, the data arrangement is determined by the rise and fall of the data. In particular,
Data latch in the latch circuit 26 is performed. Then, based on the latched correction data, the phase correction is performed on the recording data WD at the address A8.

For example, attention is paid to the rising edge Eg of the pulse at the address A7 shown in FIG. Looking at the addresses A7 to A13 at the time of the edge Eg, the logical values of the addresses A7 to A9 are "0", and the logical values are inverted to "1" at the address A10. Therefore, it is determined that the length of the data d3 before the rising edge Eg is 3T. Similarly, address A at the time of edge Eg
Looking at 0 to A6, the logical values of the addresses A1 to A6 are “1”, and the logical values are inverted to “0” at the address A0.
Therefore, it is determined that the length of the data d4 after the rising edge Eg is 6T. The addresses A11 to A13 may be "0" or "1".

Next, the logical values of the addresses A0 to A13 of the ROM 24 at the time of the rising edge Eg are set to 16
In hexadecimal notation, as shown in Table 1, addresses A11 to A13
There are eight ways depending on the value of the logical value of. In the addresses of the ROM 24 shown in Table 1, correction data indicating the amount of phase correction in the case of data arrangement of [ 3T- 6T] (for example, land is indicated with an underline and pit is indicated without) is stored. I have.

[0025]

[Table 1]

FIG. 3 (P) shows the address A of the ROM 22.
The changes from 0 to A13 are shown in hexadecimal notation. Edge E
At the timing of g, the addresses A11 to A13 are shown in FIG.
Since the logical value is “1” as shown in FIGS.
Hexadecimal display address is "3C7E" as shown on the right end
(See FIG. 3 (P)). The 8-bit correction data stored at this address is supplied from the output terminals q0 to q7 of the ROM 24 to the input terminals D0 to D7 of the latch circuit 26.
Will be output to

On the other hand, the latch circuit 26 has an address A7
Is input to the timing clock terminal TC, the input data is latched at the timing of the edge Eg, and output from the output terminals Q0 to Q7 to the phase correction circuit 30 (see FIG. 9 (Q)). ROM2 as above
The latch operation of the correction data 4 is performed at each edge of the data at the address A7 (see arrows (P) and (Q) in the same figure). At time t1, the logical values of the addresses A0 to A13 in the ROM 24 are "11111110000111", which when expressed in hexadecimal is "387F". Therefore, the correction data at this address, that is, the data sequence d1.
The correction data corresponding to d2 is latched by the latch circuit 26.

At time t2, the addresses A0 to
The logical value of A13 is "11110001111111", which is "3F81" in hexadecimal notation. Therefore, the correction data at this address, that is, the correction data corresponding to the data sequence d2 · d3 is latched by the latch circuit 26. Time t3 is as described above.

At time t4, addresses A0 to
The logical value of A13 is "11100001111110", which when expressed in hexadecimal is "1F87". Therefore, the correction data at this address, that is, the correction data corresponding to the data sequence d4.d5 is latched by the latch circuit 26. At time t5, the addresses A0 to
The logical value of A13 is “00111110000111”, which when expressed in hexadecimal is “387C”. Correction data of this address, that is, data arrangement d5.d6
Is corrected by the latch circuit 26. Hereinafter, the same applies.

Next, pulse data at the address A8 of the ROM 24 is input to the delay line 32 of the phase correction circuit 30. FIG. 3 (R) shows the ROM 2 of FIG. 3 (J).
The pulse data of address A8 of No. 4 is shown as it is, and is the original recording data WD. This data is successively delayed by a predetermined amount by the delay circuit DL of the delay line 32. On the other hand, the latched correction data shown in FIG. 2 (Q) is supplied to the decoder 34 and decoded, and the corresponding switch circuit S is turned on, and the delay circuit DL
Is output as correction data.

For example, the rising phase of the data d2 in FIG. 9 (R) is delayed by 1.2T as shown in FIG. 9 (S) based on the correction data corresponding to the data arrangement d1 and d2. . Similarly, the falling phase of the data d2 is delayed by 0T based on the correction data corresponding to the data sequence d2 · d3. The rising phase of the data d4 is delayed by 1.4T based on the correction data corresponding to the data sequence d3 · d4. The falling phase of the data d4 is delayed by 0.6T based on the correction data corresponding to the data sequence d4 · d5. Less than,
The same is true.

Since the phase of the correction data shown in FIG. 3S which has been phase-corrected as described above is entirely delayed, this is shown corresponding to the original recording data of FIG. Then, as shown in FIG. FIG. 4 (A) is FIG. 3 (R)
4B is the original recording data WD, and FIG.
This is the correction data WH of (S). As shown in FIG.
FIG. 2B also shows (B). For example, the rising phase of the correction data H1 is 0.4 T behind the recording data, and the falling phase is 0.8 T
T is ahead. The rising phase of the correction data H2 is delayed by 0.6T with respect to the recording data, and the falling phase is advanced by 0.2T.

As described above, according to this embodiment, the data arrangement in the original recording data is determined, and the phase correction is adaptively performed in accordance with the result of the determination to obtain correction data.
Then, a pit pattern is formed on the optical disk based on the correction data. For this reason, even if intersymbol interference occurs in the reproduced data, the original recorded data can be reproduced favorably, the jitter margin can be improved, and the limit to disturbance can be increased. In addition, short-wavelength recording exceeding the upper limit of the frequency band of the data recording / reproducing system can be performed, and the recording density can be improved.

<Other Embodiments> The present invention is not limited to the above-described embodiments, but includes, for example, the following. (1) As a method of phase correction, as shown in FIGS. 3 (R) and 3 (S), the maximum advance when the phase is to be advanced most is set to the delay amount “0”, and the delay amount of each edge is There is a method of delaying the entire phase by adding the maximum phase lead amount. In this example, the data of FIG.
When the phase separation is advanced, the phase relationship shown in FIGS. 4A and 4B is obtained. However, the phase may be advanced or delayed so as to obtain the phase-related correction data as shown in FIG.

(2) In the above-described embodiment, since the ROM 24 used is 128 kbits (16 kbits × 8), the data length can be measured only up to 7T, and all data lengths longer than 7T can be measured. Is considered. When it is desired to measure a data length of 7T or more, a ROM 24 having a larger capacity may be used. (3) In the present embodiment, the phase correction amount is determined by measuring only the data length immediately before and after each edge for each edge. However, if the intersymbol interference is affected not only by the data immediately before and immediately after but also by data that is further away, the phase correction amount may be determined based on the data sequence before and after each edge. The determination of this data string can be easily made by increasing the number of addresses in the ROM 24.

(4) In the present embodiment, the correction for the intersymbol interference is performed, but the correction of the conventional example may be performed simultaneously. In this case, the correction amount for the data length change due to the spread of the light beam spot may be added to the correction amount for the intersymbol interference. (5) The device configuration is not limited to the above-described embodiment, and various design changes can be made so as to achieve the same operation. Further, if intersymbol interference occurs, the present invention can be applied not only to an optical recording medium but also to a magnetic recording medium.
Generally, in magnetic recording / reproduction, a reproduction signal has a differential waveform. At this time, if there is intersymbol interference, the peak of the differential waveform moves. Even in such a case, by applying the present invention, it is possible to remove an adverse effect due to intersymbol interference.

[0037]

As described above, according to the phase correcting apparatus of the present invention, the following effects can be obtained. (1) Since adaptive phase correction based on data is performed, good data can be obtained during reproduction even if there is intersymbol interference, and a jitter margin can be improved. (2) Short-wavelength recording exceeding the upper limit of the frequency band of the recording / reproducing system becomes possible, and the recording density can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a phase correction device according to the present invention.

FIG. 2 is a time chart showing the overall operation of the embodiment.

FIG. 3 is a time chart showing a detailed operation of the embodiment.

FIG. 4 is a time chart showing a relationship between recording data and correction data in the embodiment.

FIG. 5 is a graph showing a change in data length due to intersymbol interference.

FIG. 6 is a time chart showing the influence of intersymbol interference on reproduced data according to the conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Phase correction apparatus, 20 ... Data arrangement | sequence determination circuit (data arrangement | sequence determination means), 22 ... S / P converter, 24 ... RO
M, 26: latch circuit, 30: phase correction circuit (phase correction means), 32: delay line, 34: decoder, CK
... channel clock, D ... delay circuit, d1 to d6 ... data, Eg ... edge, S ... switching circuit, SL ... threshold level, WD ... original recording data, WH ... correction data, Delta] t _n ... errors due to intersymbol interference, Δτ _n … the amount of phase correction.

Claims (2)

(57) [Claims] 1. A phase correction device for correcting the phase of pulse data in which intersymbol interference occurs when data is reproduced from a recording medium, comprising: a data arrangement judging means for judging the arrangement of the pulse data; A phase correction unit that performs adaptive phase correction in consideration of the degree of intersymbol interference that occurs in the case of the data arrangement performed for each pulse of the pulse data. 2. A recording medium obtained by performing a recording process based on pulse data phase-corrected by the phase correction device according to claim 1.