JP2734871B2 - Digital video signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal processing circuit suitable for use in a camera-integrated digital VTR or the like for performing band compression processing of an image signal, and more particularly to a circuit for changing the aspect ratio of a video screen. .

[0002]

2. Description of the Related Art In the current television signal system, the aspect ratio or aspect ratio of a television screen is 3: 4. Television cameras or video cameras,
Alternatively, in an imaging apparatus such as a camera unit of a camera-integrated video tape recorder, it is assumed that an imaged screen is displayed on a television screen having such an aspect ratio. For this reason, the aspect ratio of the imaging device of the imaging device is also 3: 4. On the other hand, in general, in a movie for a theater, the aspect ratio of the screen is different from the aspect ratio of the television, and the screen is a horizontally long screen as is well known. For this reason, when broadcasting a movie on a television, the landscape screen of the movie is broadcast with the upper and lower portions of the television screen blanked (black screen) in the vertical direction. May be.

In recent years, monitor screens such as televisions and video projectors have a large screen size. CRT televisions have a screen size of 30 inches, and projectors have a screen size of 100 inches or more. . When viewing on such a large screen monitor, the current aspect ratio is 3:
For example, a horizontally long screen having an aspect ratio of 9:16 is easier to see than 4. In addition, when watching a movie on a television, it is better to blank the upper and lower portions of the screen to make the atmosphere more like a movie.

On the other hand, digital VTRs are currently being put into practical use, and there are D1 system for recording and reproducing component signals and D2 system for recording and reproducing composite signals as international standards. However, the D1 and D2 methods use a large amount of tape, and the digital V
Considering TR, it is necessary to reduce the amount of tape used.
For that purpose, image compression is indispensable.

As one example of the image compression processing, there is an image compression apparatus as shown in FIG. This device is JPEG, an organization that promotes international standardization of color still image coding.
Device proposed by (Joint Photographic Expert Group) (The Journal of the Institute of Television Engineers of Japan, P 158 Vol144 No2 1990)
See).

Hereinafter, this apparatus will be described. First, 1
A DCT (Discrete Consine Transform) block obtained by extracting eight vertical and eight digital pixel data from the screen is supplied to a DCT (8 × 8 DCT) 1 where a two-dimensional DCT is performed. An 8 × 8 transform coefficient is supplied to the linear quantizer 2.

The multiplier 4 multiplies the reference quantization matrix supplied from the quantization matrix generator 3 (quantization matrix) by the scaling factor S, and performs linear quantization using the quantization matrix obtained. Are supplied to the one-dimensional predictor 5 and the zigzag scanner 7, respectively.

[0008] The one-dimensional predictor 5 compresses the information amount of the continuous DC conversion coefficient 2a and converts the information amount into a first Huffman encoder 6a.
To supply. The first Huffman encoder 6 is a kind of entropy code because the Huffman code that allocates a smaller number of bits in descending order of the event occurrence rate is formed based on the event occurrence probability. Also, the occurrence probability of an event may use the result measured in advance, and need not be obtained at the time of encoding.

On the other hand, the zigzag scanner 7 scans the AC conversion coefficient 2b from the low-frequency component to the high-frequency component as shown in FIG. 8, and the second Huffman encoder 8 outputs the value "0". Similarly, a Huffman code is generated for the run length of the transform coefficient of "1" and the value of the transform coefficient other than "0", and supplied to the other input of the multiplexer 9. And the multiplexer 9
Outputs a multiplexed output signal 9a obtained by multiplexing the respective inputs to a transmission line (not shown).

Since the above-mentioned conventional technique uses the Huffman code, the information amount of the multiplexed output signal 9a fluctuates with respect to a fixed input information amount. For this reason, using the scaling factor S, for example, the information amount of the multiplexed output signal 9a per field is controlled to be kept constant.

[0011]

By the way, the cinema mode function may be adopted in a camera-integrated digital VTR or the like having the above-mentioned compression processing device. In this case, the cinema mode processing is performed. A desired function can be obtained by providing the circuit on either side of the compression processing device.

However, in the above-described compression processing apparatus, a processing error called mosquito noise occurs at a large edge portion of an image or a portion having many high-frequency components. The appearance of mosquito noise generated at the boundary between the upper and lower blanks for the cinema mode differs depending on the position of the mosquito noise. Therefore, the present invention has been made in view of such a point, and when the cinema mode function is adopted, the mosquito key
It is intended to reduce noise.

[0013]

The present invention aims to achieve the above object by the following means. That is, in a digital video signal processing circuit for performing a predetermined band compression process on a digital video signal displayed as an image with a predetermined size by a band compression processing circuit employing block coding, Mask processing means for masking a part of the digital video signal to be displayed as an image, and setting a vertical masking process in the mask processing means so that a masking boundary coincides with a boundary between blocks. Characteristic digital video signal processing circuit.

[0014]

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram of a camera-integrated digital VTR (hereinafter simply referred to as a camera device) employing a video processing circuit according to an embodiment of the present invention.

In FIG. 1, reference numeral 20 denotes a camera unit including a lens, an image sensor, etc., 21 a camera signal processing circuit, 22 a mask processing circuit, 23 a band compression processing circuit, and 24 a recording process circuit. For example, the incoming optical image information is converted into an electric signal by the camera unit 21, an analog signal is converted into a digital signal in the next camera signal processing circuit 21, and the luminance signal is subjected to processing such as gamma correction and white clipping. Is performed on the color signals, and processing such as gamma correction is performed on the color signals. Thereafter, both signals are supplied to the mask processing circuit 22 in the next stage.

In this case, normally, the mask processing circuit 22 outputs a video signal such that the display screen has an aspect ratio of 3: 4 as shown in FIG. 2A, for example. When the mode is switched to the cinema mode as desired, signal processing is performed so that the display screen has an aspect ratio of approximately 9:16 as shown in FIG. The mask processing circuit 22 will be described later in more detail.

The band compression processing circuit 23 at the next stage employs a band compression processing device having the same configuration as that described in the above-described conventional example, and performs the same compression processing as described above. And
The band-compressed signal is supplied to a recording process circuit 24, where it undergoes the same signal processing as performed in a general VTR, and is recorded on a tape by a head (not shown).

As described above, the camera device of the present embodiment is
The above-mentioned object is achieved by providing the mask processing circuit 22 in a stage preceding the band compression processing circuit 23. This will be described in further detail together with other features. FIG. 3 is an example of a detailed block diagram of the mask processing circuit 22. In the figure, reference numeral 30 denotes an input terminal to which a cinema mode signal is supplied. This input terminal is connected to a switch 31 and an inverter 32. The switch 31 is connected to a reset terminal R of the counter 33, and the counter 33 is connected to an upper mask position determining circuit 34 for determining an upper mask position and a lower mask position determining circuit 35 for determining a lower mask position. ing. The output sides of these circuits 34 and 35 are connected to a set terminal S and a reset terminal R of an RS-FF (RS flip-flop) 36, and the output terminal Q is connected to one end of an OR 37. The other end is connected to the output side of the inverter 32.

The output side of the OR circuit 37 is connected to a switch 3
The input side of the switch 38 is connected to an input terminal 39 for supplying a video signal (V) from the camera signal circuit 21. An input terminal 40 supplies a horizontal synchronizing signal (HD) from the camera signal processing circuit 21 to the clock terminal C of the counter 33. Further, reference numeral 41 denotes a switch 31 for transmitting a vertical synchronizing signal (VD).
And an input terminal for supplying the same to the above.

Next, the operation based on these configurations will be described. First, the case of the normal mode in which the aspect ratio at the time of screen display is 3: 4 will be described. In this case, the cinema mode signal S does not come in from the input terminal 30, and the switch 3
1 is switched to the L side (earth side), and the counter 33 is not operated. A high-level signal is supplied to one end of the OR circuit 37 via the inverter 32, and a high-level signal is output from the OR circuit 37 to switch the switch 38 to the H terminal side.

Therefore, for example, when a video signal having a normal blanking period as shown in FIG. 4A is input from the input terminal 39, this signal is output as it is via the switch 38. The image is output from the terminal 42 to the band compression processing circuit 23, and finally an image having m scanning lines and an aspect ratio of 3: 4 as shown in FIG. 2A is displayed.

Next, the case where the cinema mode is selected will be described. In this case, a high-level cinema mode signal S is input from the input terminal 30, and the switch 31 is switched to the H terminal side, and is inverted by the inverter 32 to be connected to one end of the OR circuit 37. The signal of is supplied.
At this point, the other end of the OR circuit 37 has R
A low level signal is input to the S-FF 36,
A low level signal is output from the OR circuit 37, and the switch 38 is switched to the L terminal side. Then, a black level signal is applied to the L terminal, and a black level signal (masking signal) is output from the output terminal 42 from this point.

On the other hand, from the input terminal 41, for example, FIG.
A vertical synchronizing signal as shown in (B) is supplied, and the counter 33 is reset at the fall. Then, the counting of the horizontal synchronizing signal HD coming from the input terminal 40 as shown in FIG. 4C is started, and the counted number is sent to the next upper mask position judging circuit 34 and lower mask position judging circuit 35, respectively. Supplied.

The upper mask position judging circuit 34 judges a horizontal line to be an upper mask position, and outputs an RS signal only when judging the count number of this line.
-Supply to set terminal S of FF36. This allows RS
A high-level signal is output from the FF 36 to the OR circuit 37, and a signal changed from low level to high level is output from the OR circuit 37, and the switch 38 is switched to the H terminal side. The video signal coming from the terminal 39 is output.

Further, when the count number of the counter 33 advances and the lower mask position determining circuit 35 determines the horizontal line to be the lower mask position, an output signal is supplied to the reset terminal R of the RS-FF 36. From this point, a low-level signal is output from the SR-FF 36, and a low-level signal is output again from the OR circuit 37.
The switch 38 is switched to the L terminal side to output a black level signal, and the lower side mask processing is performed.

Therefore, when the cinema mode is selected, an image as shown in FIG. 2B appears on the screen. In this case, the upper and lower portions of the screen are masked by the black signal, and the image (the approximate image portion is 3 / 4m) so that the aspect ratio is approximately 9:16.
Horizontal scanning line) appears. Note that this mask processing may be set to a gray level without being a separate black signal.

As described above, in this embodiment, since the mask processing is performed before the band compression processing, the processing is equivalent to processing an image having an increased number of flat portions (mask portions).
Since this flat portion includes only the DC component, the number of codes at the time of band compression processing can be reduced. In the band compression processing, since one screen is controlled at a constant rate, the amount of codes allocated to the remaining image display parts (display parts excluding the mask part) relatively increases, and as a result, the image display part compression processing is performed. Error
(Mosquito noise) is reduced, and the image quality can be improved.

In other words, the compression ratio of the image display portion is apparently the same as that of the compression ratio, and has a characteristic that cannot be obtained by the conventional analog processing. ing. Further, it is not necessary to provide a special circuit in order to achieve this effect, it is only necessary to change the circuit installation location, and it is possible to reduce the circuit size and cost.

In addition, a characteristic processing method is performed in the mask processing circuit 22 of the camera apparatus. That is, the method is characterized in selecting the number of scanning lines at the start of the mask and the number of scanning lines at the end of the mask.

Hereinafter, this will be described in detail. The compression processing circuit 23 of this apparatus performs the JPEG compression processing as described above. For example, in a component system having 525 scanning lines as shown in FIG. Are 480 × 720 pixels vertically and horizontally. This value is adopted in general digital video systems other than the D1 system.

Here, assuming that mask processing is performed so that the aspect ratio is exactly 9:16 as shown in FIG. 5B, the number of image display units is 3/4 × 480 = 360. On the other hand, in the JPEG compression processing performed by the compression processing circuit 23, one screen is divided into 8 × 8 pixel sizes, and then DCT processing (block coding) is performed in 8 × 8 units. Therefore, the upper and lower mask boundary lines are not a multiple of 8, and do not coincide with the block boundaries as shown in the enlarged view of FIG.

It is generally known that in block coding, when a large edge portion occurs in a block, mosquito noise tends to occur in this block. If this is adopted, even if the mask processing circuit 22 is provided in front of the compression processing circuit 23 to aim for the above-described effect, mosquito noise is likely to occur again, and the effect is diminished.

Therefore, in this embodiment, in order to prevent the effect from being weakened, the upper and lower mask portions are each set to "56" pixels and are set to multiples of 8 as shown in FIG. For this purpose, the upper mask position discriminating circuit 34 requires 22 horizontal synchronizing signals corresponding to the vertical blanking period of the video signal coming from the counter 33 for each field and 28 signals corresponding to the mask screen period. The lower mask position determination circuit 35 detects a total of 50 horizontal synchronization signals with the horizontal synchronization signal, and detects 184 horizontal synchronization signals. As a result, although the aspect ratio of the image display section is not exactly 9:16, it is almost the same, and does not affect the screen effect.

In this embodiment, encoding is performed by 8 × 8 blocks in the vertical and horizontal directions. However, the present invention is not limited to this. The mask area may be an integral multiple of a. In this embodiment, the scanning line 525 in the NTSC system is used.
As described in this system, the scanning line 6 in the PAL system is used.
Naturally, the present invention can be applied to 25 systems and the like. Further, in the present embodiment, the description has been given of the case of the digital VTR integrated with the camera. However, the present invention is not limited to this. For example, a video disc reproduction or a cinema mode signal (or letter If the signal is a box signal), it is naturally applicable.

[0036]

According to the present invention, a compression processing error (mosquito noise) in an image display portion is reduced, further improving the image quality, and reducing the circuit size and cost.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a camera-integrated digital VTR employing a video processing circuit according to an embodiment of the present invention.

FIG. 2A is a diagram for explaining a display screen having an aspect ratio of 3: 4. (B) is a diagram for explaining a display screen of the cinema mode in which the aspect ratio is 9:16.

FIG. 3 is a detailed block diagram of the mask processing circuit 12.

FIG. 4 is a signal waveform diagram entering a mask processing circuit 12;

FIG. 5A is a diagram for explaining the number of pixels of one screen of a luminance signal in the NTSC system. (B) is an explanatory diagram in the case where the aspect ratio of the display screen is 9:16.

FIG. 6 is a diagram for explaining a mask boundary in a screen mode according to the present invention.

FIG. 7 is a block diagram of an image compression apparatus employing this embodiment.

FIG. 8 is a diagram for explaining an operation of a zigzag scanner in the image compression device.

[Explanation of symbols]

 Reference Signs List 20 camera section 21 camera signal processing circuit 22 mask processing circuit 23 band compression processing circuit 24 recording process circuit 30, 39, 40, 41 input terminal 31, 38 switch 32 inverter 33 counter 34 upper mask position discriminating circuit 35 lower mask position Discrimination circuit 36 RS-FF (RS Philip flop) 37 OR circuit

 ──────────────────────────────────────────────────続 き Continuation of the front page Examiner Akira Suzuki (56) References JP-A-5-145903 (JP, A)

Claims (1)

(57) [Claims] 1. A digital video signal processing circuit for performing a predetermined band compression process on a digital video signal to be displayed in a predetermined size by a band compression processing circuit employing block coding. A masking means for masking a part of the digital video signal to be displayed as an image is provided in the former part, and the vertical masking processing in the masking means is set so that the masking boundary coincides with the boundary between blocks. A digital video signal processing circuit.