JP2726668B2 - Doppler sonar velocity measurement system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]   The present invention relates to a Doppler effect velocity measuring device, in particular,
Present ship speed with acceptable error under high acceleration
And when the ship is at constant speed, smooth speed
Speed measurement mounted on a ship capable of presenting data
Related to the fixed device. [Conventional technology and problems to be solved]   Doppler velocity range finder or measuring device
Sonar signal producing significant scattering at calculated velocity
The signal produces individual processed reflected waves. Calculated speed
Why the degree or measurement speed has a substantial variation from reflection to reflection
There are many. One reason is that typically ± 7.5%
Finite of conventional sonar velocity measuring device causing puller spread
Is the beam width. In addition, a Doppler speed measurement device is installed.
The motion of the loaded vessel (ie,
And longitudinal pitching) are transducers
Causes movement. In addition, sonar speed detection allows the
Signal reflected from a body of water as if in a large body of water
Depends on the speed of the water itself.
There is a degree of diffusion component. Finally, generally, the higher the
Signal / noise ratio, so a very small amount of speed
There is ambient noise that causes indeterminacy of   For smoothing the data received from each sonar transmitter
From the continuous many valid readings of the Doppler velocity
Data before being given as output of the speed measurement device
Averaged. Speed updates and power changes that occur approximately every 5 seconds
The multiple signals reflected from the reflective surface at
Averaged for repetition rates that are low enough to avoid
The number of reflected components of a pulse is typically between 9 and 36.
You. The averaging signal is also 0.1, 0.
2, 0.3 or 0.4 knots (1 nautical mile / hour) fixed through
-Subject to rate limits. For this reason, Doppler measurement
The speed of the ship resulting in the output of the
It cannot change beyond the slew rate limit. In fact, all
All ships have maximum speed change per 5 second upward speed update
A speed change of 0.1 knots was used. Low acceleration
Large merchant ship, a small slew rate of 0.1 knots
In order to follow the acceleration sufficiently,
For providing substantially constant speed data for receiving
It was gaining.   Ship acceleration is 0.1 knots per second at 5 second update rate
Ship that cannot follow the speed update
Error rate measuring device can measure speed even under constant conditions.
Accurate at high accelerations, even when readings are acceptable
It was found that it lacked presentation of speed information. this
Updating the system cycle to address these shortages
The rate is increased to substantially one update every second,
Sonar Doppler reflected wave number averaged by a factor of 4
To produce nine reflections per cycle
From the raw data processed by the Doppler
Substantially large variation in Doppler frequency with each update
Is caused to occur. Delays that the speed measuring device can accept
To track acceleration up to 20 knots per minute
Therefore, a filter matching the binary value was added. This 2
Decimal filters are 0.1, 0.2, 0.4 and 0.8 per update
Has the capacity to produce four knot slew rates
It was.   The binary adaptive filter worked as follows. Past
Speed reading is V_N-1Knots and gate width
To G_N-1If so, the first step is the past speed
Reading V_N-1At that time reading V_NBy deducting from
Output difference at knot Δ_NIs generated. Δ_NIs G_N-1Beyond
Then, if Δ_NIs positive, the output is (V_N-1+ G_N-1)When
And Δ_NIs negative, then (V_N-1−G_N-1). I
In the case of deviation, Δ_NIs G_N-1Filter passes the value G
_N-1To the next higher tolerance for the presentation of the next reflected signal
Will be added. Alternatively, if Δ_NIs G_N-1Yo
If it was smaller, the speed reading at that time V_NIs output
And the gate value G_N-1Is changed to the next smaller increment.
If Δ_N= O, the speed output does not change and
G_NWill decrease by one increment. It has been updated
Such a selection process of changing the gate value, resulting in speed output
Process shall be continued for each cycle of the speed measurement system.
And   Filters made to follow the driving rules so far
During constant speed navigation, the slew rate is updated to a maximum of 0.1 knots per update.
Try to lower to a small value. Acceleration or deceleration
When filtering, this filter changes the speed with a satisfactory error.
Open the gate width to try to track. However,
Even during constant speed navigation following acceleration or deceleration,
The coarse speed reading given to the
As a result, the open state is maintained up to a value larger than that. This
The digital speed display, like
Shows the variation in degrees. As a result, the filters described here
The user of the speed measurement device to be used must be able to change the displayed speed.
Expected constant speed of a ship navigating at a constant engine speed
The display is not accepted because the counter has been activated
Find out what is not. The line 110 in FIG.
Simulates a speed of 10 knots with a variation of ± 2 knots
Research using FM oscillators in Doppler systems
Prior art simulations of simulated signals obtained in the
The variation in output speed as a function of filter time.
You. Lines 111 and 112 each have a speed variation of ± 2 knots.
Simulate 10-20 knots acceleration / deceleration per minute
This is the output speed when the camera is turned on. Speed fluctuations during the acceleration period
No acceleration / deceleration of 10 to 20 knots per minute each
The speed output curves 113 and 114 were obtained. Speed 10 knocks
Output speed readings, even under constant navigation conditions
Desirable about ± 0.5 knots for an average speed of 10 knots
It can be seen that no fluctuation occurs. [Means for solving the problem]   Accordingly, a primary object of the present invention is to provide a ship which is in transit, i.
When the speed is in the range, the output speed fluctuates and the speed gate width is manually controlled.
Hits the system cycle like never before
Down to a value equivalent to a speed change of up to 0.1 knots
While accelerating according to the capacity of the prior art filter
An object of the present invention is to provide a speed measuring device for maintaining a degree. Above and others
The purpose of the ship is to determine whether the ship is accelerating or navigating.
Automatically adjusts the speed gate when the gate width and according to the speed
The variability of the measured if it is under navigational conditions
Speed, and detects that the vehicle is accelerating or decelerating.
By opening the gate when coarse data is displayed,
Indicated by the measuring device for the true speed in the speed state
Improved delay to reduce delays in display output speed
This is achieved by providing a digital adaptive filter. like this
The digital filter of the present invention
Data, the coarse speed data and how often the speed gate
In the previous cycle to determine if it was open or closed
Detects the sign of the error between the data provided by the device
I do. If there is a sign change, this filter is fast.
Close the gate until the maximum change per cycle is
It should be only 0.1 knots per vehicle, but the sign
If there is no change in this filter, the filter is programmed
The speed gate is opened and closed by a method.   For the above mentioned features and other features of the present invention, see the drawings.
Will be apparent from the following description. 〔Example〕   Doppler using digital adaptive filter of the present invention
Speed measurement system tracks acceleration up to 20 knots per minute
And at the same time the ship sails at a constant speed
No excessive fluctuations in the displayed speed
Digital display. This digital
Filter is used to enter the previous value of digital display speed.
Value that changes the polarity,
Error from positive value to negative value or vice versa (error
Difference) Whenever there is a signal change, the digital display
To limit the speed variation indicated by 0.1 knots
Has been established. During operation, if the ship is accelerating, speed measurement
The display speed provided by the positioning device tracks the actual ship speed.
In this case, the continuous error signal is
The filter speed gate is digitally displayed
Update sites for a number of speed measurement systems with relatively small speed values
Allow to keep up with the actual ship speed in the cruise
Automatically opened for During acceleration or deceleration mode,
Error signal does not change sign, and
Speed change given by the speed gate
Increases with the amount given. During navigation at a constant speed,
The display speed of the scale is opposite to the direction of the previous cycle.
Small speed gate spacing for each cycle in the direction
And the displayed output speed is
Qualitatively smoother.   Digital used in Doppler velocity measuring device
Filter has a final speed reading of V_N-1, Gate width
G_N-1And the speed reading V_N-1Sign of the speed change that caused the
Operating in the following operating modes, assuming that
You. This change is Δ_N-1Is represented by The following steps
Is caused by the digital filter. Step 1: Using the Doppler speed measurement device's coarse speed data
New speed value V_NSpeed value previously displayed from
V_N-1And subtract the difference value Δ_NGet. Step 2: Δ_NIs the previous cycle Δ_N-1Same or opposite speed difference
Is determined. Step 2A: Δ_NIs Δ_N-1If they have the same sign as
Proceed to step 3A, B or C. Step 2B: If the sign is reversed, go to step 5. Step 3A: If Δ_NIs stored in the digital filter.
Gate value G_N-1Digital filter
Is the output speed reading V_N= V_N-1+ G_N-1And the gate value is
Only a large allowable increment to G_NTo be increased. Step 3B: If Δ_NIs G_N-1If less, the value V_NBut di
Digital speed display, gate G_N-1Is the next smaller tolerance
Decrement is reduced to a new value G_NBecomes Step 3C: If Δ_N= O, digital display data
V as_N= V_N-1And the gate value G_N-1The smallest
Value G_NTo decrement. Step 4: Speed value V by step 1_{N + 1}To get
No. Step 5: Error value Δ_NHas the value Δ_N-1Change from the sign of
To be Step 5A: If error value Δ_NIs a relatively low speed
Labyrinth, V_N(V_N-1-0.1 knots). Step 5B: If error values are biased to relatively fast speed
If V_N(V_N-1+0.1 knots). Both
In steps 5A and 5B, set the gate width to (G_N± 0.1 knock
To the last error Δ_NMaintain the sign of Step 6: Return to step 1 to obtain the value V_{N + 1}Proceed to
Repeat this process.   The invention is intended for use in certain Doppler systems.
Without limitation, the adaptive digital
・ The filter is a commercially available Doppler system Ra
Developed for use with ytheonDSL-250N
is there. With forward and backward transmit and receive transducers
A similar speed measurement system using Doppler frequency,
U.S. Pat.
No. 893,076. Conventional Doppler
FIG. 2 shows the printed wiring board 10 of the speed processing device of the system.
In the form of a block diagram. Each person
Tracking signal 11, before and after producing coarse speed data in the direction
12 are processed in the Doppler system and
A Doppler signal is given to the code 10 and this signal
System is transported to a body of water or ocean floor
Represents the gross data rate of a moving vessel. This crude data
Error caused by pitching and yawing of the ship
Disturbed by true Doppler data. This coarse
Data is the Doppler system of the coarse data register 13.
Generated once per system cycle. Also, do
The coarse data held in register 13 is
Doppler system as filtered version of data
Digital tables being presented to system users
And a register 14 for holding indication data. Register 1
The coarse data and display data in 3 and 14 are
Printed wiring of adaptive filters from Sessa's printed wiring board 10
Sent to board 15. Resistor board for adaptive filter 15
Data registers B and A.
The coarse data and the display data of the
Double the period during which signals are sent and received by the Doppler system
Number (9 or 3 for Raytheon DSL-250N system)
6) Transfer by the cycle start pulse generated during a certain period
Before the signal is applied to the coarse data register 13.
Averaged. The cycle start pulse is cycle
When the start pulse is generated, it is stored in registers 13 and 14.
Transfer the data to registers B and A, respectively. Adaptation
Filter 15 filters this data by 2^NSet generator 7 to 0,
To set the value of N to 1, 2, or 3
It operates in the manner described below. Generator 7 set
Value2^NIs the gate width that updates the display data register 14.
Used to secure a certain gate width value for creature 17.
To be used in the next system cycle
It is stored in the generator 7 (left and right shift registers).   The gate width is one of 1, 2, 4, and 8 μsec.
Gate width generator 17 is a DSL-250N Doppler system
Clock printed wiring board 18 is placed. Generator
A gate width of 17 is used in conjunction with clock 19 and
1, 2, 4 or just before the system cycle start pulse
Display data in register 14 for only eight clock pulses.
Clock 19 is one megacycle
Clock.   Next, in FIG. 3, the adaptive filter 15 is configured as follows.
Works with Display data of register 14 and register 13
Each of the crude data of the sonar system
Generator in response to a number (typically nine) of transmitted pulses
In response to the cycle start pulse 190 generated by 30
Each of the adaptive filters 15 once every system cycle
To the registers A and B at the same time. Regis
The data at A and B are stored in comparator 31
And compare whether A> B, A = B or A <B
judge. The information of A> B and A <B is stored (stored)
Device) 50 and their values are stored (storage device)
Compare with A '> B' and A '<B' stored in 60
Where A 'and B' are the previous filter sizes.
Represents the values of registers A and B stored at the end of the
You. If the output of comparator 31 is two consecutive cycles
If not the same, the preset counter
Filter gate width 2 given on line 160 by 16^N
Will be reduced from its last value N to N = O.   If A and B in reading the previous and then data
No change in the output of the comparator 31 in the compared value.
If so, register A is in the last filter cycle
Stored value 2^NIs incremented or decremented. If
The speed value stored in register A is higher than that in register B
Is smaller, the register A is incremented.
Decrements. Counter 2 count 2^NIs a register
Output of register A when being clocked to A
Is compared with the data in register B.
The data in these two registers must be equal
The value N stored in the register 7 increases to (N + 1)
Where N cannot exceed 3. Only
If, during this clock cycle, register A
Data equals the data in register B
If the clock operation stops at the value A = B,
Two^NIs 2^N-1Where (N−
1) cannot be less than 0.   Under any of the above conditions, the filter 15
The last value N stored in the data
To the clock width generator 17 in
A '> B' at store 60 in the cycle and
As a result in store 50 to be used as A '<B'
Store the resulting values A> B and A <B, then
Program unit until energized by the
The filter cycle for cut 9 ends.   FIG. 3 is a block diagram of the digital adaptive filter 15 of FIG.
FIG. 3 shows a detailed block diagram. The operation of the filter 15 is as follows
It is. First, the Doppler velocity measurement system
Data on the speed of the ship where the system is located
Digital measurements) and in system registers
Display data (filtered coarse data)
A preset cow in response to the cycle start pulse 190
Counter B and preset up / down count
Provided to the user A. The filter circuit 15 will be described in detail later.
The data in counters A and B as described in
Working, 2^N(Register) 7 to 0, 1, 2 or 3
To the value N. Via inverter 162 and line 161
Value 2 set in generator 7 given as^NFor
And the value 2^NEither 1, 2, 4 or 8 microseconds depending on
At the output 160 of the preset counter 16
Secure the width value. Gate width 2^NIs AN by counter 16.
Given to D-gate 8, other inputs of this AND gate
Is the clock from the clock / generator 100 with a frequency of 1 MHz.
Signal. The output of AND gate 8 is up / down
Provided as a clock input to the counter A
Do counter A (depending on the output state of inverter 82)
Doppler by 1, 2, 4, or 8 clock pulses
.In visual display of digital output of system
Increases or decreases the display speed.
If the pulse is a device used in a speed measuring device,
They correspond to 0.1, 0.2, 0.4 and 0.8 knots, respectively. Sa
The cycle start pulse generator 30 is configured to pre-
Cycle start pulse train 190 in response to the specified number of pulses
give. Typically, 9 sonars per cycle start pulse
・ Pulse is present and counter B by sonar system
The raw data given to the Doppler system 33
9 Doppler counters that meet pre-established reliability standards
It is the average value of the injection component. Cycle start signal from generator 30
Lus 190 has the coarse data of register 13 preset
Loads counter B and displays data in register 14
To the preset up / down counter A
Load and initialize filter program unit 9
I do.   FIG. 4 shows the program generated by the program unit 9.
4 shows a timing sequence. Pre-set cow
A and B respectively receive the display data and
Triggered by cycle start pulse 190 to accept data
After being activated, program unit 9 outputs 1 to its output 1.
To generate two pulses, the output A> B of the comparator 31 and
And store the state of A <B
Behave. At this time, the previously stored output from store 50
Is the output of comparator 31 in each previous cycle.
Exclusive OR gate on corresponding output of store 60 that was in power state
The exclusive OR is performed in the port circuit 51. If Compare
The output from the data 31 changes from A> B to A <B or vice versa.
If it changes, the exclusive OR circuit 51 outputs its output and
1 microsecond pulse at output 3 of gram unit 9
Both pass through the AND gate circuit 52 and through the OR gate 80
Clear shift register 7 and program unit 9
Signal level. Shift cash register
To clear the star 7, the maximum allowable data change amount is set to 0 every update.
You will be limited to one knot. Program Unit
In order to clear (g), this device must be used in the timing diagram of FIG.
Time T_oAnd program unit 9 is now
Wait for activation for next cycle start pulse on line 32
Will be.   The exclusive OR circuit 51 includes two conventional exclusive OR circuits (shown in the figure).
Without). One of these exclusive OR circuits
Has an input A> B for two consecutive cycles.
Other exclusive OR circuits are input during the same two consecutive cycles
A <B. The output of each of these exclusive ORs is AN
An OR circuit (not shown) before being applied to D gate 52
Union).   If exclusive OR circuit 51 did not change its output
That is, if A> B in two consecutive cycles
Was true or A <B is two consecutive cycles
If true in program unit 9
Produces one pulse output on its output 3 and
The counter 16 is initialized. This counter 16
From shift register 7 resulting from the filter cycle of
Of the number existing on line 161 by the pulse on output 3.
Will be set. As soon as it is set in advance
At the same time, counter 16 provides an output signal on line 160, which
The counter 16 clocks up to its preset count.
Until the program unit 9 is shut down
Prohibits changing the state of pulse output. Counter 16
Gate width on line 160 generated by is also AND gate
8 so that the AND gate 8 has 1, 2, 4 or
Presets up / down 8 clock pulses
Allowed for counter A. Set counter 16 in advance.
The action to be set is to provide the correct polarity to the counter 16.
After being inverted by inverter 162 to provide
On line 161 provided by the output of register 7
This is done by a 3-bit number. Counter A is a line
In response to the gated clock pulse on
To the U / D terminal of counter A via barter 82
According to the state of the output A> B of the comparator 31 given
Being counted up or down
Become. Therefore, if the comparator 31 has its A> B output
Counter A counts at terminal B at terminal
If it produces a signal that is smaller than
The polarity of the signal applied to the U / D terminal of
Clock A supplied to its input line 81
Increase by a number not greater than the number of
Reverse. If a clock pulse is given on line 81
The polarity of the output of the comparator 31 during the
For example, if the load R /
The L input causes the shift register 7 to be set, resulting in a shift
The binary output of the register output (OUT) is the shift register
Is present at output terminal 4 of program unit 9.
Get another "1" when clocked by a pulse
Will do. The program unit 9 outputs
4 is advanced to produce one pulse, and
Line 16 when set counter 16 completes its count
Remove the inhibit signal on 0. In addition, the program unit
The output pulse at output 4 of clock 9 clocks register 7.
The value "1" to the digit appearing at the output of register 7.
Add to the number of barrels. This other "1" is a preset
The gate width given by the counter 16 and the previous two^N
2 from the value of^{N + 1}To increase. If shift register
The digital number included in the star 7 is
If all three output lines are "1",
Another “1” is added to the contents of the shift register 7
This means shifting “1” from one end of the register
This has the effect of inserting "1" into the other end of the star. others
Therefore, there is no change in the contents of the shift register 7,
The width is a shift that gives three "1" s to the three output lines.
Register 7 and its maximum of 0.8 knots per corresponding update
It remains fixed at the value.   If the preset counter 16 clock cycle
During the output A> B or A = B, there was a change in the state
Then, the load R / L input to the shift register 7 is
Register 7 at output 4 of program unit 9
When clocked by a pulse, the OR gate 53 registers
Zero is added to the shifted output of star 7 to its least significant digit
To be set by the OR gate 53.
You. One input to the OR circuit 53 is the output of the comparator 31.
From force A = B. Other input to OR circuit 53
Is stored in the store 50 at the above clock operation interval.
Stored state A> B and A> B output of comparator 31
State of the power terminals, which are
Given to. Then the previously described operation sequence
Will be generated by the preset counter 16.
The gate width obtained is determined by the shift register 7
Must hold all zeros at the three output lines in
If the last gate width is 2^N-1Only decrease. in this case,
The system update stays at its minimum of 0.1 knots,
One clock pulse in the next cycle of the filter
Provided to the up / down counter A
Means When converting the pulse at terminal 4,
The program unit 9 sends a 1 μs
In the store 50, where A> B and A <B
State to the store 60. At the end of pulse 5, the next
Until the first system cycle pulse 190 occurs.
The pulse 6 from the gram unit 9 passes through the OR circuit 80
Reset the program unit 9. Register 7
Newly obtained value 2^NAt this time, the next system cycle
Prior to the start pulse, the system must update the display register 14
It is provided for the gate width generator 17 of the stem.   FIG. 5 is a diagram of FIG. 1 obtained by a filter of the prior art.
Digital adaptation of the invention under the same conditions as indicated in
The result obtained by the filter is shown. Fig. 5
Lot 150 contains the simulated sonar reflected signal
3 read out from the speed display 2 under different conditions.
It is an analog display showing a digital value. Plot 150
The part 151 shows the variation of ± 2 knots at the rate of 1 second.
Display data output at a constant speed of 10 knots
Is shown. Compare plot 151 to plot 110 in Figure 1.
Then, at a constant speed using the filter of the present invention,
At least in the variation of the output speed in register 14
A significant 3 to 1 reduction occurs when using the filter of the present invention.
It can be seen that it can be obtained. ± 2 knots fluctuate and fluctuate
Acceleration or decrement between 10 and 20 knots per minute in the absence of
The high speed blots 152, 153, 154
Filter and prior art filters are equally good under accelerated conditions
It shows that you follow well.   Having described one preferred embodiment of the present invention,
Those skilled in the art will recognize that other embodiments incorporating the concepts of the present invention may be used.
It will be clear that you can. Therefore, the present invention is disclosed in the text.
It should not be limited to the embodiment shown, but rather an acronym
Should be limited only by the appended claims.
You.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing the output speed displayed at a constant speed and acceleration / deceleration using a prior art filter in a Doppler speed measurement system, and FIG. 2 is a prior art Doppler. FIG. 3 is a block diagram showing the interconnection state of the adaptive filter of the present invention with the components of the speed measurement system, FIG.
FIG. 4 is a block diagram showing the digital adaptive filter of the present invention, FIG. 4 is a timing diagram showing the output states of program units used in the digital adaptive filter, and FIG. 5 is the same input condition as in FIG. FIG. 6 is a diagram showing a display speed output provided by the digital adaptive filter of FIG. 7 ... ^2N generator, 10 ... Doppler system speed processing unit Printed wiring board, 11, 12 ... Back and forth tracking signal, 13 ...
… Coarse data register, 14… Digital display data holding register, 15… Digital adaptive filter, 16… Counter, 17… Clock width generator, 18… Printed wiring board, 30… Cycle start pulse generator , 50, 60 ... store, 100 ... Doppler system speed processor printed wiring board, 160, 161 ... line, 162 ... ... inverter, 1
90: Cycle start pulse train.

Claims (1)

(57) [Claims] A Doppler sonar speed measurement system comprising a coarse speed data register and a display data register, wherein the display data is filtered coarse speed data, wherein the coarse data is transferred to a first register of an adaptive filter. Means for transferring the display data to a second register of the adaptive filter; means for comparing the transferred data in the first and second registers; and data compared in the first and second registers. Means for storing a sign of the difference between: establishing a permissible speed change value for said display data for each comparison, wherein said permissible speed change is determined by the magnitude and sign of each comparison; Said allowed when the sign given by the comparison of the first and second registers changes from the sign of the previous comparison stored in the means for storing said sign Doppler sonar velocity measuring system comprising a means for reducing the degree change in the minimum predetermined value, the. 2. A method of filtering the coarse data of each cycle of the Doppler velocity signal of the sonar to obtain a display value of the Doppler velocity, storing a previous coarse velocity value _V′N−1 , and applying a velocity value before filtering. V _N-1 is stored, and a speed gate width G _N-1 is generated, and a difference Δ _N-1 between the filtered speed value and the coarse speed value is ΔN _-1 = V
_N-1 -V 'acquires the _N-1, to determine the sign of the change in the polarity of the delta _N-1, Step A: raw data rate V' to determine the new value of _{N,
V 'N [Δ N = (} V' N -V N-1)] by subtracting the velocity value V _N-1 multiplied by the previous filter from the value _{Δ N = V 'N -V N} -1 symbols and it obtains the difference, step B: comparing the value Δ _N Δ _N-1 and determines whether the code has changed, if no code changes, delta _N is the speed gate width value G _N-1
Determining whether exceeds, if delta _N if is greater than G _N-1, giving the velocity value _{V N-1 + G N-} 1 multiplied by filter in the first register, the value G _N-1 following Is increased by a large allowable increment to G _N, and if Δ _N is less than G _N−1 , the value V ′ _N is provided to the first register and the gate value G _{N−1 is set} to the next smaller allowable value G _N is reduced to _N, if if delta _N is zero, the value V _'N gives the first register,
The gate value G _N-1 is reduced to the next smaller tolerance G _N , retaining the sign of the previous difference reading error Δ _N-1 , returning to step A to return the coarse data input V ′ in the next cycle. by repeating the steps of the process with respect to _{N + 1,} it determined that acquires the Doppler velocity value V _{N + 1} times the following filter, if step B is, the sign of the delta _N and delta _N-1 is changed if you and if the difference is changed to a lower speed, the value V _N is equal to V _N-1 -V ₀ (where, V ₀ is the minimum allowable change value in display speed value), G _N was set to V _0, and holds the sign of the difference value delta _N, if if step B is, determines that the sign of the delta _N and delta _N-1 is changed, and if the difference is higher speed if changes to the value V _N is equal to V _N-1 + V _0, sets the G _N to V _0, and holds the sign of the difference delta _N, the process returns to step a, the following service Repeating the process steps for the coarse data entry in the cycle to obtain the next filtered Doppler velocity value V _{N + 1} . 3. A Doppler sonar velocity measurement system, comprising: means for periodically obtaining coarse data corresponding to a Doppler velocity measured during one cycle; and Doppler filtering and filtering the periodic coarse data. Means for obtaining velocity data; and means for storing filtered Doppler velocity data from a cycle prior to the one cycle, wherein the means for obtaining the filtered Doppler velocity data comprises: Means for comparing data with the filtered data of the previous cycle to provide a difference signal; means for varying the stored filtered data to reduce the difference signal; and In response, determine whether the sign of the amplitude of the difference signal has changed and determine whether the difference signal has been reduced to zero. Means for determining whether or not, in response to the difference signal, means for stopping the means for changing the stored filtered data in response to a zero output from the comparing means; and Means for limiting the amount by which the changing means can change the magnitude of the stored filtered data in response to the change of the sign of A Doppler sonar speed measurement system comprising: 4. A Doppler velocity measurement system comprising a coarse velocity data register and a display data register, wherein the display data is filtered coarse velocity data, wherein the filter comprises a preset register B and an up / down register A. Means for generating a cycle start pulse for generating a periodic start pulse; means for transferring the coarse speed data and the display speed data to the preset register and the up / down register respectively in response to each start pulse; Connected to the outputs of the registers A and B, the comparison output A>
A comparator means for generating values of B, A = B and A <B; a programmer pulse means connected to the start pulse generating means for generating a pulse train of 1 to 6 in response to each start pulse; A pulse source and a 2 ^N binary value generating means responsive to a pulse at a fourth output terminal of the programmer pulse means (where N
Is a decimal number), a preset counter set to a ^2N binary value provided by the generating means and counted down by the clock pulse, and an output of the preset counter decremented by the clock pulse Responsive to a state, and in response to the clock pulse, connected to the register A to generate a clock pulse, depending on the state of the signal applied to the U / D terminal of the register A by the A> B output of the comparator. A first for causing the counter to count in a determined direction
And first and second storage means for storing the states of the outputs A> B and A <B of the comparator in successive first and second cycles, respectively. The means is responsive to a pulse at a first output terminal of the programmer pulse means after activation by the cycle start pulse, further comprising a first OR circuit; and an output A of the first and second storage means. A first exclusive OR circuit connected to B and A <B to provide an output signal to a first input of a second AND gate;
An AND gate connected to the output of the first exclusive OR circuit and the second output terminal of the programmer pulse means to provide a signal to the clear input of the ^2N generating means; > B and the first exclusive OR
In response to the output A> B from the last cycle of the circuit,
A second exclusive OR circuit for providing an output signal to a second input of the first OR circuit, wherein an output of the first OR circuit is connected to an R / L terminal of the ^2N generating means. The output of the preset counter is provided as an input to a forbidden terminal of the programmer pulse means so that the programmer pulse means can output from its fourth output terminal until the count of the preset counter counts down. Inhibiting the generation of a pulse clocking said ^2N generating means, said programmer pulse means providing a pulse to said second storage means at its fifth output terminal at the end of the pulse at a fourth output terminal. And give
Transferring the outputs A> B and A <B of the first storage means to the second storage means, providing a second OR gate; and providing the programmer pulse means at its sixth output terminal A pulse is applied to one input of the second OR gate at the end of the pulse at the fifth output terminal, the second input of the second OR gate being connected to the second AN gate.
The second OR gate is connected to the output of the D-gate, the output of which is connected to the clear input of the programmer pulse means, causing the programmer pulse means to respond to the next occurring cycle start pulse. Doppler velocity measurement system, which is a filter. 5. The first exclusive OR circuit comprises third and fourth exclusive OR circuits.
The third exclusive OR circuit has an input connected to the output A> B of the first and second storage means, and the fourth exclusive OR circuit has an input connected to the first And the second
And a third OR circuit having an input connected to the output of the third and fourth exclusive OR circuits, the output of the third OR circuit being connected to the output A> B of the storage means. 5. The system according to claim 4, wherein the system is connected to one input of a second AND circuit. 6. A method in a sonar Doppler velocity measurement system for providing a series of coarse data, measured velocity data, and providing a corresponding series of filtered display velocity data, comprising: generating first coarse velocity data; Comparing the relative magnitude of the filtered display speed data resulting from the filtering operation of the speed data with the relative magnitude of the resulting second coarse speed data and the filtered display speed data; Determining from the comparison whether there is a reversal of an approximate magnitude, and when the reversal occurs, limiting the amount by which the filtered display speed changes in the direction of the second coarse speed data. How to be. 7. 7. The method of claim 6, wherein said relative magnitude comparison is performed by use of a comparator whose output varies with the magnitude of the coarse velocity data and the filtered velocity data.