JP2720792B2 - TEI mapping search method for frame multiplexing protocol - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame multiplex protocol processing system, and more particularly to a TEI mapping system for each subscriber.

[0002]

2. Description of the Related Art Conventionally, this type of TEI mapping processing is used in frame multiplex protocol processing of communication equipment. In such processing, the subscriber unit (UDLC
An allocation area for the maximum number of mappings is provided for each I), the correspondence between the upper address indicating the link unit of the actual link state memory, the SAPI and the TEI of the corresponding DLCI, and the setting flag are set by software processing. Before the necessary information is read and written, a search is made of an allocation area for each UDLCI, and an upper address in link units of a real link state memory corresponding to the corresponding DLCI is obtained. In the second example of the conventional TEI mapping process, an area for holding a set number for monitoring the maximum number of mappings for each UDLCI and an allocation area for the maximum number of mappable links in the real link state memory are provided. The correspondence between the upper address indicating the link unit of the link state memory and the corresponding DLCI and the setting flag are set by software processing, and before the necessary information on the actual link state memory is read and written, the assigned area is searched, and the corresponding D
This is realized by obtaining the upper address of each link of the real link state memory corresponding to LCI.

[0003]

In the first example of the conventional system, before the necessary information is read and written on the real link state memory, it always matches the corresponding DLCI in the allocated area for the maximum number of mappings for each UDLCI. It is necessary to search for the allocated area, and the DLCI value must be UDLCI, SAPI, TE
The load of the data operation divided into I and the comparison processing of the set number of data is large, and there is a problem in that the throughput of data transmission / reception is reduced, and the performance degradation of command transmission and response transmission which requires prompt response of a response.

In the second example of the conventional method, in the worst case, it is necessary to search the allocated area of the real link state memory for the maximum number of links that can be mapped, and cannot be applied to the frame multiplexing protocol processing with a high degree of multiplexing.

SUMMARY OF THE INVENTION An object of the present invention is to provide a frame multiplexing protocol which has a small hardware scale, eliminates software processing related to TEI mapping search, and can perform high-speed processing of reading and writing of a real link state memory corresponding to each DLCI at the time of TEI mapping. The purpose of the present invention is to provide a TEI mapping search method.

[0006]

The TEI mapping search method for a frame multiplexing protocol according to the present invention comprises a hardware DLCI register for setting a DLCI value by software, and a wiring connected to the DLCI register in the hardware. Register holding SAPI and TEI which can be configured by U and U holding subscriber unit
DLCI register and upper address are for each subscriber unit
The assigned, the lower address assigned to each storage area of the mapping is the upper address of the actual link state memory that is allocated to the appropriate DLCI and S bits and SAPI and TEI indicating the setting "1" in each area JMADR
A TEI mapping search table for holding a DLCI value in the DLCI register, an address counter for sequentially outputting lower addresses of the TEI mapping search table from the time the software sets the DLCI value in the DLCI register, and a setting value read from the TEI mapping search table. The SA
Comparing means for sequentially comparing the PITEI register value when the S bit is "1"; and latching the JMADR read from the TEI mapping search table when the comparison result of the comparing means indicates a match, It has a latch means for outputting to the upper address of the real link state memory, and after the software determines the JMADR, outputs the lower address of the real link state memory to read and write necessary information.

[0007]

In the case of performing by software processing, it is necessary to perform data operation (bit shift, AND, comparison, etc.) on SAPI and TEI for each UDLCI for each search, and to search for the assigned actual link state. growing.

In the present invention, the actual link state memory can be read / written only by setting the DLCI by software (which is almost the same as ordinary memory read / write). Since hardware searches, processing can be performed at high speed. On the other hand, the hardware configuration includes a DLCI register (23 bits), a comparator of 23 bits (DLCI register and mapping memory data), and a counter (TEI in the current protocol) capable of counting the number of assignments.
The number of assignments is 8 or 16) and only extra wiring is required, and the table memory and the actual link memory are originally required in the above processing.

Therefore, TE to real link state memory
After the I mapping is set, the TEI mapping search at the time of protocol processing for each DLCI can be processed at high speed without software.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a hardware block diagram of one embodiment of the present invention, and FIG. 2 is a configuration diagram of a DLCI register 1, a TEI mapping search table 9, and a real link state memory 12. Software is DLC in DLCI register 1.
Set the I value. DLC held by DLCI register 1
As for the I value, bits 21 to 22 indicate the SAPI value, bits 07 to 19 indicate the UDLCI value, and bits 00 to 06 indicate the TEI value. A SAPITEI register 2 holding SAPI and TEI, which can be configured only by wiring, and a UDLCI register 3 holding UDLCI, which are connected to the DLCI register 1 in hardware and provided in hardware, are provided.

In the TEI mapping search table 9, a UDLCI is connected to an upper address, a storage area for the maximum number of mappings is allocated to a lower address as one TEI mapping holding area 8, and a setting of "1" is made to each 1 TEI mapping holding area 8. It holds the S bit 4, SAPI5, TEI6, and JMADR7 assigned to the corresponding DLCI. MAX 110 indicates (maximum number of mappings-1) in UDLCI units.

In the actual link state memory 12 used in the protocol processing, the memory divided for each JMADR indicates the one link state memory 11 required for the protocol processing in link units.

When the software setting timing signal 21 is input, the UDLCI data from the DLCI register 1 is stored in the upper address 13 of the TEI mapping search table.
SAPI and TEI are output at comparator input 18. Also, at the same timing, the TEI is
Addresses are output in order of the maximum number of allocated areas in the mapping search table lower address 14. At this time, the SAPI, TEI data 16, S bit data 15, and JMADR data 17 are sequentially output from the TEI mapping search table 9. The comparator 22 compares the input data 16 and 18 with each other when the S bit data 15 is “1”.
A comparator output 20 for giving a timing to latch the ADR data 17 is output. The latch register 24 latches the JMADR data 17 at the timing of the comparator output 19 and outputs it to the upper address 20 of the real link state memory 12.

After the software determines the JMADR output, it outputs the lower address of the real link state memory 12 to read and write necessary information on the one link state memory 11. At this time, the detection of the JMADR determination is performed by the look-in of the JMADR determination display signal, the JMADR determination interrupt, the MA
This is realized by inserting another instruction during the maximum fixed waiting time determined by X1.

FIG. 3 is a diagram showing a TEI mapping search sequence according to this embodiment. The UDLCI in the DLCI value set by the software is output to the upper address 13 of the TEI mapping search table memory 9. TEI
The upper address 13 of the mapping search table memory 9 has the UDLCI in the DLCI value set by the software.
Is output. TEI mapping search table memory 9
The lower address 14 of (MAX1 +
The addresses of 1) are sequentially output. S every time the lower address 14 of the TEI mapping search table memory 9 changes
The bit data output 15, SAPI and TEI data output 16, and JMADR data output 17 are read. SA
The data output 18 of the PITEI register 3 and the SAPI
When the comparison result output 19 with the TEI data output 16 matches, the JMADR data output 17 is latched and output to the upper address 20 of the real link state memory.

[0017]

As described above, according to the present invention, after setting the TEI mapping to the real link state memory, each DLCI
At the time of processing each protocol, high-speed processing can be performed without software performing a TEI mapping search.

Also, the hardware configuration can be easily configured by wiring of software interface registers and registers in hardware, a memory for a TEI mapping search table which is originally essential, a counter for sequentially outputting addresses, and address allocation to the memories.

[Brief description of the drawings]

FIG. 1 is a TEI mapping search hardware block diagram showing an embodiment of a TEI mapping search method according to the present invention.

FIG. 2 is a configuration diagram of a DLCI register 1, a TEI mapping search table 9, and a real link state memory 12.

FIG. 3 is a TEI mapping search sequence diagram of the embodiment.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 DLCI register 2 SAPITEI register 3 UDLCI register 4 S bit 5 SAPI 6 TEI 7 real link state memory upper address 8 1 TEI mapping holding area 9 TEI mapping search table 10 maximum mapping number in UDLCI unit -1 11 1 link state memory 12 real link State memory 13 TEI mapping search table upper address 14 TEI mapping search table lower address 15 S bit data output 16 SAPI and TEI data output 17 JMADR data output 18 SAPITEI register data output 19 Comparison result output 20 Real link state memory upper address 21 Software setting Timing signal 22 SAPI and TEI comparator 23 TEI mapping search table lower address counter

Claims (1)

(57) [Claims] 1. A hardware DLCI register for which a software sets a DLCI value, and an SA that holds a SAPI and a TEI that can be configured only by wiring and is connected to the DLCI register in the hardware.
UDLC holding PITEI register and subscriber unit
And I register, upper address is assigned to each of the subscriber units, the lower address is assigned to each storage area mapping, S bits and SAPI and TE indicating the setting "1" in each area
I and a TEI mapping search table holding JMADR which is an upper address of the real link state memory allocated to the corresponding DLCI; and a lower address of the TEI mapping search table from the time when software sets a DLCI value in the DLCI register. An address counter for sequentially outputting, a comparing means for sequentially comparing the set value read from the TEI mapping search table with the SAPITEI register value when the S bit is "1", and a comparison result of the comparing means. The T
The JM read from the EI mapping search table
Frame multiplexing means for latching ADR and outputting to a higher address of the real link state memory, and after software determines JMADR, outputs a lower address of the real link state memory to read and write necessary information TEI mapping search method for protocol.