JP2718108B2 - Interleave circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interleave circuit, and more particularly, to an interleave circuit used for a digital communication system using an error correction code.

[Conventional technology]

2. Description of the Related Art In recent years, digital communication systems using error correction codes have been adopted in the field of satellite communication and the like. In particular, error correction codes used in the SCPC-PSK modulation / demodulation scheme include a BCH code of a block code and a self-orthogonal code of a convolutional code. However, these error setting codes can correct a bit error occurring at random, but have a drawback that they cannot cope with a burst error of several consecutive bits.

Therefore, conventionally, only in the case of a block code, an error correction circuit using a BCH code and the interleave circuit shown in FIG. 11 are combined to deal with a burst error of several consecutive bits.

Such an interleave circuit includes a frame counter 81 and address counters 82 and 83, as shown in FIG.
And data selectors 84 and 85, memories 86 and 87, and a selector
88 and a selector 89. The frame counter 81 receives the transmission request signal 101 and the transmission clock signal 102 which become "1" only when the transmission data signal 103 is inputted, and repeats "1" and "0" for each frame of the transmission data signal 103. It outputs a selector control signal 104. The address counter 82 is a counter for sequentially specifying the memory addresses of the memories 86 and 87 in the row direction from the first row, and the address counter 83 converts the memory addresses of the memories 86 and 87 to the left side. The data selectors 84 and 85 address the memories 86 and 87 by a selector control output 104 of the frame counter 81 and a selector control signal 109 having an inverted value of this signal, respectively. counter
This is a selector for selecting which of the address counters 82 and 83 to specify an address. The memories 86 and 87 both have the same row × column memory cell array, and have the same memory capacity as the number of bits of one frame of the transmission data signal 103.
An AM (random access memory) for writing and reading the transmission data signal 103 according to the polarities of “0” and “1” of the selector control signals 104 and 109, respectively. The selector 89 selects the memory output signal 117 while the memory 86 is reading, selects the data signal 118 while the memory 87 is reading, selects both signals, and multiplexes both signals. This is a selector for outputting to the outside as an interleave output signal 119.

FIG. 12 is a time chart showing the operation of the interleave circuit. In the figure, A, B, C,... Indicate the frame numbers of the transmission data signal 103, and “row” indicates that the memory addresses of the memories 86, 87 are sequentially specified in the row direction from the first row. The “column” in the outputs 115 and 116 of the data selectors 84 and 85 indicates that the memory address is sequentially specified in the column direction from the left column, and “A specification” indicates the mode in which the frame A of the transmission data signal 103 is written. Show,
“A read” indicates a mode for reading frame A. No.
As can be seen from FIG. 12, odd frames, ie, A, C, E,... Of the transmission data signal 103 are written to the memory 86, and even frames, ie, B, D, E,.
The transmission data signal 103 written in the memories 86 and 87 is always written sequentially from the first row of the memory cells in the row direction.
The data is sequentially read from the left column in the column direction. Also memory
86 and 87 are a selector control signal 104 and a selector control signal 109 having an inverted value of this signal. While the memory 86 is performing writing, the memory 87 transmits the transmission data signal written half a cycle before the selector control signal 109. The memory 86 performs an operation such as reading the transmission data signal 103 written half a period before the selector control signal 104 while the memory 87 is writing.

Next, the block diagram of the deinterleave circuit on the receiving side is shown in FIG.
Figure 13 shows. The components of the deinterleave circuit are exactly the same as those of the interleave circuit, but the connection of the address counter and the data selector is reversed. That is, the data selectors 104 and 105 select the transmission data signal 103 when the selector control signals 204 and 209 are “0”, and select the address counter 102 when the selector control signals 204 and 209 are “1”. Therefore, as can be seen from the time chart showing the operation of the deinterleave circuit shown in FIG.
Received data signals 203 written to 106 and 107 are always written sequentially from the left column in the column direction, and read is sequentially read from the first row in the row direction.

In FIG. 15, a transmission data signal 103 having a bit length of 4096 bits for one frame is stored in a memory 8 having a 64 × 64 memory cell array.
FIG. 16 shows the data matrix when data is written to 6,87, and the bit configuration of an arbitrary frame at the input / output terminals of the interleave circuit and the deinterleave circuit at that time. Here, the data values of the interleaved output signal 119 and the received data signal 203 in FIG. 16 have the same value unless there is a bit error in the transmission space. Now, assuming that a burst error has occurred in the transmission space and a 64 bit hatched portion of the received data signal 203 has caused a burst error, the received data signal 203 is rearranged by a deinterleave circuit and an error is output as a deinterleave output signal 221. It is sent to the correction circuit. At the time of this rearrangement, a burst error of 64 bits continuous is evenly distributed among 4096 bits as shown in FIG. 16, so that it can be equivalently regarded as a random error of 1 bit out of 64 bits. If this value is equal to or less than the number of correctable bits of the error correction circuit, the output data signal of the error correction circuit is transmitted to the terrestrial line as an error-corrected signal.

[Problems to be solved by the invention]

Consider a case where burst error correction in the case of a convolutional code is performed using the above-described conventional interleave circuit. Here, the bit length in the column direction read from the RAM by the interleave circuit or the bit length in the column direction written to the RAM by the deinterleave circuit is called an interleave order.

Now, assuming that a bit having twice the order of the interleave has caused a burst error in the transmission space, the burst error bits are equally distributed over one frame at the time of being rearranged by the deinterleave circuit, and equivalently 2 bits. A random error occurs with consecutive bits. When two consecutive bit errors occur, the convolutional coding method has a drawback that the error patterns cannot be corrected because the respective error patterns are duplicated.

[Means for solving the problem]

An interleave circuit according to the present invention includes a frame counter that inputs a transmission request signal and a transmission clock signal that become “1” and outputs a selector control signal only when a transmission data signal is input; A first address counter for inputting a clock signal to sequentially address a memory address in the row direction from the first row, and inputting the transmission request signal and the transmission clock signal to input an odd number of memory addresses every other column A second counter for sequentially addressing only the columns in the column direction, and a third counter for inputting the transmission request signal and the transmission clock signal and sequentially addressing the memory addresses every other column in the column direction only for the even columns.
An address counter, an output signal of the first, second, and third address counters and a selector control signal output from the frame counter are input, and the address of the memory is changed by the first, second, and third address counters. A first and a second data selector for selecting which output signal is to be used for addressing, the input of the transmission data signal, and the output signal of one of the first and second data selectors being input as an addressing signal, First and second memories for setting the mode of writing and reading by the selector control signal output from the frame counter and temporarily writing and reading the transmission data signal, and the first and second memories by the selector control signal output by the frame counter. Multiplexing a read data signal from the second memory and outputting it as an interleaved output signal Characterized by including and.

An interleave circuit according to the present invention comprises: a frame counter that inputs a transmission request signal and a transmission clock signal that become “1” only when a transmission data signal is input and outputs a selector control signal; A first address counter for sequentially inputting the address of the memory in the row direction from the first row by inputting a signal, and inputting the transmission request signal and the transmission clock signal so that the address of the memory is arranged at arbitrary plural columns. A plurality of fourth address counters for sequentially designating addresses in the column direction, an output signal of the first and a plurality of fourth address counters, and a selector control signal from the frame counter are inputted to change the address of the memory to the first address. 1. first and second data selectors for selecting which output signal of a plurality of fourth address counters is to be used for addressing; The first type the data signal, the second
One of the input signals of the data selector is input as an address designating signal, and the mode of writing and reading is set by the selector control signal output from the frame counter, and the first and second modes for temporarily writing and reading the transmission data signal are performed.
A second memory, and a selector for multiplexing the read data signals from the first and second memories based on a selector control signal output from the frame counter and outputting the multiplexed data signal as an interleaved output signal.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a frame format diagram showing the operation of the interleave circuit of FIG.

The frame counter 1 inputs the transmission request signal 101 and the transmission clock signal 102 which become “1” only when the transmission data signal 103 is input, and sends the data request to the data selectors 4 and 5, the memories 66 and 67 and the selector 89. It outputs selector control signals 104 and 105 as shown in FIG. The convolutionally encoded transmission data signal 103 is input to the memories 66 and 67. The address counters 82, 2, and 3 receive the transmission request signal 101 and the transmission clock signal 102, respectively.
67 addresses are sequentially counted up from the first row in the row direction, and a row direction row order address signal 112 for specifying an address is output. The address counter 2 sequentially counts up only the odd columns of the memory address in the column direction to address. The address counter 3 outputs an odd-column column-direction address signal 123 to be designated, and the address counter 3 sequentially counts up even-numbered columns of the memory address in the column direction and outputs an even-column-column address signal 124 to designate an address. Each of the data selectors 4 and 5 receives a row direction row order address signal 112, 123 and 124, and further has two systems of selector control signals 105 and 104 of the frame counter 1 or a selector control signal 109 obtained by inverting the selector control signal 104 by an inverter 88. In response to the control signal, data selector signals 115 and 116 shown in FIG. 2 are output to the memories 66 and 67, respectively. The memories 66 and 67 show the transmission data signal 103 inputted by the data selector signals 115 and 116 and the write / read (R / W) control by the frame counter 1 and the selector control signals 104 and 109 by the inverter 88, respectively, as shown in FIG. In such a procedure, a cycle of writing data in the row direction sequentially from the first row, reading data in the odd columns in the column direction, and subsequently reading data from the even columns in the row direction is performed. The selector 89 is a selector control signal 104 by the frame counter 1 and the inverter 88,
109, the read data signals 117, 11 from the memories 66, 67
8 are multiplexed and an interleaved output signal 119 is output to the outside.

That is, as the operation of the entire interleave circuit, the second
In the figure, the frames A, B, C, and D of the transmission data signal 103 are rearranged in the interleaved output signal 119 by serial / parallel conversion by writing / reading in the memories 66 and 67, and A odd (= in odd columns) Rows of the written signal frame A → column conversion signal), A even (= rows of the signal frame A written to the even column → column conversion signal), and so on. C-odd and D-even are output in this order, and the frame format is such that odd-bit data and even-bit data are alternately repeated.

Next, a deinterleave circuit used in combination with the interleave circuit of FIG. 1 will be described with reference to the block diagram of FIG. 3 and the frame format diagram of FIG.

The components of the deinterleave circuit of FIG. 3 are the same as those of the interleave circuit of FIG. 1, but the counting operations in the address counters 102, 7, and 8 are different as follows. As shown in FIG.
2 sequentially counts up from the first row of the addresses of the memories 306 and 307 in the column direction and outputs a column direction column order address signal 210 for specifying the address. The address counter 7 sequentially counts up only the odd columns of the memory address in the row direction. The address counter 8 outputs an even-numbered row-direction address signal 222 of the memory address. Due to the above difference, in the deinterleave circuit, as shown in FIG.
The frames of the received data signal 203 corresponding to the interleaved output signal 119 shown in FIG.
Means that in the memories 306 and 307, the frame A odd data signal is written into the memory 306 in odd columns in the row direction, and then the frame A even is written in the even columns in the row direction.
Data is read in the column direction from the column in the column direction, and while the memory 306 is reading, the memory 307 similarly performs writing of frames B odd and B even, and so on. Is performed. Finally, a deinterleave signal 220 is obtained as a multiplexed output of the selector 89 in FIG. 3 as shown in FIG. 4, and the transmission data signal in FIG.
103 frames A, B, C and D are reproduced.

Here, regarding the effect of burst errors in the transmission space in data transmission using the interleave circuit of FIG. 1, the frame bit length of the interleave order 64 bits
An example of 4096 bits (64 bits × 64) will be described with reference to the data matrix of FIG. 5 and the frame bit configuration diagram of FIG. Writing and reading of data in the memories 66 and 67 of the interleave circuit of FIG. 1 are performed in accordance with the data matrix of FIG. 5A. As shown in FIG. 6, the transmission data signal 103 includes bits 1, 2, 3,. … 4096 is an interleave output signal according to the reading of the odd-numbered column of the memory → the reading of the even-numbered column.
Converted to 119. Writing and reading of data in the memories 306 and 307 of the deinterleave circuit of FIG. 3 used together with the interleave circuit of FIG. 1 are performed in accordance with the data matrix of FIG. 5B, and reception corresponding to the interleave output signal 119 shown in FIG. The data signal 203 is inversely transformed as a deinterleave signal 220 and the transmission data signal 103
, 4096 are reproduced. Now, as shown by hatching in FIG. 6, when it is assumed that a continuous burst error having a length of 128 bits, which is twice the interleave order, occurs in the transmission space. It can be seen that in one frame, no burst error bits are continuous two bits.

In the convolutional code method, an error correction circuit can correct an error that is not continuous by two bits. If the interleave circuit of the first embodiment of the present invention is used, the number of continuous bits of a burst error in the transmission space can be reduced by the interleave order. Up to two times can be tolerated.

On the other hand, in the conventional interleave circuit of FIG.
In the figure, a burst error in the received data signal 203 is represented by hatched bits 1, 65,.
Assuming that a burst error occurs up to bit 2,66 beyond 9,4033, in the deinterleaved output signal 221, bits 1,2 and bits 65,66 become errors of two consecutive bits, and the convolutional coding method Since the error correction circuit cannot correct the error, conventionally, a burst error can be tolerated only up to consecutive bits of the interleave order.

FIG. 7 is a block diagram of a second embodiment of the present invention, and FIG. 8 is a frame format diagram showing the operation of FIG.

In this embodiment, one additional address counter is added to the components of the interleave circuit of the first embodiment shown in FIG. 1. In the first embodiment, in the matrix conversion processing of the interleave circuit, the column address at the time of memory reading is read. While the designation is divided into two stages of odd columns and even columns, in the second embodiment, the column direction address designation at the time of memory reading is (3n-2).
Columns, (3n-1) columns, and 3n columns (n is a natural number 1, 2,...).

FIG. 9 is a block diagram of a deinterleave circuit combined with the interleave circuit of the embodiment shown in FIG. 7, and FIG. 10 shows a frame format thereof.

As described in the first embodiment, by combining the interleave circuit and the deinterleave circuit,
For a burst error in the transmission space, it is possible to correct continuous bit burst errors up to the bit length, which is an error correction circuit of the convolutional code method, by bit rearrangement processing of the data signal, but with an interleave circuit configuration of the same memory capacity In contrast to the first embodiment, continuous burst error correction can be performed up to a bit length twice as long as the interleave order, whereas in the second embodiment, a continuous burst error having a bit length three times the interleave order can be corrected. It has the advantage of being.

Similarly, an interleave circuit that increases the number of address counters of the interleave circuit to N and performs memory reading at N column intervals to enable error correction up to a continuous berth error having a bit length of N times the interleave order. Can be

〔The invention's effect〕

As described above, according to the present invention, the transmission data signal
When serial-to-parallel conversion is performed, the address specification at the time of RAM reading is specified by reading at intervals of one or more columns, so that a burst error having a bit length twice the interleave order occurs in the transmission space. Even in this case, the bit rearrangement operation does not result in an error of two consecutive bits, but is converted into a random error separated by one or more bits, so that an error correction circuit of the convolutional code format can correct the error. . This contributes to high reliability of transmission quality in a convolutional code type line.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a timing chart showing the operation of FIG. 1, FIG. 3 is a block diagram of a deinterleave circuit combined with the interleave circuit of FIG. FIG. 5 is a timing chart showing the operation of FIG. 3, FIG. 5 is a data matrix diagram of the memory in the interleave circuit of FIG. 1 and the memory in the deinterleave circuit of FIG. 3, and FIG. FIG. 3 is a diagram showing the bit configuration of a frame of a data signal, and FIG.
8 is a timing chart showing the operation of FIG. 7, FIG. 9 is a block diagram of a deinterleave circuit combined with the interleave circuit of FIG.
10 is a timing chart showing the operation of FIG. 9, FIG. 11 is a block diagram showing the configuration of the conventional example, FIG. 12 is a timing chart showing the operation of FIG. 11, and FIG. 13 is the interleave circuit of FIG. FIG. 14 is a timing chart showing the operation of FIG. 13, and FIG. 15 is a data matrix of the memory in the interleave circuit of FIG. 11 and the memory in the deinterleave circuit of FIG. FIG. 16 is a diagram showing the bit configuration of the frame of the data signal shown in FIG. 11 and FIG. 1,11: Frame counter, 2,3,82,12,13,14 ... Address counter 4,5,15,16 ... Data selector, 66,67,76,77 ... Memory, 89 ... Selector, 101 ... Transmission request Signal, 102: transmission clock signal, 103: transmission data signal, 104 to 107, 109, 204
... 207,209 ... selector control signal, 112,113,211 ... row direction row order address signal, 114,210,211 ... column direction column order address signal, 123 ... odd column direction address signal, 124 ... even column direction address signal, 221 ... odd column row direction address Signal, 222
... Even-column row direction address signal, 125 ... (3n-2) column-column address signal, 126 ... (3n-1) column-column address signal, 127 ... 3n column-column address signal, 222 ... Even-column row direction address 223 ... (3n-2) row direction address signals, 224 ... (3n-1) row direction address signals, 225 ... 3n row direction address signals, 115,116,213,214 ... data selector signals, 117,118,215-217 ... memory Output signal, 119: interleave output signal, 201: ACQ signal, 202: reception clock signal, 203: reception data signal, 220: deinterleave signal.

Claims (2)

(57) [Claims] 1. A frame counter for inputting a transmission request signal and a transmission clock signal which become "1" only when a transmission data signal is input and outputting a selector control signal; And a first address counter for sequentially addressing the address of the memory from the first row in the row direction from the first row, and the transmission request signal and the transmission clock signal to input the memory address every other column in the odd column direction. A second address counter for sequentially addressing only in the column direction, and a third address for inputting the transmission request signal and the transmission clock signal and sequentially addressing the memory address every other column in the column direction only in the even column direction. A counter, an output signal of the first, second, and third address counters and a selector control signal from the frame counter; The address of the memory first, second,
First and second data selectors for selecting which output signal of the third address counter to address, and inputting the transmission data signal and addressing either output signal of the first or second data selector First and second memories which are inputted as signals and perform writing and reading modes by a selector control signal from the frame counter and temporarily write and read the transmission data signal;
By a selector control signal from the frame counter,
A selector for multiplexing the read data signals from the first and second memories and outputting the multiplexed data signals as an interleave output signal. 2. A frame counter for inputting a transmission request signal and a transmission clock signal which become "1" only when a transmission data signal is input and outputting a selector control signal; And a first address counter for sequentially addressing the addresses of the memory from the first row in the row direction from the first row, and inputting the transmission request signal and the transmission clock signal so that the addresses of the memory are arranged in arbitrary plural columns in the column direction. And a plurality of fourth address counters for sequentially designating addresses, an output signal of the first and a plurality of fourth address counters, and a selector control signal from the frame counter, and input a memory address to the first, First and second data selectors for selecting which output signal of a plurality of fourth address counters to address, and inputting the transmission data signal The output signal of one of the first and second data selectors is input as an address designating signal, and the mode of writing and reading is set by the selector control signal from the frame counter to temporarily write and read the transmission data signal. A first memory, a second memory, and a selector for multiplexing read data signals from the first and second memories and outputting the multiplexed data signals as an interleave output signal according to a selector control signal from the frame counter. Interleave circuit.