JP2713177B2 - Structure of field effect type semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor memory device having a ferroelectric capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Semiconductor memory devices, particularly non-volatile memory devices using ferroelectrics, have been proposed. The information holding method can be broadly divided into two methods. One is a method of combining a switching element and a capacitance element serving as a signal path gate and holding information as charges on the capacitance element electrode (JP-A-63-201).
Another method is to use a ferroelectric for a gate insulating film of a field effect transistor and to control a threshold voltage based on the ferroelectricity (Japanese Patent Laid-Open No. 48-919).
No. 83, JP-A-50-15446, etc.). The present invention relates to the latter method.

FIG. 4 shows an example of a semiconductor memory device disclosed in Japanese Patent Application Laid-Open No. 48-91983. An element-isolated p-type semiconductor substrate 301 and an n-type conductive source / drain region 3 formed on the surface of the substrate.
04, a gate insulating film 306 of a ferroelectric film having spontaneous polarization characteristics, a gate electrode 307, and a source / drain electrode 308.

When a positive voltage is applied to the gate electrode 307 to such an extent that the ferroelectric is polarized, a channel is formed in the p-type semiconductor region 301 below the ferroelectric film, and then a voltage is applied to the gate electrode. When stopped, the channel remains in the formed state due to the polarization properties of the ferroelectric,
Alternatively, a low resistance state such as a weak inversion state is obtained. next,
Applying a negative voltage as much as possible to reverse the polarization closes the channel, and the channel remains closed when the voltage is turned off. Then, the threshold voltage becomes a positive value, and the transistor becomes an enhancement type transistor.

The source / drain diffusion layers of a field effect transistor having a ferroelectric gate insulating film as described above are described in the publication "Ferroel" by SY Wu.
ectics 1976, Vol. 11, pp. 37
9-383 ", is formed before the formation of the gate insulating film and the gate electrode. An oxide film is formed on the surface of the Si substrate as a mask for impurity diffusion to the source / drain, and lithography is performed. An impurity diffusion mask is formed by etching, an impurity is introduced into the surface of the Si substrate by thermal diffusion, and then the mask oxide film is removed to form a ferroelectric film.

On the other hand, when forming the source / drain of a field-effect transistor of a highly integrated semiconductor integrated circuit, after forming a gate, an ion implantation method is performed in a region where the source / drain is to be formed in a self-aligned manner. Techniques for doping impurities with the like are well known. According to this method,
As the element size decreases, it becomes easy to control the impurity distribution of the transistor, which becomes difficult only by lithography technology, and it is possible to avoid deterioration and asymmetry of characteristics due to gate displacement with respect to source / drain positions.

[0007]

In the former method of manufacturing a field-effect transistor using a ferroelectric as a gate insulating film, the source / drain regions are formed before the gate is formed. It is difficult to miniaturize. On the other hand, in the case of the latter manufacturing method in which the source / drain region is formed in a self-aligned manner by the ion implantation method after the formation of the ferroelectric film and the formation of the gate electrode,
It is necessary to perform a high-temperature heat treatment to make the impurities electrically active. In this case, the metal element constituting the ferroelectric diffuses into some of the semiconductor substrates due to the high-temperature heat treatment, thereby changing the transistor characteristics, deteriorating the film characteristics due to evaporation outside the film, and generating cracks due to thermal stress. Problems such as shape change occur.

An object of the present invention is to provide a field effect type semiconductor memory device in which a source / drain region is formed before a gate is formed, and a ferroelectric gate insulating film can be provided in a self-aligned manner with respect to the source / drain region. And a method for manufacturing the same.

Another object of the present invention is to activate the impurities in the source / drain regions of a field effect type semiconductor memory device using a ferroelectric as a gate insulating film, secure the quality of the ferroelectric film, and prevent deterioration of transistor characteristics. An object of the present invention is to provide a field effect type semiconductor memory device and a method of manufacturing the same.

Still another object of the present invention is to provide a field effect type semiconductor memory device capable of realizing a nonvolatile memory integrated circuit using a highly integrated ferroelectric material whose element size is miniaturized and its manufacture. It is to provide a method.

[0011]

According to the present invention, a source region and
In a field- effect type semiconductor memory device having a gate electrode connected to a semiconductor via a ferroelectric film disposed between the drain region and the semiconductor device, the surface of the ferroelectric film is located at the position of the surface of the source / drain region. Approximately the same, and the interface between the ferroelectric film and the semiconductor is a source / drain region.
It is characterized by being located below the surface .

In manufacturing the field effect type semiconductor memory device, a groove region where the ferroelectric film is located is formed.
After the step of forming, the sources separated by the trench regions
Forming the ferroelectric film after forming the source / drain region
Performing

[0013]

The position of the interface between the ferroelectric of the gate insulating film and the semiconductor in contact with the semiconductor or in contact with the other via another dielectric is
Since it is located below the surface of the source / drain region, it is possible to form the source / drain region before forming the gate and to provide a ferroelectric gate insulating film in self-alignment with the source / drain region. Become.

Further, since the source / drain regions are formed before the gate is formed, it is possible to activate impurities in the source / drain regions, secure the quality of the ferroelectric film, and prevent deterioration of transistor characteristics.

[0015]

FIG. 1 is a sectional view of a field effect transistor which is an embodiment of a field effect type semiconductor memory device according to the present invention. This field-effect transistor is a p-type semiconductor substrate 10
1, a source / drain region 104, a low dielectric constant insulating film 105, a ferroelectric material 106 serving as a gate insulating film, a gate electrode 107, and a source / drain electrode 108. Low-k insulating film 1 underneath
05 and the p-type semiconductor are in the source / drain region 1
04 is located below the upper surface. Low dielectric constant insulating film 1
05 is a bias between the source and the drain,
This is for weakening the lateral electric field applied to 6.

A first embodiment of the method for manufacturing the field effect transistor will be described with reference to FIG.

First, as shown in FIG. 2A, a groove 102 is formed on a p-type semiconductor substrate 101 by lithography and etching.
To form

Next, as shown in FIG.
Is buried with a Si oxide film 103. Next, the semiconductor substrate 10
1 is ion-implanted with an impurity (n-type dopant) to make it the opposite conductivity type, followed by performing a high-temperature heat treatment to electrically activate the impurities and to form the source / drain region 10.
4 is assumed.

Next, as shown in FIG.
After the Si oxide film 103 embedded in the silicon oxide film 103 is selectively removed to form a groove, a Si oxide film 105 as a low dielectric constant insulating film is formed on the entire surface.

Next, as shown in FIG. 2D, Bi ₄ Ti ₃ O ₁₂ as a ferroelectric material 106 is sputter-deposited in the groove and etched back to be embedded.

Next, as shown in FIG. 2E, Pt is formed and processed as a gate electrode 107 on the ferroelectric 106. As a method of embedding the ferroelectric substance 106 in the groove, it is also possible to perform mechanical polishing, chemical polishing or mechanical chemical polishing after forming the ferroelectric substance.

Finally, as shown in FIG. 2F, metal source / drain electrodes 108 are wired to complete the process.

As described above, the low dielectric constant layer 105 is for weakening the lateral electric field applied to the ferroelectric by the bias between the source and the drain. Therefore, it is possible to use a Si oxide film as a Si nitride film or a material such as Ta ₂ O ₅ having a lower dielectric constant than a ferroelectric.

Although Bi ₄ Ti ₃ O ₁₂ is used as the ferroelectric, PZT, PLAZT, BiSr ₂ Ta ₂ O ₉ or the like may be used.

Although Pt is used as the gate electrode material, other metal materials such as Ru and Au can be used.

While the embodiment of the field effect type semiconductor memory device of the present invention has been described above, the following structure can be adopted.

For example, a structure may be employed in which after forming a low dielectric constant film, only the bottom of the groove is removed by anisotropic etching, so that a low dielectric constant insulating film is disposed on the side wall of the groove. At that time, another dielectric film can be arranged at the interface of the semiconductor substrate under the ferroelectric film.

It is also possible to adopt a structure in which a low dielectric constant film is not provided at the interface between the ferroelectric and the semiconductor.

Pt is formed not only on the gate insulating film but also on the source and drain, and silicide with Si of the source and drain is formed by appropriate heat treatment without reacting with the ferroelectric. It is also possible to reduce the source / drain parasitic resistance.

In the embodiment shown in FIG. 2, the groove 102 is formed in the p-type semiconductor substrate by lithography and etching.
As shown in FIG. 3A, S on the p-type semiconductor substrate 201.
i, a polycrystalline or single crystal semiconductor film 211 is formed, and then, as shown in FIG.
2 can also be formed. Thereafter, a field-effect type semiconductor memory device can be manufactured in the same manner as in the process of FIG.

In the manufacturing method described with reference to FIGS. 1 and 2, as a source / drain formation method, a semiconductor substrate or a Si film formed on a semiconductor substrate is doped with impurities by ion implantation or thermal diffusion. Then, a method of forming a groove and separating the source and the drain is also possible.

The field-effect semiconductor memory device of this embodiment can be an n-type semiconductor substrate provided with p-type sources and drains.

[0033]

According to the present invention, since the gate insulating film is disposed in a self-aligned manner with respect to the source / drain regions, even if a large number of elements are formed on the semiconductor substrate, the characteristics of the elements vary. Was few. Also, since no heat is applied to the ferroelectric film, no structural deformation such as cracks is observed in the ferroelectric film even after the process is completed. No element diffusion was observed, and the leakage current did not increase.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a field-effect transistor that is an example of a field-effect semiconductor memory device according to the present invention.

FIG. 2 is a diagram illustrating a method of manufacturing the field-effect transistor of FIG.

FIG. 3 is a diagram showing another method of manufacturing the field-effect transistor of FIG.

FIG. 4 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 101,201 p-type semiconductor substrate 211 single-crystal or polycrystalline semiconductor film 102 groove for burying ferroelectric substance 103 Si oxide film 104,304 source / drain region 105 low dielectric constant insulating film 106,306 Bi ₄ Ti ₃ O ₁₂ ferroelectric Body 107,307 Gate electrode 108,308 Source / drain electrode

Claims (4)

(57) [Claims] An arrangement is provided between a source region and a drain region.
In the field effect type semiconductor memory device having a ferroelectric film gate electrode connected to the semiconductor through which are, substantially the same as the position of the ferroelectric film surface surface of the source and drain regions of, and the A field effect type semiconductor memory device wherein an interface between a ferroelectric film and the semiconductor is located below a surface of a source / drain region. 2. The method of manufacturing a field- effect semiconductor memory device according to claim 1, wherein after the step of forming a groove region in which the ferroelectric film is located, a source / drain region separated by the groove region. method for producing a field effect semiconductor memory device which is characterized in that the formation of the ferroelectric film after forming the. A step of preparing a semiconductor substrate; a step of forming a groove in the semiconductor substrate; a step of burying the groove with a Si oxide film; and implanting an impurity into the semiconductor to activate the impurity. Performing a high-temperature heat treatment to form a source / drain region; removing the Si oxide film; embedding a ferroelectric in a groove after the removal; and forming a gate electrode on the ferroelectric, Forming a source / drain electrode on the source / drain region. A method for manufacturing a field effect type semiconductor memory device, comprising: 4. A step of preparing a semiconductor substrate; a step of forming a polycrystalline or single crystal semiconductor film of Si on the semiconductor; a step of forming a groove in the semiconductor film; Burying; implanting impurities into the semiconductor; performing high-temperature heat treatment to activate the impurities to form source / drain regions; removing the Si oxide film; Embedding a ferroelectric material; and forming a gate electrode on the ferroelectric material and a source / drain electrode on the source / drain region. Method.