JP2707663B2 - Message transfer check method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION (Industrial Application Field) The present invention relates to a multi-processor comprising a plurality of boards having a bus interface capable of transmitting and receiving a message transfer and a plurality of boards having no bus interface. Regarding the function check method of message transfer in the message processor system, in particular, to improve the reliability of the bus interface in a system that requires data transfer such as an execution program by message transfer from the master board to the slave board after powering on the device. The present invention relates to a message transfer check method in a multiprocessing system to be inspected.

(Prior Art) Conventionally, a message transfer in a multiprocessor system is performed by a processor in a board having a bus interface that enables the message transfer, by controlling a bus interface that transfers the message and transmitting the message. The transmission / reception program and transfer data are held in a board that performs transmission / reception of a message transfer by performing a loopback, and a data transmission / reception opposition test is performed between any two boards in a multiprocessor system. There is a method of confirming that predetermined transfer data is transmitted and received correctly.

(Problems to be Solved by the Invention) However, in such a method for checking transmission / reception of message transfer in a multiprocessor system, since it is not a check via a system bus, bus arbitration, a function for requesting message transfer, etc. In some cases, there is a check for a function that directly accesses the system bus, and it is not possible to check for a bus failure during message transfer. Also, in the facing test between any two boards in a multi-processor system, if a transmission / reception test is performed on all boards having message functions, the processing becomes complicated and a long processing time is required. There is. Furthermore, it is not possible to determine whether there is a board in the system that cannot transfer messages, and it is not possible to check it.

An object of the present invention is to provide a message transfer check method in a multiprocessor system which has solved the above-mentioned problems.

(Means for Solving the Problems) In order to achieve the above object, a message transfer check method according to the present invention includes a bus interface that enables message transfer via a system bus, and a processor that controls the bus interface. In a multiprocessor system including a plurality of first boards capable of transferring a message and a plurality of second boards unable to transfer a message, a bus interface is controlled as the first board by controlling a bus interface. Master board for transmitting and receiving data, a slave board for controlling the bus interface and transmitting and receiving messages, a bus service board having a function of monitoring and controlling the system bus and a bus timeout function, and a message transferred via the system bus To A bus test service board having a control function for performing a test transfer, wherein the bus service board sends a message transfer check packet to a board having a higher priority, and when transferring the message transfer check packet, the bus test service board An error is generated to check the transfer of the message transfer check packet, the result is returned, and thereafter, the message transfer is sequentially performed between the board with the highest priority and the board with the next highest priority, and A check similar to the transfer check is sequentially performed, and when a message transfer check packet is sent to the second board that cannot transfer the message, a timeout of the message return is monitored.

(Example) Hereinafter, the present invention will be described in more detail with reference to the drawings.

FIG. 1 is a basic circuit configuration diagram showing an embodiment of a message transfer check system according to the present invention.

After the power is turned on, the bus service board 1 performs a bus reset operation. The bus service board 1 sends an ID indicating the arbitration right of the system bus and an ID indicating the position of the board on the system bus to each board connected to the system bus 7 during the reset operation period. However, this transmission is not performed by message transfer, but is performed by other means. For example, it is set directly by an ID transmission signal line. Here, the arbitration priority in the system is highest for the bus service board 1 and lowest for the bus test service board 6. Therefore, the master board 2, the slave boards 3, 5 and the non-message transfer board 4
Has a higher arbitration right than the bus test service board 6 and a lower arbitration right than the bus service board 1. A processor is mounted on the master board 1 and the slave boards 3 and 5 that support message transfer, and a program that supports message transmission and reception by the processor and message retransmission and error processing when a bus transfer error occurs. It has a program to support etc.

Further, since the non-message transfer board 4 does not have a processor that supports message transfer, the non-message transfer board 4 does not have the above-mentioned program and does not have a message transfer function.
However, the ID indicating the arbitration right and the ID indicating the position of the board in the system are received.

After the arbitration right is sent from the bus service board 1 to each board, the master board 2 transfers a message to the system bus 7. Here, the format of the message to be transferred is not a message format sent by a normal bus transfer but a message packet having a packet ID called a message transfer check.

FIG. 2 is an example of a message format for basket used in the present invention. 2 (a) is a basic packet of the message format, FIG. 2 (b) is an example of a message transfer check packet transmitted first from the bus service board 1, and FIG. 2 (c) is a message on the master board 2. FIG. 2 (d) shows an example of a message transfer check packet indicating that the transfer has been normally completed. FIG. 2 (d) shows a packet transmitted to a non-message transfer board and then transmitted to the next board. FIG. 2 (e) shows an example of a message transfer packet returned from the bus test service board 6 to the bus service board 1 in the circuit configuration of the specific example shown in FIG.

The check of the message transfer is performed by sequentially performing the message transfer from the master board having the higher bus priority to the slave board having the lower priority. First,
The master board 2 issues a command for executing a message transfer check to the bus service board 1 having the highest bus priority. Therefore, in the example shown in FIG. 1, message transfer is first performed between the bus service board 1 and the master board 2.

The bus service board 1 sends the packet shown in FIG. 2B to the master board 2 at the start of the message transfer check. The master board 2 receives the packet sent from the bus service board 1. At this time,
The bus test service board 6 is a bus service board 1
Detects that the packet is a message transfer check packet to the master board 2, a bus error is intentionally generated for the bus. The bus error includes, for example, a data or address bus parity error.

When a bus error occurs, the bus service board 1 performs a message retransmission procedure, and retransmits a packet to the master board 2. However, at the time of packet retransmission, the bus test service board 6 does not generate a bus error even if it detects that it is a message transfer check packet from the bus service board 1 to the master board 2. Accordingly, the master board 2 which has received the message transfer packet from the bus service board 1 adds data indicating that the packet has been successfully received to the message transfer packet. FIG. 2 (c) shows a packet to which the message transfer check received by the mat board 2 has been added normally.

Subsequently, the message transfer is similarly performed between the master board 2 and the slave board 3, and the message transfer is sequentially performed from the board having the higher bus priority to the board having the lower bus priority. The message transfer packet transmitted from the master board 2 to the slave board 3 is shown in FIG.
Is a packet obtained by adding a slave board ID to the message transfer packet shown in FIG.

The message transfer is continued from the board with the higher bus priority to the board with the lower bus priority, but if the message transfer is performed to the non-message transfer board 4 which does not support the message transfer, the message transfer stops here. . Therefore, the bus service board 1
Always monitors whether the message transfer is completed within a certain period of time. By this function, the message transfer check packet is transmitted to the non-message transfer board 4, and the message transfer check is not aborted by the non-message transfer board 4.

Here, when the board that has transmitted the message transfer packet determines that transmission has been performed to the board that cannot perform the message transfer by the bus monitoring function of the bus service board 1, the board that transmits the message transfer check packet next. Perform the same message transfer operation. However, as shown in FIG. 2 (d), the packet transmitted here adds information indicating that a message transfer check packet has been transmitted to a board that cannot transmit and receive the message transfer.

Finally, data transfer is performed between the bus test service board 6 and the bus service board 1. When the last message transfer check is completed, the bus service board 1
Informs the master board 2 that the check has been completed. The master board 2 determines the reception packet of the bus service board 1 and confirms that there is no abnormality in the message transfer circuit system in the message transfer.

By the above operation, the master board 2 and the slave board 3
Check of the packet transfer (normal processing, abnormal processing) during the period becomes possible.

(Effects of the Invention) As described above, the message transfer check method according to the present invention performs a message transfer check including an abnormal processing system in the bus transfer by newly adding a bus test service board to the bus. Can be.
Furthermore, since message transfer is sequentially performed between boards having a message transfer function, it is possible to diagnose the message transfer circuit system in the system without the master board intervening in each process. And the time required for diagnosis can be shortened. Further, even if a board that cannot transmit and receive message transfer is connected to the bus, the mounting position of the non-message transfer board can be determined, and the message transfer function can be checked between boards excluding the board.

Therefore, a device such as a workstation, which needs to detect a failure of the message transfer function using the system bus as an initial diagnosis process after turning on the device and needs to execute the failure detection process in a short time. It is suitable for.

[Brief description of the drawings]

FIG. 1 is a basic circuit configuration diagram showing an embodiment of a message transfer check system according to the present invention, and FIG. 2 is a diagram showing an example of a message format for a bus check used in the present invention. An example of a basic packet of the message format, (b) is an example of a message transfer check packet transmitted first from the bus service board,
(C) is an example of a message transfer check packet indicating that the message transfer has been completed normally on the master board, and (d) is a message transfer to a non-message transfer board, followed by transmission to the next board. (E) shows an example of a message transfer packet returned to the bus service from the bus test service board in the circuit configuration of the specific example shown in FIG. 1 Bus service board 2 Master board 3 5 Slave board 4 Non-message transfer board 6 Bus test service board 7 System bus

Claims (1)

(57) [Claims] The present invention has a bus interface for enabling message transfer via a system bus, a processor for controlling the bus interface, and a plurality of first boards for enabling message transfer. In a multiprocessor system comprising a plurality of second boards that cannot be used, a master board that controls a bus interface to transmit and receive a message and a slave board that controls a bus interface to transmit and receive a message as the first board A bus service board having a function of monitoring and controlling a system bus and a bus timeout function, and a bus test service board having a control function of testing a message transferred through the system bus. Basser The board sends a message transfer check packet to a board with a higher priority, and when transferring the message transfer check packet, causes an error in the bus test service board to check the transfer of the message transfer check packet and returns the result. Hereinafter, the message transfer is sequentially performed between the board with the highest priority and the board with the next highest priority, and the same check as the message transfer check is sequentially performed. A message transfer check method in a microprocessor, wherein when a message transfer check packet is sent to a board, a timeout of message return is monitored.