JP2705415B2 - A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is used for an A / D converter (analog-to-digital converter). The present invention relates to an N (N is a natural number) input A / D converter having a sample-and-hold circuit that can reduce the probability that an error becomes large.

[0002]

2. _Description of the _Related Art A conventional sample-hold circuit of a d-bit N-input A / D converter (d and N are natural numbers) of a full-scale voltage V _REF has been configured as shown in FIG.

To sample the L-th voltage source (L) (1.ltoreq.L.ltoreq.N), an L-th analog switch (L)
Is closed, all the remaining analog switches are opened, and the A / D conversion circuit 18 is initialized. The sampling capacitor C is charged to the potential E _L through the output resistance r _L of the voltage source (L). After the elapse of the sampling time t seconds, the analog switch (L) is opened to start A / D conversion.

Therefore, after sampling the L-th voltage source (L), the M-th voltage source (M) (1 ≦ M ≦ N,
When sampling the potential E _M of L = M), the sampling capacitor C has already been charged to the potential E _L , so that the voltage E _C across the sampling capacitor C after the elapse of the sampling time t seconds from the start of sampling becomes M th E than the output resistance r _M of the voltage source _{(M) C = (E M} -E L) (1-EXP (-t / (r M C))) + E L ... formula next, M-th voltage source of the error [delta] with respect to the potential _{E M δ = | E M -E} L | EXP (-t / (r M C)) ... a formula. From 0 ≦ E _M and E _L ≦ V _REF , the maximum value of the error δ is V _REF EXP (−t / (r _M C)).

From the equation, when the output resistance r _{M of the} Mth voltage source (M) is large and | E _M −E _L | is large, δ> V
_REF / 2 ^d becomes, 1LSB more error occurs in the A / D conversion value.

On the other hand, when the output resistance r _M of the M-th voltage source (M) is small, an overcurrent proportional to | E _M −E _L | flows into the sampling capacitor C, thereby damaging the circuit. become.

[0007] Japanese Patent Laid-Open Publication No.
-92023. This is shown in FIG.
When sampling the voltage source (L), before closing the analog switch (L) 14, the analog switch (N)
+3) Close 29 to precharge the sampling capacitor C to a voltage V _REF / 2 which is half the full scale voltage V _REF . Thus, L th when sampling M-th voltage source (M) After sampling the voltage source (L), L-th voltage source (L) of the voltage across the sampling capacitor C irrespective of the potential E _M E _C is V _REF / 2
Therefore, the error δ is expressed as follows: δ = | E _M −V _REF / 2 | EXP (−t / (r _M C)) From 0 ≦ E _M ≦ V _REF , the maximum value of the error δ is V _REF
EXP (−t / (r _M C)) / 2, which makes it possible to increase the maximum value of the error by 0.50 times as compared with the simplest case shown in FIG. 3 and to suppress occurrence of overcurrent. Can be reduced.

[0008]

The conventional Japanese Patent Application Laid-Open No.
In the A / D converter disclosed in Japanese Unexamined Patent Application Publication No. 92023, the sampling capacitor C is precharged to V _REF / 2 before starting the next sampling regardless of the value sampled last time. | E
There are many combinations where _M− V _REF / 2 |> | E _M −E _L |, and there is a problem that the probability that the error becomes larger than in the simplest case shown in FIG. 3 is increased.

An object of the present invention is to solve such a problem, and an object of the present invention is to provide an A / D converter capable of greatly reducing the probability that an error will increase.

[0010]

Means for Solving the Problems The present invention includes an A / D converter circuit for converting the analog voltage from the input analog voltage source digital signal is sent to the output terminal, connected to the input of the A / D converter circuit A / D comprising: a sampling capacitor that has been connected; and means for precharging the sampling capacitor prior to connecting the input analog voltage source.
In the converter, means for the _{precharging, 0 ≦ E C ≦ a ·} V REF value E _C obtained by the sampling with respect to the full scale voltage V _REF, or (1-a), · V
_REF ≦ E _C ≦ V _REF, provided that a is a comparator means for comparing whether the range of the coefficient is 0 ≦ a ≦ 1/2, before performing the sampling of the following values, the last sampled value E
_{When C} is 0 ≦ E _C ≦ a · V _REF , the sampling capacitor is precharged with the voltage of a · V _REF , and the previously sampled value E _c becomes (1−a) · V _REF ≦ E _C ≦ V
_{When REF,} the sampling capacitor is (1-a)
Means for precharging V _REF .

It is preferable that the coefficient is a = 1 / √6 = 0.4082.

[0012]

[Operation] The value E _C sampled last time is 0 ≦ E _C ≦ a ·
For V _REF precharging a · V _REF in the sampling capacitor, the value E _C is the previously sampled (1-
a) When V _REF ≤ E _C ≤ V _{REF When} (1-a) V _REF is precharged to the sampling capacitor, the expected value f (a) of the maximum error value is expressed by the following equation.

F (a) = (a ² · a · V _REF + a · (1-2a) ² · V _REF + a ² · (1−a) · V _REF ) × 2 + (1-2a) · a · ( 1−a) · V _REF × 2 + (1-2a) ³ · V _REF = (4a ³ −2a + 1) · V _REF where a = 0.5, when a = 0.5, the aforementioned JP-A-2-9202
3 becomes equivalent to the A / D converter disclosed in
f (0.5) = 0.5V _REF .

In the simplest case shown in FIG. 3, a = 0.
And f (0) = V _REF .

The value of a that minimizes f (a) is f '(a)
= 12 (a ² −1 / √6) = 0, a = 1 / √6 =
0.4082. At this time, f (a) is f (1
/√6)=0.456 V _REF , and the probability of occurrence of an error can be significantly improved as compared with f (0.5) or f (0), that is, the simplest case shown in FIG.

[0016]

Next, an embodiment of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

In the first embodiment of the present invention, A / D conversion for converting analog voltages from the input analog voltage sources (1), (L), (M), and (N) into digital signals and sending the digital signals to the output terminal 19, respectively. Prior to connecting the circuit 18, the sampling capacitor C connected to the input of the A / D conversion circuit 18, and the input analog voltage sources (1), (L), (M), (N), and means for precharging C, further, as a feature of the present invention, the precharge _{means, 0 ≦ E C ≦ a ·} V REF value E _C the previously sampled for a full-scale voltage V _REF,
Or _{(1-a) · V REF} ≦ E C ≦ V REF ( provided that a is 0 ≦ a ≦ 1/2 a is the coefficient) the first analog voltage comparator 25 and which compares whether the range of the Before the second analog voltage comparator 26 and the control circuit 20 perform sampling of the next value, the previously sampled value E _C is 0 ≦
When E _C ≦ a · V _REF a
· A voltage of V _REF to precharge, the value E _C the previously sampled _{(1-a) · V REF} ≦ E C ≦ V (1-a) in the sampling capacitor C when the _{REF-V REF} to precharge to means And

Channel (1) to channel (N) not shown
Respectively have the potentials E ₁ , E _L , E _M , E _N and the output resistance r
_{A first} voltage source (1) having ₁ , r _L , r _M , r _N ,
The L-th voltage source (L), the M-th voltage source (M), and the N-th voltage source (N) are connected. Channels (1) to (N) are analog switches 13, 14, 15, 16
Through the sampling capacitor C.

The voltage E across the sampling capacitor C
_C is input to an A / D conversion circuit 18, converted into a digital value, and output from an output terminal 19. Further, the sampling capacitor C is connected to 1 / √6 times the full scale voltage V _REF through the analog switch 23 and the resistor r _{N + 1} , and the sampling capacitor C is connected to the analog switch 24 and the resistor r _{N + 2} of the full scale voltage V _REF ( 1-1 / √6) times.

The first analog voltage comparator 25 receives (1-1 / √6) of the full scale voltage V _REF and the voltage E _C across the sampling capacitor C, and outputs the comparison result to the control circuit 20. You. Second analog voltage comparator 2
6 receives 1 / √6 of the full-scale voltage V _REF and the voltage E _C across the sampling capacitor C, and outputs the comparison result to the control circuit 20. Each analog switch 1
3, 14, 15, 16, 23, and 24 are controlled by the control circuit 20.

Next, the operation of the first embodiment of the present invention will be described.

The control circuit 20 includes voltage sources (1), (L),
Before closing any of the corresponding analog switches 13, 14, 15, 16 to sample any of (M) and (N), based on the information input from the analog voltage comparators 25 and 26, Sampled value E _C
Analog switch 2 when 0 ≦ E _C ≦ V _REF / √6
3 to close precharged V _REF / √6 sampling capacitor C, the value E _C is the previously sampled (1-
1 / √6) · V _REF ≦ E _C ≦ V _REF When the analog switch 24 is closed, the sampling capacitor C
1 / √6) Precharge V _REF .

After the precharging of the sampling capacitor C is completed, the control circuit 20 opens the analog switch 23 or the analog switch 24, closes one of the analog switches 13, 14, 15, and 16, and sets the corresponding voltage source ( 1) Sampling of one of (L), (M) and (N) is started. After the elapse of the sampling time t, the closed analog switch is opened to instruct the A / D conversion circuit 18 to start conversion. When the A / D conversion is completed, the result of the A / D conversion is output from the output terminal 19.

In the first embodiment, in order to directly compare the voltage E _C across the sampling capacitor C, the analog voltage comparators 25 and 26 perform the comparison while the A / D conversion circuit 18 performs the A / D conversion. Therefore, the time required for precharge can be shortened, and it is possible to cope with the case where the conversion is initialized in the middle of one A / D conversion and another input is sampled.

(Second Embodiment) FIG. 2 is a block diagram showing a configuration of a second embodiment of the present invention.

In the second embodiment of the present invention, a digital comparator 27 is provided instead of the first analog voltage comparator 25 and the second analog voltage comparator 26 in the first embodiment.
Other configurations are the same as in the first embodiment.

Channel (1) to channel (N) not shown
Respectively have the potentials E ₁ , E _L , E _M , E _N and the output resistance r
_{A first} voltage source (1) having ₁ , r _L , r _M , r _N ,
The L-th voltage source (L), the M-th voltage source (M), and the N-th voltage source (N) are connected. Channels (1) to (N) are analog switches 13, 14, 15, 16
Through the sampling capacitor C.

The voltage E across the sampling capacitor C
_C is input to an A / D conversion circuit 18, converted into a digital value, and output from an output terminal 19. The sampling capacitor C is connected to 1 / √6 of the full-scale voltage V _REF through the analog switch 23 and the resistor r _{N + 1} ,
The analog switch 24 is connected to the full scale voltage V _REF (1-1 / √6) through the resistor r _{N + 2} .

The output of the A / D conversion circuit is input to the digital comparator 27, and the comparison result is output to the control circuit 20. Each analog switch 13, 14, 15, 16, 2
3 and 24 are controlled by the control circuit 20.

Next, the operation of the second embodiment of the present invention will be described.

The control circuit 20 includes voltage sources (1), (L),
Before closing any of the corresponding analog switches 13, 14, 15, 16 to sample any of (M) and (N), the previously sampled value based on information input from the digital comparator 27. E _C is 0 ≦ E _C
≦ For V _REF / √6 closes the analog switch 23 precharges V _REF / √6 sampling capacitor C, the last sampled value E _C is (1-1 / √6) ·
When V _REF ≦ E _C ≦ V _REF , the analog switch 24 is closed and the sampling capacitor C is set to (1-1 / √6).
The V _REF to precharge.

After the precharging of the sampling capacitor C is completed, the control circuit 20 opens the analog switch 23 or the analog switch 24, closes one of the analog switches 13, 14, 15, and 16, and sets the corresponding voltage source ( 1) Sampling of one of (L), (M) and (N) is started.

The control circuit 20 determines the sampling time t.
After elapse, open the closed analog switch and open A /
Instructs the D conversion circuit 18 to start conversion. When the A / D conversion is completed, the result of the A / D conversion is output from the output terminal 19.

In this embodiment, the sampling capacitor C
The voltage E _C across for not enter directly into the comparator, it is possible to hold the voltage across E _C of the leakage current without sampling capacitor C from the comparator with high accuracy.

As described above, by applying the first embodiment or the second embodiment of the present invention, the maximum expected value of the error is 45.6% of the simplest configuration shown in FIG. 91.2% of the configuration disclosed in Japanese Patent Application Laid-Open No. 2-92023 can be achieved, and the acquisition time during which the voltage E _C across the sampling capacitor is determined can be reduced to 78.5%. Becomes possible.

[0037]

As described above, according to the present invention, the expected value of the maximum value of the error is significantly reduced, and the voltage at both ends of the sampling capacitor is reduced when the simplest case of the error is about the same. The determined acquisition time can be reduced, and furthermore, the occurrence of overcurrent can be suppressed, and the damage to the circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional example.

FIG. 4 is a block diagram showing another configuration of the conventional example.

FIG. 5 is a diagram illustrating a combination of a full-scale voltage and a voltage source in a conventional example.

[Explanation of symbols]

 Reference Signs List 13 analog switch (1) 14 analog switch (L) 15 analog switch (M) 16 analog switch (N) 18 A / D conversion circuit 19 output terminal 20 control circuit 23 analog switch (N + 1) 24 analog switch (N + 2) 25th One analog voltage comparator 26 Second analog voltage comparator 27 Digital comparator 29 Analog switch (N + 3) C Sampling capacitor

Claims (2)

(57) [Claims] 1. An analog voltage from an input analog voltage source.
An A / D converter circuit for delivering the converted output to digital signals, and connected to the sampling capacitor to the input of the A / D converter, the sampling capacitor prior to coupling the input analog voltage source In the A / D converter provided with a means for precharging, the precharge means may be arranged such that the sampled value E _C is 0 ≦ E _C ≦ a · V _REF or (1-a) with respect to the full-scale voltage V _REF . _{) · V REF ≦ E C ≦} V REF provided that a is a comparator means for comparing whether the range is the coefficient of the 0 ≦ a ≦ 1/2, before performing the sampling of the following values, previous sampling the precharged voltage of a · V _REF in the sampling capacitor, the last sampled value E _C is _{(1-a) · V REF} ≦ E C ≦ when the value E _C given by a _{0 ≦ E C ≦ a · V} REF V _{When REF} , (1-a) · V
Means for precharging _REF . 2. The coefficient is a = 1 / √6 = 0.4082.
The A / D converter according to claim 1, wherein