JP2697714B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.
It relates to an address buffer circuit . 2 and 3 are diagrams showing an address buffer circuit of a conventional semiconductor memory device. In particular, FIG. 2 shows an X address buffer circuit, and FIG. 3 shows a Y address buffer circuit. . A conventional address buffer circuit will be described with reference to FIGS. An X address signal Aix to a Y address signal Aiy are applied to an X address input buffer circuit X1 to a Y address input buffer circuit Y1. The X address buffer circuit of FIG. 2 is configured to output a complementary signal pair of a signal Ax having the same phase as the X address signal Aix and a signal Ax # having the opposite phase by combining the X address input buffer circuit X1 and an inverter array. It is. Output signals Ax, Ax # of the X address buffer circuit are input to the row decoder, and control the rising and falling of the word line. The Y address buffer circuit of FIG. 3 has basically the same circuit configuration as the X address buffer circuit of FIG.
A signal having the same phase as iy and a signal having the opposite phase to the signal Ay are output. Output signals Ay, Ay # of the Y address buffer circuit are input to a column decoder, and control on / off of a column gate. The reason why the number of inverters forming the inverter row in the Y address buffer circuit in FIG. 3 is larger than that in the X address buffer circuit in FIG. 2 is to take the timing of rising of a word line and turning on a column gate. The outputs Ay, Ay # of the address buffer circuit are delayed as compared with the outputs Ax, Ax # of the X address buffer circuit. The X address input buffer circuit X1 and the Y address input buffer circuit Y1 are required to be able to convert a TTL input level signal into an internal signal without using a pull-up element. Therefore, the aspect ratio (W / L) of the Nch transistor constituting the input buffer circuit is
By making the aspect ratio (W / L) of the transistor higher, the logic level with respect to the input signal is designed to be close to 1.5V. FIGS. 4A and 4B show the above X
FIG. 5 is a diagram showing operation waveforms of the address buffer circuit,
(A), (b) is a figure which shows the operation waveform of the said Y address buffer circuit. The conventional address buffer circuit configured as described above has the following two problems. One is an Nch constituting an input buffer circuit.
Since the aspect ratio (W / L) of the transistor is larger than the aspect ratio (W / L) of the Pch transistor, the response of the input buffer circuit when the falling signal of the address signal is input is:
This means that the response is slower than the response when the rising signal of the address signal is input. Therefore, in the operation waveform of the X address buffer circuit shown in FIG. 4, the output Ax of the X address buffer circuit when the falling signal of the address signal is input.
And Ax # have High and High periods, and if the input of the next row decoder is High active,
There is a risk that two word lines are selected at the same time. The simultaneous active period can be solved by adjusting the aspect ratio (W / L) of the Pch transistor and the Nch transistor of the inverter constituting the X address buffer circuit. This is not a good idea when considering the variation in the aspect ratio (W / L). The second is the operation of the Y address buffer circuit, in which the output signal A of the Y address buffer circuit is related to the rise of the word line and the timing of turning on the column gate.
y, Ay} is delayed. The signal that changes from active to non-active output of the Y address buffer circuit that controls column gate off is also delayed,
That is, the timing of turning off the column gate is delayed. This delay in column gate off timing is caused by RA
When the address signal changes at the time of the change of the operation from the read-out of M to the write operation, the write enable signal (hereinafter abbreviated as WE #) high-to-low change time and the address signal of the write enable signal (hereinafter abbreviated as WE #) for not writing to the address before the address signal change Address change time tA, which is a margin for timing
s. Therefore, an object of the present invention is to provide an aspect ratio (W) of a transistor constituting an address buffer circuit during a simultaneous active period occurring at an output of the address buffer circuit.
/ L) not only by adjusting but also by changing the output signal of the Y-address buffer circuit from active to non-active, and the address set time tAs
An object of the present invention is to provide an address buffer circuit capable of improving characteristics. A semiconductor memory device according to the present invention is provided.
Inputs the address signal and outputs the internal X address signal
And an internal X address signal
An X decoder circuit for selecting a word line based on the
Y that inputs a dress signal and outputs an internal Y address signal
An address buffer circuit;
And a Y-decoder circuit for selecting a column gate.
The X decoder circuit and the Y decoder
Each of the decoder circuits inputs the address signal,
A delay circuit for outputting an in-phase delay signal of the address signal
And the same phase delay of the address signal and the address signal.
And the input signals are both at the first input level.
The internal X address signal of the first output level.
Signal or internal Y address signal, and
If at least one of them has the second input level, the second
Output level internal X address signal or internal Y address
A logic gate circuit for outputting a Y signal.
The delay circuit of the X-decoder circuit.
The delay amount is larger than that of the extension circuit. According to the address buffer circuit of the present invention, the signal which changes from non-active to active among the output signals of the address buffer circuit is compared with the signal which changes from active to non-active by the delay time of the delay circuit. Because of the slowness, the occurrence of the simultaneous active period in the output signal of the address buffer circuit can be broken in terms of circuit configuration, and the change from active to non-active is only the delay in the input buffer circuit and the NAND circuit. In addition, the delay of the column gate off timing can be solved. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail based on embodiments. FIG. 1 is a block diagram schematically showing an address buffer circuit according to the present invention. FIG. 6 is a diagram showing one embodiment of the X address buffer circuit of the present invention, and FIG. 7 is a diagram showing one embodiment of the Y address buffer circuit of the present invention. The X address buffer circuit shown in FIG. 6 includes a NOR 10 receiving an address signal Aix 'and an inverter 20,
An inverter 30, a circuit A1 for outputting an in-phase signal AX 'with the address signal Aix', and an address signal Aix '
And a circuit A2 that outputs a signal Ax′￣ having the opposite phase. The input of the row decoder connected to the next stage is H
It is assumed to be "active". When the address signal Aix 'rises, the output of the inverter 30 becomes Hi.
gh → Low, and receives this signal change.
The output of the signal 40 goes from low to high, and the output Ax′￣ is high.
It changes from high to Low. On the other hand, as for the output Ax ', the output of the impeller 20 changes from Low to High, and the signal after passing through the four stages of inverters 40 → Inverter 50 → Inverter 60 → Inverter 70 becomes Low →
When the signal changes to High, the output of NAND80 becomes High →
Since the output becomes low, the change in the output Ax # is delayed by the delay caused by the four stages of inverters. Also,
Similarly, when the address signal Aix ′ falls, similarly to the output Ax ′ which is transmitted through the path of NOR10 → inverter 20 → NAND80 → inverter 90 and changes from High → Low, the output Ax′￣ is the inverter 1
Low by the delay of four stages of 00 to inverter 1350
→ High, that is, non-active → active change is delayed. High of output Ax 'and output Ax'￣ →
The time difference between the Low change time and the Low change time can be arbitrarily set according to the number of stages of the inverters constituting the inverter array. Here, the circuit configuration of the delay circuit is limited to an inverter array, and may be a delay circuit using a CR. As described above, since the change from non-active to active is delayed by four inverters compared to the change from active to non-active, a simultaneous active period does not occur at the output of the address buffer circuit. Absent. Further, since the delay time is determined mainly by the number of stages of the inverters constituting the inverter row, the aspect ratio (W
/ L) is less affected. FIGS. 8A and 8B are diagrams showing operation waveforms of FIG. The configuration of the Y address buffer circuit of FIG. 7 is basically the same as the configuration of the X address buffer circuit of FIG. 6, and the X address buffer of FIG. This is different from the circuit. In the operation of the Y address buffer circuit, similarly to the operation of the X address buffer circuit, the change of the output of the Y address buffer circuit from non-active to active is inferior to that of the eight stages of inverter rows, whereas the change from active to
Change to non-active is NOR10 ', inverter 2
0, the delay in the NAND 80 and the inverter 90 ', or the NOR 10', the inverter 20 ', the inverter 30', the NAND 140 'and the inverter 15'
Only the delay at 0 'does not cause the delay at the time of active-to-non-active change, which is a conventional problem. For this reason, the timing of turning off the column gate can be advanced, and the characteristics of the address set time tAs during the write operation can be improved. FIGS. 9A and 9B are diagrams showing operation waveforms of FIG. As described above, according to the present invention , the column
It is impossible to solve the delay of the gate off timing.
Address characteristics can be improved.
You.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram schematically showing an address buffer circuit of the present invention. FIG. 2 is a circuit diagram showing a conventional X address buffer circuit. FIG. 3 is a circuit diagram showing a conventional Y address buffer circuit. FIGS. 4A and 4B are operation waveform diagrams for explaining the operation of FIG. 2; FIGS. 5A and 5B are operation waveform diagrams for explaining the operation of FIG. 3; FIG. 6 is a circuit diagram showing one embodiment of an X address buffer circuit of the present invention. FIG. 7 is a circuit diagram showing one embodiment of a Y address buffer circuit of the present invention. 8 (a) and (b) are operation waveform diagrams for explaining the operation of FIG. 6; FIGS. 9A and 9B are operation waveform diagrams for explaining the operation of FIG. 7;

Claims (1)

(57) [Claims] Input the address signal and output the internal X address signal.
And a word line based on the internal X address signal.
Inputs an X decoder circuit and an address signal, and outputs an internal Y address signal
Selects a column gate based on a Y address buffer circuit and the internal Y address signal
Semiconductor memory device having a Y decoder circuit
The X decoder circuit and the Y decoder circuit are respectively
The address signal is inputted, and the address signal is delayed in phase.
A delay circuit for outputting an extension signal, the address signal and an in-phase delay signal of the address signal.
And the input signals are both at the first input level
If there is, the internal X address signal of the first output level
Or output the internal Y address signal, and
A second output if at least one is at a second input level;
Level internal X address signal or internal Y address signal
A logic gate circuit for outputting a signal, and the delay circuit of the Y decoder circuit comprises:
The delay amount of the circuit is larger than that of the delay circuit.
Semiconductor storage device.