JP2692955B2 - Parallel A / D converter - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel A / D converter that converts an analog signal into a corresponding digital signal.

2. Description of the Related Art In recent years, digitization of electronic devices has progressed, and it has become necessary for A / D converters used in these devices to have higher accuracy and lower cost.

The configuration of the conventional parallel type A / D converter will be described below. FIG. 3 is a block diagram of a conventional parallel type A / D converter. In FIG. 3, reference numeral 1 is a signal input terminal for applying an analog signal, and 2 is a reference voltage generating means for giving a reference for comparison of the input signals. The output of the comparator array 3 is converted into a specific digital code by the encoder 5. 6-9
And 10 to 13 are comparators forming two comparator rows 3.

FIG. 4 is a circuit diagram showing in detail the comparators 9 and 10 of FIG. 3, in which 18 to 21 are transistors, 15 is the collector of the transistor, 16 is the base of the transistor, and 17 is the emitter of the transistor. .

The operation of the parallel A / D converter configured as above will be described below. The analog signal applied to the signal input terminal 1 is given to all the comparators 6 to 13, and this analog signal is compared with the reference voltage given from the reference voltage generating means 2 in each of the comparators 6 to 13 to obtain the comparator. The output of the comparator corresponding to the input level among 6 to 13 becomes active. The encoder 5 to which the output of the comparator array 3 is input outputs a digital code corresponding to the output of the activated comparator. With the above operation, a digital code corresponding to the input analog signal can be generated. Here, the encoder 5 needs to have the outputs of the two comparator rows 3 as inputs, and each of the comparators 6 to 13 needs to have the same characteristics. The comparators 6 to 9 and the comparators 10 to 13 are arranged in a point-symmetrical relationship, the bases 16 of the transistors 18 and 20 are connected to the reference voltage generating means 2, and the bases of the transistors 19 and 21. Is connected to the signal input terminal 1.

However, in the above-described conventional configuration, when a spatial gradient occurs in the base-emitter voltage of a plurality of transistors, for example, the base-emitter voltage V of the transistors 18 to 21 shown in FIG. _BE18, V _BE19, V _BE20, if V _BE21 becomes _{V BE18> V BE19> V BE21} > V BE20 the relationship, the sign of the input offset voltage of the comparator 10 and the input offset voltage of the comparator 9 is reversed However, there is a problem that the difference in the input offset voltage between the comparators causes a conversion error in the parallel A / D converter.

Further, in manufacturing, if the collector and the emitter of the transistor are misaligned, for example, if the collector 15 and the emitter 17 of the transistors 18 and 19 in FIG. There is a problem that a gap is generated between the emitter 17 and the emitter 15 in a direction away from each other, a mismatch occurs in the characteristics of the comparator 9 and the comparator 10, and a conversion error occurs.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a highly accurate parallel A / D converter that is less affected by transistor characteristic mismatches and pattern shifts that occur during manufacturing.

Means for Solving the Problems In order to solve the above problems, a parallel A / D converter according to the present invention includes first and second comparator rows each having a plurality of comparators, and the above first comparison. An encoder which is arranged between the comparator array and the second comparator example and which receives the output signals of the first and second comparator arrays as an input and outputs a digital code corresponding to the input signal; A first transistor having an input terminal connected to the signal input terminal, and a second transistor having the input terminal connected to the reference voltage generating means. The transistor constitutes a first comparator included in the first comparator array,
A second comparator included in the second comparator row is configured by a third transistor having an input terminal connected to the signal input terminal and a fourth transistor having an input terminal connected to the reference voltage generating means. However, the arrangement of the second transistor with respect to the first transistor and the arrangement of the fourth transistor with respect to the third transistor are in the same direction.

Operation With this configuration, it is possible to realize a highly accurate parallel A / D converter that is less affected by transistor characteristic mismatches and pattern shifts that occur during manufacturing.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a parallel type A / D converter according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing in detail 39 and 40 of FIG. In FIG. 1, 31 is a signal input terminal for applying an analog signal, 32 is a reference voltage generating means for giving a reference for comparison of input signals, and each input signal is compared with a reference voltage in a comparator row 33. The output of the comparator array 33 is converted into a specific digital code by the encoder 35. Reference numerals 36 to 39 and 40 to 43 are comparators forming two comparator rows 33.

In FIG. 2, 48 to 51 are transistors, 45 is a collector of the transistor, 46 is a base of the transistor, 17 is an emitter of the transistor, and the transistors 50 and 51 are opposite to the conventional transistors 20 and 21, The collector, base and emitter are arranged in the same direction.

The operation of the parallel type A / D converter of the present embodiment configured as described above will be described below. The analog signal applied to the signal input terminal 31 is given to all the comparators 36 to 43, and this analog signal is compared with the reference voltage given from the reference voltage generating means 32 in each of the comparators 36 to 43 to obtain the comparators. 36 ~
Of the 43, the output of the comparator corresponding to the input level becomes active. The encoder 35 to which the output of the comparator array 33 is input outputs a digital code corresponding to the output of the activated comparator. With the above operation, a digital code corresponding to the input analog signal can be generated. Here, since the encoder 35 needs to input the outputs of the two comparator rows 33, and the characteristics of the respective comparators 36 to 43 need to be completely equal, the comparators 36 to 43 are almost similar. Take shape,
The array of comparators 36-39 and the array of comparators 40-43 are arranged in an axially symmetric relationship, and the transistors 50, 51 of the comparator 40 corresponding to the transistors 48, 49 of the comparator 39 exchange connections. A transistor corresponding to the conventional transistor 21.
The base 46 of 50 is connected to the reference voltage generating means 32, and the base of the transistor 51 corresponding to the transistor 20 of the conventional example is connected to the signal input terminal 31.

As described above, according to the present embodiment, by arranging the comparators 39 and 40 arranged on both sides of the encoder 35 in an axially symmetric relationship, the collector, base, and emitter of the transistors 48, 49, 50, 51 are The arrangement order becomes the same, and for example, even if a pattern shift occurs in the direction in which the collectors and emitters of the transistors 48 and 49 come close to each other, the collector and emitter of the transistors 50 and 51 also come close to each other.
No mismatch of 8,49,50,51 characteristics occurs. In addition, by connecting the bases 46 of the transistors 50 to the reference voltage generating means 32 by exchanging the connections of the transistors 50 and 51 forming the comparator 40 and connecting the bases 46 of the transistors 51 to the signal input terminal 31, The transistors 48, 50 connected to the voltage generating means 32 and the transistors 49, 51 connected to the signal input terminal 32 are arranged in the same order, and for example, the base-emitter voltage V _BE48 , of the transistors 48, 49, 50, 51.
V _BE49, V _BE50, V _BE51 is _{V BE48> V BE49> V BE50} > input offset voltage of the comparator 39 and 40, even if it is a V _BE51 can be reduced.

EFFECTS OF THE INVENTION As described above, according to the present invention, the transistors connected to the signal input terminals and the reference voltage generating means that constitute the comparators of the first and second comparator rows arranged on both sides of the encoder are provided. The difference between the input offset voltages of the first and second comparators is made small by making the arrangement of the transistors connected to the same direction in both arrays, and the difference of the input offset voltage of all the comparators is made small. It is possible to realize an excellent parallel type A / D converter that can be suppressed and has high accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram of a parallel type A / D converter according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a part of FIG. 1 in detail, and FIG. 3 is a conventional parallel type A / D converter. FIG. 4 is a block diagram of the D converter, and FIG. 4 is a circuit diagram showing a part of FIG. 3 in detail. 31 …… Signal input terminal, 32 …… Reference voltage generating means, 33 ……
Comparator row, 35 ... Encoder, 36-43 ... Comparator, 45 ...
… Transistor collector, 46 …… Transistor base, 47 …… Transistor emitter, 48-51 …… Transistor.

Claims (1)

(57) [Claims] 1. A first and a second comparator row each having a plurality of comparators, and the first and second comparator rows arranged between the first and second comparator rows. An encoder for receiving an output signal of the comparator array and outputting a digital code corresponding to the output signal, and a reference voltage generating means arranged in a peripheral portion including the first and second comparator arrays, The first transistor included in the first comparator row is configured by the first transistor whose input terminal is connected to the signal input terminal and the second transistor whose input terminal is connected to the reference voltage generating means described below. A second comparator included in the second comparator array is formed by a third transistor having an input terminal connected to the signal input terminal and a fourth transistor having an input terminal connected to the reference voltage generating means. Configuring the first ton transistor to the first Sequence and said third transistor
A parallel type A / D converter characterized in that the arrangement of the fourth transistor is the same as that of the above transistor.