JP2692037B2 - Electrostatic induction transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static induction transistor (SIT) and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional SIT will be described with reference to FIG. According to the same figure (a), surface gate type SIT
Is an n ⁺ substrate 101 to be a drain region and an n epitaxial layer 10 to be a channel region provided thereon.
2 and the n ⁺ source region 103 and the p ⁺ gate region 104 provided on the surface of the n epitaxial layer 102. With such a surface gate structure, the high-frequency characteristics are improved because the gate resistance is reduced, and a prototype is manufactured up to about 1 GHz. Further, since the diffusion depth of the p ⁺ gate region 104 can be set to 2 to 3 μm or more, when the thickness of the n epitaxial layer 102 is 20 μm, it is 200 to 300 V.
In the same manner, a withstand voltage of 60 V can be obtained in the case of 6 μm.

Further, as a structure with further improved high frequency characteristics, a recess gate type SIT and a side gate type SIT shown in FIGS. 1B and 1C have been proposed.
In the recess gate type SIT, the n epitaxial layer 102
A groove portion 105 is provided in the p ⁺ gate region 106 at the bottom of the groove portion 105. In the side gate type SIT, n
P ⁺ gate regions 108 are formed at both corners of the groove 107 provided in the epitaxial layer 102. Those SITs are
Gate-source capacitance Cgs compared to surface gate type SIT
Also, since the gate-drain capacitance Cgd can be reduced, the power gain is improved to almost the upper limit of the UHF band. In the recess gate type SIT, for example, when the thickness of the n epitaxial layer 102 is about 6 to 10 μm, 1
The power gain at ˜3 GHz is 7 to 10 dB, and an element of several GHz is obtained as the maximum oscillation frequency fmax at which the gain is 1 (0 dB).

To improve high frequency characteristics, gate / source
It suffices to reduce the capacitance Cgs and the gate-drain capacitance Cgd. To reduce Cgd, the p ⁺ gate region 106
The diffusion depth Xj may be shallow. Also, since Cgd increases in inverse proportion to the distance between the gate and the drain, Cgd
The thickness of the n epitaxial layer 102 may be increased to reduce d. However, increasing the thickness of the n-epitaxial layer 102 lowers the gain due to the transit time effect caused by electrons traveling from the source to the drain.
There is a trade-off relationship with x.

In addition, the gate-drain breakdown voltage BVgd
May be increased Xj to enhance, but the game
The distance between the capital region and the drain region intends want to increase Cgd becomes shorter. That is , regarding the diffusion depth Xj of the p ⁺ gate region 106, BVgd and Cgd have a trade-off relationship. Thus, the high frequency characteristic and the breakdown voltage are related to each other. BVgd is pn between the gate and the drain
This is the reverse breakdown voltage of the junction, which determines the maximum voltage that can be applied to the drain (drain breakdown voltage).

By the way, the actual BVgd in the recess gate type SIT is smaller than the theoretical withstand voltage determined by the plane junction inside the element. Therefore, the pn junction of the gate and the drain was reversely biased, a voltage which became a breakdown voltage was applied, and the surface was examined by an infrared radiation microscope. Then
Since the temperature rises at the outermost peripheral portion of the p ⁺ + gate region 106, not at the flat junction portion (the portion where the theoretical breakdown voltage is secured) of the gate / drain, but at the spherical or cylindrical joint portion formed at the outermost peripheral portion. It was found that the breakdown voltage was reduced.

The output power in the SIT increases in proportion to the product of the drain voltage and the drain current.
In order to realize a high output device, the optimum design is to obtain the theoretical breakdown voltage determined by the thickness between the gate and drain without impairing the high frequency characteristics. However, the actual BVgd is lower than the theoretical withstand voltage, and high-frequency, high-power recess gate type S
In order to form IT, it is required to increase BVgd to the theoretical breakdown voltage. The same applies to the side gate type SIT as the recess gate type SIT.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-frequency / high-power recess gate type or side gate type S
It is to provide IT.

[0009]

Static induction transistor according to the present invention SUMMARY OF THE INVENTION comprises a n ⁺ drain region, and the n ⁺ drain region n-type channel region provided on a plurality of provided in the channel region n ⁺ source region, a plurality of groove parts provided in the channel region, a plurality of p ⁺ gate regions provided in the channel region from the bottom of each groove part or a part of the bottom part, and each p ⁺ gate region And a p ⁺ guard ring region disposed around the plurality of p ⁺ gate regions. The plurality of n ⁺ source regions and the plurality of p ⁺ gate regions are arranged in parallel to each other, and the p ⁺ gate regions are arranged on both outer sides. The width of the p ⁺ guard ring region is set to be a distance between the p ⁺ gate region and the n ⁺ drain region or slightly larger.

In the method of manufacturing an electrostatic induction transistor according to the present invention, a step of forming an n-type semiconductor layer serving as a channel region on an n ⁺ -type semiconductor substrate and a strip-shaped p ⁺ guard ring region in the semiconductor layer. A step of forming a plurality of grooves in the semiconductor layer so as to be parallel to the inside of the p ⁺ guard ring region, and a step of forming a plurality of grooves in the semiconductor layer so as to be connected to the p ⁺ guard ring region provided at the bottom of the groove. a plurality of p ⁺ gate region formed in the semiconductor layer, the p ⁺
Forming a plurality of n ⁺ source regions in the semiconductor layer inside the guard ring region and alternating with the plurality of p ⁺ gate regions.

[0011]

According to the static induction transistor, the p ⁺
By providing the p ⁺ guard ring region around the gate region, the depletion layer reaches the p ⁺ guard ring region or expands further. As a result, the gate-drain breakdown voltage BVgd is determined not at the end of the p ⁺ gate region, that is, at the flat junction rather than the spherical junction or the cylindrical junction, and can be greatly improved.

According to the manufacturing method, after forming the p ⁺ guard ring region, the can be formed inside the groove so as to include a portion of the p ⁺ guard ring region, whereby said p ⁺ The p ⁺ gate region can be formed to connect with the guard ring region.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 1A, the recess gate type SIT has a plurality of p ⁺ gate regions 16 (16a, 16a).
(including b), a plurality of n ⁺ source regions 18, and a strip-shaped p ⁺ guard ring region 13 (a part surrounded by a broken line) arranged so as to surround the p ⁺ gate region 16. The p ⁺ gate region 16 and the n ⁺ source region 18 are alternately arranged in parallel lines.

As shown in FIG. 1B, the p ⁺ gate region 16a provided on the outermost side is the p ⁺ guard ring region 1
The p ⁺ gate region 16b connected to the n ⁺ source region 18 is connected to the p ⁺ guard ring region 13 at its end. Further, the corner of the p ⁺ guard ring region 13 is formed in a round shape so as to alleviate the electric field concentration. Furthermore, in order to prevent the breakdown voltage BVgs between the gate and the source from decreasing, n
^{The +} source region 18 is preferably formed so that L2 ≧ Wgs. In the figure, L1 is the width of the p ⁺ guard ring region 13, L2 is the distance between the end of the n ⁺ source region 18 and the p ⁺ guard ring region 13, and Wgs is the n ⁺ source region 18.
And the p ⁺ gate region 16 are shown.

Further, a more detailed description will be given with reference to FIG. This figure is a cross-sectional view showing AA 'in FIG.
The recess gate type SIT includes an n ⁺ drain region (n ⁺ substrate) 11 and an n epitaxial layer 12 which is a high resistance channel region provided on the n ⁺ drain region 11.
And a groove portion 14a provided in the n epitaxial layer 12,
and b, the insulating film 15 on the n epitaxial layer 12, grooves 14a, ^p formed from the bottom of b in n epitaxial layer 12 ⁺ gate regions 16a, b and, in the n epitaxial layer 12 of ^{p +} gate region 16 a The p ⁺ guard ring region 13 provided so as to be connected in the outer peripheral portion and the n ⁺ source region 18 provided in the n epitaxial layer 12
And a gate electrode 19 and a source electrode 20 provided on the p ⁺ gate region 16 and the n ⁺ source region 18, respectively.
And a drain electrode 21 provided on the n ⁺ drain region 11. As the insulating film 15, a SiO ₂ film, Si
An N film, a PSG film or a composite film thereof can be used.

In the figure, W1 is the thickness of the n epitaxial layer 12, W2 is the distance between the p ⁺ gate region 16 and the n ⁺ drain region 11, and W3 is the distance between the p ⁺ guard ring region 13 and the n ⁺ drain region 11. , Xj is the diffusion depth of the p ⁺ guard ring region 13, and Rj is the p ⁺ guard ring region 1
3 shows a radius of curvature of 3. Rj is about 80% of Xj.

For example, W1 is 9 μm, the depth of the groove 14 is 1 to 1.5 μm, and the diffusion depth of the p ⁺ gate region 16 is about 0.5 μm. In the case of a conventional device having no p ⁺ guard ring region, BVgd is about 50 to 60V.
On the other hand, in the case of the device of the present invention provided with the p ⁺ guard ring region 13 having L1 of 8 to 13 μm and Xj of about 2 μm, BVgd is 120 to 140 V, which is about twice or more that of the conventional device. The value of was obtained.

In the case of the above-mentioned shape, W2 is about 7 μm in consideration of the transition region of the n ⁺ drain region 11 and the n epitaxial layer 12. In that case, the theoretical breakdown voltage is determined by the plane junction of the p ⁺ gate region 16 and is about 156V. With the structure having the p ⁺ guard ring region 13 according to the present invention, a value close to 90% of the theoretical breakdown voltage was obtained.

Next, the width L1 of the p ⁺ guard ring region 13
Will be described. In SIT provided p ⁺ guard ring region 13, a parasitic capacitance is generated that Cgd' between ^{p +} guard ring region 13 and ^{n +} drain region 11. The Cgd
Unless ′ is sufficiently small with respect to Cgd formed between the p ⁺ gate region 16 and the n ⁺ drain region 11, the high frequency characteristic deteriorates and specifically the power gain decreases. Therefore, it is necessary to make Cgd ′ small, and it is better to make L1 as short as possible. However, if L1 is too short,
Since the breakdown voltage is determined at the cylindrical junction portion around the p ⁺ guard ring region 13, the breakdown voltage BVgd is lowered. Therefore, the width L1 of the p ⁺ guard ring region 13 needs to be determined in relation to the breakdown voltage BVgd.

FIG. 3, 9 .mu.m and W1, 1 to 1.5 [mu] m and depth of the groove 14, ^{p +} about 0.5μm diffusion depth of the gate region 16, in the SIT was 2μm and Xj, ^{p +}
Guard ring width L1 and gate-drain breakdown voltage BVgd
The relationship is shown. According to the figure, BVgd is saturated when L1 is approximately 8 μm or more. When L1 is 8 μm or more, the depletion layer on the surface is the distance W2 from the p ⁺ gate region 16 to the n ⁺ drain region 11 (about 7 to 7.5 μm).
m) or more. This relaxes the electric field on the surface, and the breakdown voltage BVgd is determined at the plane junction of the p ⁺ gate region 16 inside the element. Therefore, in order to secure the breakdown voltage and at the same time reduce the parasitic capacitance Cgd ', it is desirable that the width L1 of the p ⁺ guard ring region 13 is set to about W2 or slightly larger.

In FIG. 4, one source length (parallel line width) is 120 μm and 100 sources are connected in parallel (total source length 1.2 c).
m) shows the relationship between the power gain calculated from the S-parameter measurement of the recessed gate SIT and the frequency. S of the present invention
IT has L1 of about 8 μm and is shown in comparison with a conventional SIT having no guard ring structure. The bias is the following condition. Since the BVgd of the SIT of the present invention having the p ⁺ guard ring is large, Vds is set to 50V, which is twice the SIT of the conventional type.

Bias condition Vds (v) Id (mA) Vgs (v) SIT 50 50-3.17 of the present invention SIT 25 50-4.45 of conventional type As shown in the same figure, MSG (Maximum Sta).
ble gain), that is, with respect to the maximum stable gain, the SIT of the present invention has a gain reduction of about 0.5 dB due to Cgd ′, but MAG (Maximum Availa).
ble Gain), i.e., since the maximum available gain comes out the effects of such inductance not only必<br/> Zushimo Cgd and Cgd ', substantially equal in interest <br/> to conventional SIT There are also frequencies that are more profitable. The SIT of the present invention is a conventional S
Compared to IT, the breakdown voltage can be doubled or more with almost no deterioration in frequency characteristics. That is, in the SIT having the same source length, the DC input can be doubled,
The output power is doubled.

Next, another embodiment according to the present invention will be described with reference to FIG. the n epitaxial layer 12 so as to be adjacent to the p ⁺ guard ring region 13 ^{p +} floating region 2
Form 2 The p ⁺ floating region 22 is formed in a band shape so as to surround the p ⁺ guard ring region 13.
It goes without saying that the p ⁺ floating region 22 may be provided in double or triple in order to obtain a higher breakdown voltage.
Here, the p ⁺ floating region is included, including the case of multiplexing.

Further, as shown in FIG. 6, an n ⁺ region 23 may be provided around the p ⁺ guard ring region 13.
The n ⁺ region 23 prevents the depletion layer from spreading too much from the p ⁺ guard ring region 13 and is used as a dicing region for cutting the element along a line along BB ′. By providing the n ⁺ region 23, it is possible to prevent the generation and increase of the leak current when cutting the element. The diffusion depth of the n ⁺ region 23 is at least the p ⁺ guard ring region 13
It is preferable that the depth is deeper than that, and it may be in contact with the n ⁺ drain region 11. Incidentally, ^p around the p + guard ring region 13 ⁺
The floating region 22 is provided, and the n ⁺ region 2 is provided around the floating region 22.
3 may be provided.

A method of manufacturing the SIT according to the present invention will be described with reference to FIGS. Incidentally, those FIG. 7 to FIG.
Shows a cross section taken along the line AA ′ in FIG.

First, the impurity density is 1 × 10 ¹⁸ to 1 × 1.
An n ⁺ substrate (hereinafter referred to as an n ⁺ drain region) 11 to be a drain region having a (100) or (111) plane of about 0 ¹⁹ cm ⁻³ is prepared. SiCl ₄ on top of it
And a high-resistance n epitaxial layer 12 grown by the vapor phase growth method using H ₂ and H ₂ are formed. The impurity concentration of the n epitaxial layer 12 is set to 1 × 10 ¹³ cm ⁻³ or less, or 1 × 10 ¹³ to 1 × 10 ¹⁵ cm ⁻³ . Also,
In order to obtain just pinch-off characteristics, the lower part of the n epitaxial layer 12 on the substrate side has an impurity concentration of 1 × 10 ¹³
cm ⁻³ , and the upper 2 μm to 3 μm may be about 5 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ^{−3, which} has a higher impurity density than the substrate side, and has a uniform impurity density or a non-uniform impurity density distribution depending on the design. It goes without saying that it is good as a layer. After that, using SiO ₂ or the like (not shown) as a mask,
The p ⁺ guard ring region 13 is formed by the ion implantation method or the like (FIG. 7).

Next, using the SiO ₂ film or the like (not shown) as a mask on the n epitaxial layer 12, a plurality of trenches 14a and 14b to serve as recess gates are formed in the n epitaxial layer 12 by the RIE method. The outermost groove portion 14a is formed so as to partially overlap with the p ⁺ guard ring region 13 in the longitudinal direction, and the groove portion 14b is formed so as to overlap with the p ⁺ guard ring region 13 at an end not shown. Groove 14
The widths of a and b are 2 μm and 1 μm, respectively, and the depth is 1 to 1.
5 μm. The interval between the adjacent groove portions 14 is, for example, 3 to 7.
It may be μm. RIE uses a mixed plasma of SF ₆ and O ₂ gas (FIG. 8).

After that, the insulating film 15, for example, 0.5 to 1 μm
An oxide film having a thickness of about m is formed by oxidizing the entire surface of the n epitaxial layer 12 in water vapor. Grooves 14a, b are formed by RIE using CF ₄ or a mixed gas of CF ₄ and CHF _3.
Is opened only at the bottom of the substrate to expose the n-epitaxial layer 12. Subsequently, the p ⁺ gate region 1 is diffused into the window-opened region by boron or the ion implantation method.
6a, b are formed. By this step, the p ⁺ guard ring region 13 and the p ⁺ gate region 16a are connected. still,
Similarly, the p ⁺ gate region 16b is connected to the p ⁺ guard ring region 13 at its end (not shown). The diffusion depth of the p ⁺ gate region 16 is about 0.5 μm (FIG. 9).

Next, a mask pattern such as a resist is formed on the entire surface.
Then, the insulating film 15 in the portion to be the source region is removed by RIE or the like to expose the n epitaxial layer 12 (FIG. 10). Implanting phosphorus or arsenic into the exposed n epitaxial layer 12 by ion implantation,
The n ⁺ source region 18 is formed. After that, the mask pattern 17 is removed. The mask pattern 17 is made of SiO ₂
And the like, the n ⁺ source region 18 can also be formed by diffusion from polycrystalline silicon added with an n-type impurity (FIG. 11). Then, the p ⁺ gate region 16, the n ⁺ source region 18 and the n ⁺ drain region 1 formed as described above are formed.
A gate electrode 19, a source electrode 20 and a drain electrode 21 are formed on each of the layers (FIG. 12).

Although the recess gate type SIT has been described, the same can be said for the side gate type SIT by providing the guard ring region 13. Also,
Not only SIT made of Si but also other GaAs, I
It goes without saying that the present invention can also be applied to compound semiconductors such as nP.

[0032]

In the recess gate type or the side gate type SIT, by providing the guard ring region around the gate region, the gate / drain junction resistance is significantly improved.
It is possible to obtain an element having a large pressure . The SIT of the present invention can provide a high-output SIT with almost no deterioration in high-frequency characteristics, and the voltage that can be applied between the drain and the source is more than double that of the conventional SIT.

[Brief description of the drawings]

1A is a plan view schematically showing an SIT according to a first embodiment of the present invention, and FIG. 1B is an enlarged view of a circled portion in FIG. 1A.

FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG.

FIG. 3 is a graph showing the relationship between the width L1 of the guard ring and the gate-drain breakdown voltage BVgd.

FIG. 4 is a graph showing frequency characteristics of power gain of SIT according to the present invention.

FIG. 5 is a sectional view schematically showing a SIT of a second embodiment according to the present invention.

FIG. 6 is a sectional view schematically showing a SIT according to a third embodiment of the present invention.

FIG. 7 is a first process sectional view showing the method of manufacturing the SIT according to the present invention.

FIG. 8 is a second process sectional view showing the method for manufacturing an SIT according to the present invention.

FIG. 9 is a third process sectional view showing the method for manufacturing an SIT according to the present invention.

FIG. 10 is a fourth process sectional view showing the method of manufacturing the SIT according to the present invention.

FIG. 11 is a fifth process sectional view showing the method of manufacturing the SIT according to the present invention.

FIG. 12 is a sixth process sectional view showing the method for manufacturing an SIT according to the present invention.

13A is a sectional view schematically showing a conventional recess gate type SIT, and FIG. 13B is a sectional view schematically showing a conventional side gate type SIT.

[Explanation of symbols]

11 ... n ⁺ drain region (n ⁺ substrate), 12 ... n epitaxial layer 13 ... p ⁺ guard ring region, 14 ... groove, 15 ... insulating film 16 ... p ⁺ gate region, 17 ... mask pattern, 18 ...
n ⁺ source region 19 ... Gate electrode, 20 ... Source electrode, 21 ... Drain electrode 22 ... P ⁺ floating region, 23 ... N ⁺ region

Claims (7)

(57) [Claims] 1. A drain region of one conductivity type, a channel region of one conductivity type provided on the drain region, a plurality of source regions of one conductivity type provided in the channel region, and a drain region of the channel region. A plurality of groove portions provided, and a plurality of gate regions of opposite conductivity type provided in the channel region from the bottom portion of each groove portion or a part of the bottom portion, the plurality of source regions and the plurality of gate regions; Are arranged so as to be parallel to each other, and have guard ring regions of opposite conductivity type that are connected to the respective gate regions and are arranged around the plurality of gate regions and are provided in the channel region. Static induction transistor. 2. The static induction transistor according to claim 1, wherein the plurality of source regions are respectively sandwiched between the plurality of gate regions. 3. The static induction transistor according to claim 1, wherein a width of the guard ring region is equal to or larger than a distance between the gate region and the drain region. 4. A floating region having an opposite conductivity type is provided in the outer peripheral portion of the guard ring region and is provided in the channel region.
The static induction transistor described. 5. The static induction transistor according to claim 1, further comprising a semiconductor region of one conductivity type disposed in the outer peripheral portion of the gate ring region and provided in the channel region. 6. The static induction transistor according to claim 5, wherein the semiconductor region is used as a dicing region. 7. A step of preparing a semiconductor substrate of one conductivity type to be a drain region, a step of forming a semiconductor layer of one conductivity type to be a channel region on the semiconductor substrate, and a strip-shaped opposite conductivity to the semiconductor layer. Forming a guard ring region of a mold, forming a plurality of groove portions in the semiconductor layer in parallel lines inside the guard ring region, and forming the guard ring region in the semiconductor layer from the bottom of the groove portion. Forming a plurality of gate regions of opposite conductivity type formed so as to be connected to the semiconductor device, and forming a plurality of source regions of one conductivity type inside the guard ring and alternating with the plurality of gate regions. And a step of forming the layer into a layer.