JP2688487B2 - Pulse width modulation inverter controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a pulse width modulation inverter having a function of correcting distortion of an output voltage due to a dead time of a main circuit switching element, and particularly suitable for induction motor operation. The present invention relates to a control device for a pulse width modulation inverter. [Prior Art] Various switching elements used in a pulse width modulation inverter inevitably have a switching delay. Therefore, an arm short circuit is required to control the switching elements that constitute each arm of the inverter main circuit. It is necessary to set a so-called dead time to prevent this. As a result, distortion occurs in the output of the inverter, that is, dead time distortion. Therefore, in a conventional pulse width modulation inverter (hereinafter referred to as a PWM inverter), for example, as described in JP-A-60-207464, a current detector is provided for each phase of the PWM inverter output, and a current detector is obtained from these current detectors. Voltage distortion due to dead time was corrected by correcting the gate signal given to the positive and negative side switching elements of each phase arm of the PWM inverter main circuit according to the polarity of each phase current. [Problems to be Solved by the Invention] By the way, such a PWM inverter is often operated with an induction motor or the like as a load, but in the above-mentioned conventional technology, when the electric motor is used as a load, the load current is No consideration was given to the ripple components that would be included,
There is a problem in that the detection accuracy of the current zero phase point necessary for determining the current polarity cannot be obtained sufficiently. Especially when operating a motor with a PWM inverter,
It is customary to variably control the output frequency. At this time, as a matter of course, the number of pulses per cycle of the output voltage of the PWM signal also changes, and as a result, the accuracy of the current polarity determination described above further deteriorates. An object of the present invention is to provide a PWM inverter control device that can always perform sufficient current distortion correction without detecting current. [Means for Solving Problems] The above-mentioned object is to provide a signal serving as a reference for creating a gate signal to be applied to the PWM inverter main circuit switching element and a pulsed arm voltage generated in the arm of each phase of the main circuit. It is achieved by comparing, detecting the error component by these calculations, and performing the correction. Therefore, the arm voltage detecting means for detecting the arm voltage of each phase of the pulse width inverter,
An error voltage detecting means is provided, and by this error voltage detecting means, an error pulse is obtained from the reference PWM signal and the pulse voltage detected by the arm voltage detecting means, and this error pulse is synchronized with the rising time of the reference PWM signal. When the error pulse is positive, the error pulse is negative when it is synchronized with the falling time, and the positive pulse is adjacent to the positive error pulse in the positive direction. A correction error voltage in the negative direction is generated between the sex error pulses. [Operation] An error pulse is generated when there is a level mismatch between the reference PWM signal and the arm voltage (pulse). For example, when the negative arm voltage of the PWM inverter is detected as the arm voltage, the PWM in the error pulse is
The falling sync error pulse that is synchronized with the falling time of the signal becomes an extra voltage with respect to the voltage command, and the rising sync error pulse that is synchronized with the rising time of the PWM signal becomes a voltage that is insufficient with respect to the voltage command. Become. Therefore, the rising sync error pulse synchronized from the error pulse to the rising time of the PWM signal and the falling sync error pulse synchronized to the falling time of the PWM signal are separated, and the rising sync error pulse is generated. Then, the voltage command and the magnetic flux command are corrected so as to increase, and conversely, these commands are corrected so as to decrease in the section where the falling sync pulse is generated. This operation provides a control function in the direction in which the generation of the error pulse is suppressed, so that a voltage or magnetic flux without distortion corresponding to the voltage command or the magnetic flux command can be obtained. [Embodiment] Hereinafter, a PWM inverter control device according to the present invention will be described in detail with reference to the illustrated embodiment. FIG. 1 is an embodiment of the present invention. In the figure, one terminal of a U-phase arm 2, a V-phase arm 3 and a W-phase arm 4 is connected to the positive side terminal of a DC power supply 1, The other terminal of the U-phase arm 2, the V-phase arm 3 and the W-phase arm 4 is connected to the negative terminal of the. The U-phase arm 2, the V-phase arm 3 and the W-phase arm 4 are respectively composed of a positive side arm and a negative side arm, but since they have the same configuration, only the U-phase arm 2 will be explained, The description of the configuration of the phase arm of is omitted. The positive side arm of the U-phase arm 2 is a power transistor 21,
It is composed of a diode 23, and the anode terminal of the power transistor 21 and the cathode terminal of the diode 23 are both connected to the positive side of the DC power supply 1. The cathode terminal of the power transistor 21 and the anode terminal of the diode 23 are connected to the U-phase terminal of the induction motor 5. On the other hand, the negative side arm of the U-phase arm 2 is composed of the power transistor 22 and the diode 24.
And the cathode terminal of the diode 24 are both connected to the U-phase terminal of the induction motor 5. The cathode terminal of the power transistor 22 and the anode terminal of the diode 24 are both connected to the negative side of the DC power supply 1. From each phase arm described above to the U phase, V of the induction motor 5
One terminal of resistors 61, 71, 81 is connected to the line connected to each phase and W phase terminal, and the other terminal of each resistance is U phase photo coupler 6, V phase photo coupler 7, and W phase The photocoupler 8 is connected to the respective Ard terminals of the primary side light emitting diodes. Primary side light emitting diode 62 in U-phase photo coupler 6
Is connected to the negative terminal of the DC power supply T. The anode terminal of the secondary side phototransistor 63 of the U-phase photocoupler 6 is connected to the power supply, and the cathode terminal is grounded via the resistor 64. Since the photo couplers 7 and 8 have the same structure as the photo coupler 6, their details are omitted. The cathode terminals of the secondary side phototransistors of the photo couplers 6, 7, 8 are connected to one input terminal of the error pulse detection circuit 9. The other input terminal of the error pulse detection circuit 9 is connected to the output terminal of the PWM signal generation circuit 15.
The output terminal of the error pulse detection circuit 9 is the error voltage detection circuit 10
Is connected to the input terminal. Further, the other input terminal of the error voltage detection circuit 10 is connected to the output terminal of the inverter input voltage circuit 101. The three output terminals of the error voltage detection circuit 10 are connected to the negative terminals of the subtracters 12, 13, and 14, respectively. The voltage command V _R and the frequency command ω _R are input to the modulated wave generation circuit 11. The three output terminals of the modulated wave generation circuit 11 are connected to the plus terminals of the subtracters 12, 13, and 14, respectively. Subtractor 1
The output terminals of 2, 13, 14 are connected to the input terminals of the PWM signal generation circuit 15. The output terminals U _P and U _N of the PWM signal generating circuit are the gate terminals U _P and U of the power transistor 21 on the positive side of the U-phase arm 2.
It is connected to the gate terminal U _N of the power transistor 22 of the negative-side arm of the phase arm. The other output terminals V _P and V _{N of the} PWM signal generation circuit 15 are also V
It is connected to the gate terminals of the power transistors 21 on the positive and negative arms of the phase arm 3. Similarly, the output terminals W _P and W _N of the PWM signal generation circuit 15 are also connected to the gate terminals of the positive side arm and the negative side arm of the W-phase arm 4, respectively. Therefore, the control pulse is supplied from the PWM signal generating circuit 15 to the arms 2, 3, and 4, whereby the DC power from the DC power supply 1 is converted into a three-phase AC power having a predetermined voltage at a predetermined frequency, It will be supplied to the induction motor 5. Next, the control operation of the circuit of FIG. 1 will be described with reference to FIG. In Fig. 2, the configuration of one phase of the U phase of the PWM inverter and the direction of current flow are divided into four in the upper stage, and in the middle stage, the triangular wave, the modulation wave, and the fundamental wave component of the primary current are described. Is shown. And, in the lower stage, the reference U-phase PWM signal E _U obtained by the comparison between the triangular wave and the modulated wave, and the gate of the U-phase positive arm obtained based on the PWM signal E _U signals U _P, the gate signal U _N of the negative-side arm, the gate signals U _P, the power transistors Yotsute U-phase to U _N are controlled to generate the negative-side arm when current is flowing to the upper U phase negative-side arm voltage e _u, PWM signal E _U and U-phase arm voltage e _u and the exclusive (E _U e _u) an error pulse a is obtained Te convex, PWM signal E _U of this error pulse a rising synchronous error pulse b in synchronization with the rise time of, PWM signal E falling synchronous error pulses c in synchronism with the falling time of the _U among the error pulse a, the polarity of the rising synchronous error pulse b negative, the falling The error voltage d obtained by setting the polarity of the synchronization error pulse c to be positive, and the phase of the error voltage d matches the error voltage d. Then, the square wave-shaped error voltage d height whose positive and negative magnitudes are proportional to the positive portion and the negative partial area of the error voltage d is sequentially shown. The operation of the embodiment shown in FIG. 1 will be described below using the above signals. Since the time t ₁ before and summer and the gate signal U _N is "1" level of the negative-side arms of the U-phase, conductive and negative side of the transistors of U-phase, the current path Tado connexion negative direction Is flowing. Therefore, the potential at the point A has the same voltage as the negative side of the DC power supply 1. As a result, since no current flows in the light emitting diode of the photocoupler 6, the secondary side phototransistor 63 is also not conducted, and the negative arm voltage e _u obtained from the photocoupler 6 becomes "0" level. Becomes the gate signal U _N is "1" level to the "0" level of the negative-side arm of the U-phase at time t _1, and conducts the diode 23 to the direction does not change the flow of current, through a path connexion current Flows. As a result, the potential at the point A becomes the same potential as the positive side potential of the current power supply 1, current flows through the light emitting diode 62, and the negative side arm voltage becomes the "1" level at this time t ₁ . Gate signal U _P of the positive side of the arm of the U-phase from time t ₁ until time t ₂ has elapsed, the gate signal U _N of the negative-side arm are decreased to both "0" level. Generally, even if the gate signal of the power transistor is turned on, this power transistor does not turn off immediately. Therefore, by operating the gate signal in this way, the transistor in the positive arm and the transistor in the negative arm are Simultaneous conduction (short circuit state) is avoided. This time is a so-called Detsudotaimu T _d, the period during current also in this Detsudotaimu T _d is without interruption, in continue to flow in the path shown. Therefore, the arm voltage e _u negative side obtained from Fuotokapura 6 is decreased to remain "1" level. At time t ₂ when the time T _{d has} elapsed, the gate signal of the positive arm of the U phase becomes the “1” level. Again, current continues to flow in the negative direction through the path. Therefore, the negative arm voltage
e _u remains at “1” level. This state is at time t ₃
In PWM signal E _U and the gate signal U _P is "0" continues from a connexion to the level until the time t ₄ when further Detsudotaimu T ₄ has elapsed. At time t ₄ , the gate signal U _N becomes “1” level, and at this time,
To flow in the current path, the arms voltage e _u is the time t ₁ as before "0" level. Here the voltage command PWM signal E _U and a negative side of the arm voltage e
_Let's compare _u . During the T _d of the PWM signal E _U the time t ₃ from falling connexion to the gate signal U _N rises, the arm voltage e _u negative side is level "1". In this way, when the current direction is flowing from the motor side to the inverter side, the PW
Even if the M signal E _U falls, the negative arm voltage e _u does not become the level “0” during the period of T _d until the gate signal U _N rises. Next, the case where the current flows from the inverter side to the electric motor side, that is, in the positive direction will be described. At time t ₅ before PWM signal E _U and the gate signal U _P is decreased to "1" level, the positive-side arm of the U-phase transistor 21
Is conducting, and the current is flowing in the positive direction along the path. In such a state, the potential at the point A is the same as the positive potential of the DC power supply 1, and the negative arm voltage e _u is at “1” level. Time t ₅ in PWM signal E _U and the gate signal U _P becomes "0" level. At this time, the current tries to continue flowing in the positive direction without being interrupted through the path of. As a result, the potential at the point A becomes the same potential as the negative side of the DC power supply 1. Arm voltage e _u of the sub connexion negative becomes "0" level in this state. This state continues from the PWM signal E _U the time t ₆ after Detsudotaimu T _d, until the gate signal U _P becomes "1" level. As a result, the arm voltage of the negative side of the PWM signal E _U as a potential command e _u is the time t ₆
From (t ₆ + T _d ) the potential decreases (becomes level “0”). Negative arm voltage in the section where current flows in the positive direction
The "1" level of e _u coincides with the "1" level of the gate signal U _P on the positive side of the U phase. Meanwhile, the gate signal U _P is made One Kezurito only pulse width corresponding to Detsudotaimu T _d from the rising time of the PWM signal E _U. If slave connexion current is flowing in the positive direction, the pulse width of the arm voltage of the negative side is only the pulse width Detsudotaimu T _d becomes narrower from the rising time of the PWM signal E _U. For the same considerations, when current is flowing in the negative direction, the pulse width of the arms potential of the negative-side Detsudotaimu T _d by the pulse width increases from the falling point of the PWM signal E _U. From the above, to detect the negative side of the arm voltage having the same pulse width as the inverter output voltage (phase voltage) (pulse signal) and a pulse width of the PWM signal E _U as a reference for voltage error (error pulse) This means that the error voltage is obtained without directly detecting the direction of the current. Returning to Fig. 1, the arm voltage on the negative side of each of the U, V, and W phases
e _u, e _v, e _w is by connexion detected Fuotokapura 6, 7 and 8, this signal is input to the error pulse detection circuit 9. Error pulse detection circuit 9 PWM signal E _U as a reference, E _V, E _W and negative arm voltage e _u, e _v, detecting a pulse error between e _w. Exclusive of the pulse error PWM signal E _U and e _u, and E _V and e _v and E _W and e _{w
E U e u, E V e} v, obtained from E _W e _w. The signal a in FIG. 2 represents the U-phase error pulse obtained as a result. Note that the circuit operation of the other phases is exactly the same as that of the U phase, and therefore will be omitted. Next, determine the error pulse signal a rising synchronization is synchronized with the rising edge of the PWM signal E _U from the error pulse b and falling synchronous error pulses c in synchronism with the fall timing.
Here, the rising synchronization error pulse b is the error pulse a and the PWM
It sought Te logical product a · E _U Niyotsu the signals E _U, falling synchronous error pulse c is calculated Te logical product a · _U Niyotsu the inverted signal _U and the error pulse a of the PWM signal E _U. The error pulse detection circuit 9 inputs the rising sync error pulse b and the rising sync error pulse c to the error voltage detection circuit 10. This error voltage detection circuit 10 is
The rising synchronous error pulse b is converted into a pulse voltage having the negative peak value consisting -E _D based on E _D, to convert further the falling synchronous error pulse c to a pulse voltage having a positive peak value becomes E _D. By such an operation, the error voltage shown in d of FIG. 2 is obtained. Then, this error voltage d is converted into a high error voltage d via a filter (first-order lag element), and further multiplied by an appropriate gain in the error voltage detection circuit 10 to obtain an error voltage correction signal for correcting the modulated wave. It is output as ΔV _u . The modulation wave generation circuit 11 in magnitude to the voltage command V _R, and the frequency is the frequency command W _R sinusoidal modulation wave E _u equal, respectively, are generated. Here, there is a detection delay in creating the error voltage correction signal ΔV _u . Therefore, in order to eliminate the influence of this detection delay, the modulated wave generation circuit 11 delays the modulated wave _Eu based on the equation (1). Here, T ₁ is a time constant and is selected so as to have a value of 4 to 5 times or more the delay time required for detecting ΔV _u . This is to prevent the modulated wave from changing within the time required to detect ΔV _u . In this way, the PWM signal is generated using the correction modulation wave obtained by subtracting the error voltage correction signal ΔV _u from the modulation wave E _u height obtained by the equation (1). By doing so, when an error appears between the reference PWM signal and the output voltage of the inverter, a correction modulation wave that makes this error zero is generated. Therefore, the voltage distortion caused by the dead time is suppressed. In the above description, the delay until the power transistor, which is the arm switching element, is ignited is ignored. However, since there is actually a delay in firing, for example, at time t ₁
At the time point of, the PWM signal E _U and the negative side arm voltage e _u do not match. Therefore, this problem is solved by delaying the PWM signals E _U , E _V , and E _W used when obtaining the error pulse by the ignition delay time. By the way, in such a PWM inverter, the magnitude of the error voltage affecting the voltage distortion is proportional to the product of the carrier frequency, the dead time, and the inverter input voltage. In the embodiment shown in FIG. 1, however, the error voltage is accurately detected even when such parameter changes occur, so that the modulated wave can always be properly corrected. That is, when the inverter frequency and voltage command change, PW
The current ripple changes by changing the frequency and conduction ratio of the M signal. However, in the present invention, since the polarity of the current is not detected, it can be sufficiently corrected even if the current ripple changes. Next, another embodiment of the present invention will be described. FIG. 3 shows an embodiment of the present invention in the case of controlling a PWM signal by a magnetic flux command for an induction motor as a load, and is different from the embodiment of FIG. 1 in error voltages ΔV _u , ΔV _V , Δ
Since the point is the same as the point where the error voltage detection circuit 10 for detecting V _w is provided, only the connection relationship thereafter will be described. The output terminal of the error voltage detection circuit 10 is the error magnetic flux detection circuit 16
The error voltages ΔV _u , ΔV _v , and ΔV _w are input. One output terminal of the error magnetic flux detection circuit 16 is connected to the input terminal of the operational amplifier 131, and the other output terminal is connected to the input terminal of the operational amplifier 132, and Δφ _qs and Δφ _ds are input to each input terminal. It The output terminal of the operational amplifier 131 is connected to one terminal of the adder 171, and the magnetic flux command φ _ds is input to the other terminal, but the output terminal of the operational amplifier 132 is directly input to one of the correction magnetic flux operation circuits 18. Connected to the terminal. The adder 171 is connected to the other input terminal of the correction magnetic flux calculation circuit 18.
Of the signals φ ^* _ds and −φ are connected.
^* _Qs is input to each input terminal. The angular frequency command ω ₁ is input to the instantaneous angle calculation circuit 19 and the error magnetic flux detection circuit 16. The output terminal of the instantaneous angle calculation circuit 19 is connected to one input terminal of the adder 172, and the instantaneous angle θ is input. The other input terminal of the adder 172 is connected to one output terminal of the correction magnetic flux calculation circuit 18, and the corrected angle ψ is input. The other output terminal of the correction magnetic flux calculation circuit 18 is connected to one input terminal of the PWM signal generation circuit 15, and the correction magnetic flux φ ^* is input. The other input terminal of the PWM signal generation path 15 is connected to the output terminal of the adder 172, and the correction magnetic flux phase θ ^* is included in this circuit 15 ^.
Is entered. The output terminal of the PWM signal generation circuit 15 is connected to the gate terminals of the positive side arm and the negative side arm of the U-phase, V-phase and W-phase, and the gate signals _UP , _UN , _VP , _VN , W _P , W _N are supplied. The error voltages ΔV _u , ΔV _v , and ΔV _w are detected as described in the embodiment of FIG. 1, and the error magnetic flux is calculated based on the detected voltages. First, the three-phase error magnetic fluxes Δφ _u , Δφ _v , and Δφ _w are calculated based on the respective phase error magnetic fluxes according to equations (2), (3), and (4). Then, the three-phase error magnetic fluxes Δφ _u , Δφ _v , and Δφ _w are subjected to dq axis coordinate conversion based on the equations (5), (6), and (7). Δφ _qs = Δφ _u · sin (ω ₁ t) + Δφ _v · sin (ω ₁ t −2π / 3) + Δφ _w · sin (ω ₁ t + 2π / 3) (5) Δφ _ds = Δφ _u · cos (ω ₁ t) + Δφ _v · cos (ω ₁ t −2π / 3) + Δφ _w · cos (ω ₁ t + 2π / 3) (6) Next, the error magnetic fluxes Δφ _qs and Δ displayed in the dq axis coordinates.
Based on _Eqs. (7) and (8) using φ _ds , the magnetic flux command φ _ds
To obtain the magnetic fluxes φ ^* _ds and φ ^* _qs . However, T _o ; time constant S; Laplace operator, and magnetic flux φ ^* _ds , φ ^* _qs displayed on the dq axis coordinates
Is used to obtain the correction magnetic flux φ displayed in polar coordinates in the correction magnetic flux calculation circuit 18, and distortion of the magnetic flux can be suppressed by generating a PWM signal so as to follow the correction magnetic flux φ. Therefore, necessary data φ ^* , Θ ^* are calculated by the following equations. φ = φ ^*・ e ^j θ ^* (9) θ ^* = ∫ω ₁ dt + tan ⁻¹ (−φ ^* _qs / φ ^* _ds ) (11) As described above, the PWM signal generation circuit 15 generates the PWM signal so as to follow the correction magnetic flux φ. As one of the methods, for example, the following method can be considered. This is based on the fact that the voltage vector is given as the normal line of the magnetic flux, and θ on the correction magnetic flux circle shown by the solid line in FIG.
^Find the normal vector at ^* . A voltage vector having a direction closest to the direction of this normal vector is selected from FIG. By repeating such an operation every predetermined time, an optimum voltage vector that follows the correction magnetic flux can be obtained. Therefore, according to this embodiment, since the PWM signal generated from the PWM signal generation circuit 15 is controlled so as to suppress the generation of the error magnetic flux, the voltage distortion due to the dead time can be sufficiently corrected with high accuracy. Therefore, the induction motor 5 can always obtain a magnetic flux without distortion, and can provide good torque characteristics. As a method of generating the PWM signal by the PWM signal generating circuit 15, the equation (9) may be differentiated and the obtained waveform may be generated as a modulation wave by comparing this with a triangular wave. [Effects of the Invention] According to the present invention, voltage distortion due to dead time can be suppressed without detecting the polarity of the current. Therefore, the current detector becomes unnecessary, and at the same time, it is not affected by the ripple of the current. Even if the voltage changes, the voltage distortion can be suppressed accurately.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a pulse width inverter control device according to the present invention, FIG. 2 is a waveform diagram for explaining the operation, and FIG. 3 is another embodiment of the present invention. Block diagram showing an example,
FIG. 4 is an explanatory diagram of the correction magnetic flux circle, and FIG. 5 is an explanatory diagram of the voltage vector. 1 ... DC power supply, 2 ... U-phase arm, 3 ... V-phase arm, 4 ... W-phase arm, 21,22 ... Power transistor, 23,24 ... Diode, 6,7,8 ... Photocoupler , 9
...... Error pulse detection circuit, 10 ・ ・ ・ Error voltage detection circuit, 11
...... Modulation wave generation circuit, 12,13,14 …… Subtractor, 15 …… PWM
Signal generation circuit, 101 ... Inverter input voltage detector, 16
...... Error magnetic flux detection circuit, 131,132 ...... Operational amplifier, 18 ...
… Compensation magnetic flux calculator, 19 …… Instantaneous angle calculator.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Kenji Nanto               7-1-1 Higashi Narashino, Narashino City, Chiba Prefecture                 Narashino Factory, Hitachi, Ltd. (72) Inventor Toshio Suzuki               4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Co., Ltd.               Hitachi Research Laboratory, Hitachi Research Laboratory                (56) References JP-A-59-123478 (JP, A)                 JP-A-60-82066 (JP, A)

Claims (1)

(57) [Claims] A pulse width inverter for generating a reference PWM signal based on at least one of a voltage command and a magnetic flux command, converting DC power into AC power having a variable frequency and a variable voltage, and driving an AC motor at a variable speed. The arm voltage detection means for detecting the arm voltage of each phase, the reference PWM signal, and the error pulse is obtained from the pulse voltage detected by the arm voltage detection means, the error pulse at the rising time of the reference PWM signal. When synchronized, the error pulse is set to positive polarity, when synchronized to the falling time point, the error pulse is set to negative polarity, and the positive polarity error pulses adjacent to each other are in the positive direction and are adjacent to each other. The pulse width modulation inverter control device is provided with error voltage detection means for generating a correction error voltage in a negative direction between the negative error pulses. . 2. It is configured to correct the modulation wave formed from the voltage command using the error voltage detected by the error voltage detection means, and to generate a reference PWM signal based on the corrected modulation wave. The pulse width modulation inverter control device according to claim 1. 3. An error magnetic flux is calculated using the error voltage detected by the error voltage detecting means, and the magnetic flux command is corrected using this error magnetic flux to generate a reference PWM signal. The pulse width modulation inverter controller according to the first section.