JP2687795B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MASK ROM type semiconductor device having redundant cells.

[0002]

2. Description of the Related Art In a MASK ROM, with the increase in memory capacity, relief of bit defects becomes an important factor for increasing the profit rate.

On the other hand, in the RAM, since the RAM cell is not programmed during the wafer process, the replacement with the redundant cell can be performed relatively easily. However, in MASK ROM, the redundant cells must be programmed because the cell data is programmed during the wafer process.

As one of the methods, one-time PRO
There is a method of incorporating M, but in order to incorporate it in the MASK ROM, it is necessary to minimize the complexity of the manufacturing process and the circuit configuration.

FIG. 3 shows an example of a MASK ROM type semiconductor device provided with a redundant circuit by one-time PORM.

This semiconductor device has a plurality of bit lines BL1.
To BL3, which are provided between the bit lines BL1 to BL3 and the reference potential point, respectively, and are turned on when the first signal supplied to the gate is at the non-selection level, and the internal storage state is at the selection level. Memory cell M formed of a first transistor that is turned on or off according to (diffusion state)
1. A plurality of vertically stacked memory cell blocks MB in which 1 and M2 are connected in series and a plurality of word lines WL1 and WL2 for supplying the first signals corresponding to the gates of the respective transistors of these memory cell blocks MB are provided. Memory cell array 1 and redundant bit lines BLr1, BLr2,
Redundant word lines WLr1 and WLr2 and write / reference line W provided corresponding to write select lines WS1 and WS2 and memory cells M1 and M2 of memory cell block MB, respectively.
A transistor Q1 connecting R1 and WR2 and one of a source and a drain to a corresponding redundant bit line (BLr1 and BLr2) and a gate to a corresponding redundant word line (WLr1 and WLr2), and a source of the transistor Q1.
The other of the drains and the corresponding write / reference lines (WR1, W
The fuse F1 connected between R2) and the source and drain are connected between the other of the source and drain of the transistor Q1 and the reference potential point, and the gate is connected to the corresponding write selection line (WS).
, WS2) and a plurality of redundant memory cells Mr1x, Mr2x formed including a transistor Q2 connected to
The write / reference lines WR1 and WR2 are set to the write voltage level during the write operation and set to the reference potential otherwise, and one of the write selection WS1 and WS2 is selected during the write operation. And a selection circuit 4 for setting

[0007]

In this conventional semiconductor device, the redundant memory cells Mr1x and Mr2x are each formed by two transistors and one fuse, and the writing for writing to these redundant memory cells Mr1x and Mr2x is performed. Built-in circuit 3 and selection circuit 4 and write selection lines WS1, WS
2 and writing / reference lines WR1 and WR2 are required,
There is a problem that the occupied area of the redundant cell array and the redundant circuit including these becomes large.

An object of the present invention is to provide a semiconductor device which can reduce the area occupied by a redundant circuit.

[0009]

According to the present invention, there is provided a semiconductor device comprising:
A plurality of memory cells formed by first transistors that are turned on when the first signal supplied to the plurality of bit lines and gates is at the non-selection level and turned on or off according to the internal storage state when the first signal is at the selection level. Supplying the plurality of memory cell blocks connected in series between the bit lines and the reference potential point, respectively, and the first signal corresponding to the gate of each transistor of these memory cell blocks. A memory cell array having a plurality of word lines, a plurality of high resistances provided corresponding to the plurality of word lines, respectively, to one end of which a power supply potential is supplied, redundant bit lines, and memories of the memory cell block. A second transistor provided corresponding to each cell and turned on when the second signal supplied to the gate has the first level and turned off when the second signal has the second level. A plurality of redundant memory cells which are formed of a star and are connected in series between the redundant bit line and the reference potential point, and the high resistance which is provided corresponding to each of the plurality of redundant memory cells and has one end corresponding thereto. Connected to the other end of the word line, and the other end of the word line is connected to the corresponding word line in a state where it can be cut by a predetermined cutting means. It has a redundant cell array having a plurality of redundant word lines that are at the first level regardless of the level of the word line when the disconnection means is in the disconnected state.

Further, a plurality of redundant word lines are formed on the substrate on which the plurality of memory cells and the redundant memory cells are formed, an interlayer insulating film is formed on the plurality of redundant word lines, and a predetermined amount of the interlayer insulating film is formed. One contact hole is formed at a position, and a plurality of high resistances which are integrated on the contact hole and the interlayer insulating film and are respectively connected to the plurality of redundant word lines are formed. doing.

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

Memory cell arrays 1a and 1b of this embodiment
Has the same configuration as the memory cell array 1 of the conventional semiconductor device shown in FIG. However, in FIG. 1, up to four memory cells included in one memory cell block MB are displayed.

The other parts are a plurality of word lines WL1 to WL1.
A plurality of high resistances R11 to R14, (R2, which are provided corresponding to WL4, respectively, are supplied with a high level power supply potential VDD at one end and have a resistance value sufficiently higher than that of the word lines WL1 to WL4.
1 to R24) and (R21 to R24 are connected to the circuit R1
Since it is the same as the circuit connected to 1 to R14, only the circuit connected to R11 to R14 will be described below. ),
A second bit which is provided corresponding to each memory cell of the redundant bit line BL1 and the memory cell block MB and is turned on when the second signal supplied to the gate has the first level and turned off when the second signal has the second level. A plurality of redundant memory cells Mr1 to Mr4, which are formed of the transistors and are connected in series between the redundant bit line BLr1 and the reference potential point, and the plurality of redundant memory cells Mr1 to Mr4, respectively. Is connected to the other end of the corresponding high resistances R11 to R14, and the other end is connected to the corresponding word line (WL1 to WL4) in a state where it can be cut by cutting means such as a laser. In the connected state, these word lines are at the selected level. Then the second level,
A plurality of redundant word lines WLr1 are set to the first level if the level is the non-selection level and to the first level regardless of the level of the word line when the disconnection means does not connect them.
To WLr4 in a vertically stacked type redundant cell array 2a (and 2b connected to R21 to R24).

Next, the operation of this embodiment and the programming of cell data of the redundant cell array 2a will be described.

Memory cells M1 to M1 of the memory cell array 1a
M4 is a diffusion state programmed in the wafer process and is classified into an enhancement type and a depletion type, and the stored contents are determined by this. If the transistors forming these memory cells are N-type, word lines WL1 to W
By setting the selection level of L4 to the low level and the non-selection level to the high level, the memory cell is turned on at the non-selection level, turned off at the enhancement type of the memory cell (transistor), and turned on at the depletion type. , The current of the corresponding bit line is determined according to the stored contents of the memory cell corresponding to the selected level word line.

Each transistor of the redundant memory cells Mr1 to Mr4 is turned on or off under the above-mentioned conditions.
The type is an enhancement type. Redundant word line (WLr
1 to WLr4) and the word lines (WLr to WL4) are connected to each other, they become high level in the non-selected state, so that the redundant memory cells Mr1 to Mr4 are turned on.

When one of the word lines, for example, WL3, goes to the low level of the selection level, the word line WL3 and the redundant word line W
With Lr3 connected, word lines WL3,
High resistance R1 having a resistance value sufficiently higher than that of the redundant word line WLr3
Since the high-level power supply potential VDD is supplied via 3, the redundant word line WLr3 also becomes substantially low level, and the gate of the transistor forming the memory cell Mr3 becomes low level and the memory cell Mr3 is turned off. Further, in the state where the word line WL3 and the redundant word line WLr3 are disconnected, the low level of the word line WL3 is not transmitted to the redundant word line WLr3, so that the memory cell Mr3 has a high resistance R13 at the gate of the transistor forming the memory cell Mr3. A high-level power supply potential VDD is supplied via the switch to turn on.

In this way, the word lines (WL1 to WL
4) and the redundant word lines (WLr1 to WLr4) are disconnected or not, the redundant memory cells Mr1 to Mr4 can be programmed.

As described above, in the present invention, since each of the redundant memory cells Mr1 to Mr4 is formed by one transistor, the area of the redundant memory cell can be reduced, and the circuit for programming can be reduced. Since the circuit (corresponding to the write circuit 3 and the selection circuit 4 of the conventional example) is unnecessary, the occupied area of the redundant circuit including the redundant cell array can be reduced. Moreover, the program work is extremely simple as compared with the conventional example.

2 (a) and 2 (b) are a plan view and a sectional view of a main part showing the structure of the embodiment shown in FIG. 1, respectively.

The connection portion between the high resistances R11 to R14 and the redundant word lines WLr1 to WLr4 in this embodiment is formed on the substrate 21 on which a plurality of memory cells and redundant memory cells are formed.
Multiple redundant word lines 26 (corresponding to WLr1 to WLr4)
Is formed, an interlayer insulating film 27 is formed on the plurality of redundant word lines 26, one contact hole 28 is opened at a predetermined position of the interlayer insulating film 27, and the contact hole 28 and the interlayer insulating film 28 are formed. It has a structure in which a plurality of high resistances 29 (corresponding to R11 to R14) which are integrated and are respectively connected to the plurality of redundant word lines 26 are formed.

With such a structure, it is possible to avoid miniaturization of the contact hole, and it is possible to increase the alignment margin between the contact hole and the redundant word line, which has the advantage of facilitating manufacturing. .

Although the method of using the laser as the cutting means has been described in the above-mentioned embodiments, the time required for programming can be further increased by using the method of removing the interlayer insulating film, the word line and the redundant word line at the cut portion by etching. It can be shortened.

[0025]

As described above, according to the present invention, the redundant cell array has a vertically stacked structure like the memory cell array, the redundant word line is connected to the power supply potential point through the high resistance, and the word line and the redundant word line are connected. Since the redundant memory cell is composed of a single transistor and the conventional write circuit and selection circuit are not required, the redundant circuit is occupied by connecting the same and disconnecting the connected portion according to the cell data during programming. There is an effect that the area can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

2A and 2B are a plan layout view and a cross-sectional view of a main part showing the structure of the embodiment shown in FIG.

FIG. 3 is a circuit diagram showing an example of a conventional semiconductor device.

[Explanation of symbols]

1, 1a, 1b memory cell array 2, 2a, 2b redundant cell array 3 write circuit 4 selection circuit 41, 42 write voltage generation circuit BL1 to BL3 bit line BLr1, BLr2 redundant bit line F1 fuse M1 to M4 memory cell MB memory block Mr1 to Mr4, Mr1x, Mr2x redundant memory cells Q1, Q2 transistors R11 to R14, R21 to R24 high resistance WL1 to WL4 word lines

Claims (2)

(57) [Claims] 1. A plurality of bit lines and a first transistor which is turned on when a first signal supplied to a gate is at a non-selection level and is turned on or off according to an internal storage state at a selection level. A plurality of memory cells connected in series and provided between the bit lines and a reference potential point respectively, and a plurality of memory cell blocks corresponding to the gates of the transistors of the memory cell blocks. A memory cell array having a plurality of word lines for supplying one signal; a plurality of high resistances provided corresponding to the plurality of word lines, respectively, to one end of which a power supply potential is supplied; redundant bit lines; It is provided corresponding to each memory cell of the cell block, and is turned on when the second signal supplied to the gate is at the first level and turned off when it is at the second level. A plurality of redundant memory cells formed of a second transistor and connected in series between the redundant bit line and the reference potential point, and a plurality of redundant memory cells are provided corresponding to each of the plurality of redundant memory cells, and one end corresponds to the redundant memory cells. The second level and the non-selection level are connected to the other end of the high resistance, and the other end is connected to the corresponding word line in a disconnectable state by a predetermined disconnecting means. And a redundant cell array having a plurality of redundant word lines that become the first level regardless of the level of the word line when the disconnection means does not connect. A semiconductor device characterized by: 2. A plurality of redundant word lines are formed on a substrate on which a plurality of memory cells and redundant memory cells are formed, an interlayer insulating film is formed on the plurality of redundant word lines, and a predetermined amount of the interlayer insulating film is formed. 2. A contact hole is formed at a position, and a plurality of high resistances are formed on the contact hole and the interlayer insulating film, which are integrated with each other and are respectively connected to the redundant word lines. The semiconductor device described.