JP2682463B2 - Logarithmic amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logarithmic amplifier circuit,
In particular, the present invention relates to a logarithmic amplifier circuit formed on a semiconductor integrated circuit and capable of low voltage operation.

[0002]

2. Description of the Related Art A logarithmic amplifier circuit is a circuit for compressing a dynamic range of an input signal. As one of the logarithmic amplifier circuits, a plurality of amplifiers having a limiter characteristic and a plurality of amplifiers having a gain of 1 which are not saturated are connected in cascade, and the output of the amplifier having the limiter characteristic of each stage is attenuated by an attenuator. After that, the output of the corresponding stage having the gain of 1 is combined with the output of the amplifier described in JP-A-3-12750.
No. 4 discloses this.

A logarithmic amplifier circuit in which amplifiers having different gains are switched according to an input voltage when a logarithmic characteristic is approximated by a broken line using a plurality of amplifiers is disclosed in JP-A-2-141012. Have been.

Further, a logarithmic amplifier circuit in which output signals of the respective stages of the cascaded amplifiers are detected by a rectifier, and the sum of the respective detection currents is input to the emitter of a transistor whose base is grounded to add detection currents. Was published in
It is disclosed in JP-A-2-1100010.

A logarithmic amplifier circuit in which the dynamic range is widened by setting the emitter size of the transistor used in the rectifier of the logarithmic amplifier circuit and the gate width and the gate length of the MOS transistor in a specific relationship is disclosed in Japanese Patent Laid-Open No. 3-228412. No. 6,086,045. In addition, JP-A-62-293807 and JP-A-62-293807
Japanese Patent Application Laid-Open No. 292010 and Japanese Patent Application Laid-Open No. 4-165805 disclose a logarithmic amplifier circuit. These cross-connect the inputs of two unbalanced differential pairs having different emitter area ratios or gate width to gate length ratios, and connect the outputs in parallel to form a double-wave rectifier. . The construction method of such a rectifier is based on IEEE Tra.
nsaction on Circuits and
Systems-I, VOL. 39, NO. 7th of 9
From page 71 to page 777 (issued September 1992)
Are also disclosed in detail.

[0006]

Problems to be Solved by the Invention
In the logarithmic amplifier disclosed in Japanese Patent Application Laid-Open No. 4 (1999) -1999, the amplification gain has a logarithmic characteristic by saturating an amplifier cascaded in multiple stages from a subsequent stage with an increase in input voltage. In this logarithmic amplifier, the logarithmic characteristic can be approximated by a broken line, but unless the number of stages of the amplifier is increased, an approximation error from the actual logarithmic characteristic increases. For this reason, there has been a problem that the circuit becomes large in order to obtain an accurate logarithmic amplifier. This is a problem that also occurs in the logarithmic amplifier circuit disclosed in Japanese Patent Application Laid-Open No. Hei 2-141012 in which amplifiers having different gains are switched and used.

On the other hand, like the logarithmic amplifier circuit disclosed in Japanese Patent Laid-Open No. 62-100010, the output of the amplifier at each stage is detected by a rectifier having a characteristic that approximates the logarithmic characteristic. The error due to the polygonal line approximation can be reduced. However, since the dynamic range of the rectifier is narrow, in order to obtain a logarithmic amplification circuit with a wide dynamic range, the number of stages of cascaded differential amplifiers must be increased and the dynamic range must be finely divided. There was a problem that many differential amplifiers were needed. JP-A-3-228
In Japanese Patent No. 412, a half-wave rectifier using an unbalanced differential pair in which the ratio of the emitter area of a transistor or the ratio of the gate width to the gate length is different, and the inputs of two unbalanced differential pairs are cross-connected to each other. The operating range of the rectifier is expanded by using a double-wave rectifier with the outputs connected in parallel. However, since the dynamic range of the rectifier is still insufficient compared with the dynamic range of the differential amplifier, there is a problem that a large number of rectifiers are required to obtain a logarithmic amplification circuit with a wide dynamic range.

It is therefore an object of the present invention to obtain a logarithmic amplifier circuit which is excellent in logarithmic accuracy and temperature stability and which can obtain a wide dynamic range with a small number of rectifiers and which can operate at low voltage.

[0009]

According to a first aspect of the present invention, a plurality of differential amplifiers having a limiting characteristic and connected in cascade are provided, and a rectifier for detecting an input signal or an output signal of each of the differential amplifiers. And a current generating means for generating a current equal to the collector current or drain current of one of the transistors forming the differential pair ,
The collector current or drain of one of the transistors described above
An adder that adds a current equal to the in-current and a predetermined constant current
A plurality of rectifiers each having a stage and constituted by a differential circuit driven by a current of the added value of the adding means, and an adder for adding all the detected rectified currents output from these rectifiers,
A logarithmic amplifier circuit is provided with a diode-connected transistor that inputs the output of this adder.

That is, according to the first aspect of the invention, the differential pair to which the dynamic bias technique is applied is used to give the rectifier exponential characteristic or square characteristic,
The output current of the rectifier is logarithmically compressed or route compressed by a diode-connected transistor.
As a result, the dynamic range of the rectifier can be expanded.

According to a second aspect of the present invention, a plurality of differential amplifiers having limiting characteristics and cascaded in multiple stages,
A rectifier for double-wave rectifying an input signal or an output signal of each of these differential amplifiers, and a current generating means for generating a current equal to a collector current or a drain current of one of the transistors forming the differential pair, and One
Equal to the collector or drain current of the transistor
There and an adding means for adding the current and predetermined constant current, pressurized
A plurality of rectifiers in which the inputs of two half-wave rectifiers configured by a differential circuit driven by the current of the added value of the calculating means are cross-connected to each other, and all the detected rectified currents output from these rectifiers are added. And a diode-connected transistor for inputting the output of the adder are provided in the logarithmic amplifier circuit.

That is, in the second aspect of the present invention, the double-wave rectifier is constructed by cross-connecting the inputs of the two half-wave rectifiers to which the dynamic bias technique is applied. As a result, a logarithmic amplifier circuit with a wide dynamic range that can rectify both waves of the input voltage is realized with a small number of rectifiers.

According to the third aspect of the invention, the transistor diode-connected to the outputs of the rectifier and the adder is a bipolar transistor. As a result, the rectifier has an exponential characteristic, and its output is logarithmically compressed by the diode-connected transistor. Since the exponent and the logarithm have an inverse functional relationship, the slope of the exponential characteristic can be made gentle and the dynamic range of the rectifier can be widened.

According to a fourth aspect of the present invention, a transistor which is diode-connected to the outputs of the rectifier and the adder is MO.
It is an S transistor. As a result, the rectifier has a squared characteristic, and its output is route-compressed by the diode-connected transistor. Since the square and the square root have an inverse functional relationship, the slope of the square characteristic can be made gentle and the dynamic range of the rectifier can be widened.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows the logarithmic increase in one embodiment of the present invention.
It is a diagram showing an outline of the circuit configuration of the width circuit. This pair
The number amplification circuit is a plurality of differential amplifiers connected in cascade.
11 ₁~ 11_NAnd the input and
Rectifiers 12 connected to the output terminals of the final stage₁~ 12
_{N +1}And an adder 13 for adding the output currents of these rectifiers
And a diode connected to input the output current of the adder
It is composed of a transistor 14. Differential amplifier 1
1₁~ 11_NEach have limiting characteristics
As the input voltage of the logarithmic amplifier circuit increases,
The differential amplifiers in the subsequent stages are saturated sequentially.
Each rectifier is different from the input voltage range of the differential amplifier.
Are each in charge of the range
To get sex. The adder is the output of these rectifiers.
Force-current-added and diode-connected transistor 1
4 is the logarithmic compression or the root compression of the output of the adder
It has become.

FIG. 2 shows an outline of the circuit configuration of the rectifier shown in FIG. In this rectifier, the transistor 21 and the transistor 22 form a differential pair. Then, the differential circuit is driven by the sum of the constant current I _O obtained by the constant current source 23 and the collector current of the one transistor 21 forming the differential pair. First, the characteristics of a rectifier using a bipolar transistor will be described.

The relationship between the collector current and the base-emitter voltage of the bipolar transistor is expressed by the following equation, if the power law is followed.

(Equation 1) Here, _IS is the saturation current, _VT is the thermal voltage, and _VT =
It is expressed as q / kT. Where q is the unit electron charge, k
Is the Boltzmann constant, and T is the absolute temperature. In a transistor having a base-emitter voltage V _{BEi of} about 600 mV, the exponent exp (V _BEi / V _T ) has a value of about the 10th power during normal operation, and −1 in the equation (1) can be ignored. At this time, the differential output current of the bipolar differential pair driven by the tail current I _EE shown in FIG. 2 is expressed by the following equation, assuming that the matching between the elements is good.

(Equation 2) Where α _F is the direct current amplification factor of the transistor,
In a normal process, the value is 0.98 to 0.99,
Here, α _F = 1.

In addition,

(Equation 3) Since they are expressed as follows, by substituting these into the equation (1) to obtain I _C1 ,

(Equation 4)Becomes Compared with equation (1), this is the base-em
Unit voltage V_BEiIs V _iAnd the saturation current I_STo I₀Put on
It has been replaced. Saturation current I_SIs a transistor
It fluctuates due to the variation of₀Is controlled by a constant current source
It can be set at will. Therefore, I_C1Is electric
Represented by programmable parameters
Realizes an exponential circuit with high accuracy for differential input voltage
Can be

FIG. 3 shows the relationship between the input voltage and the collector current in the rectifier shown in FIG. The vertical axis represents the collector current I _C1 and the horizontal axis represents the input voltage (V _i / V _T ). In this way, one collector current of the differential pair to which the dynamic bias current technique is applied has an exponential characteristic.

FIG. 4 is a logarithmic representation of the relationship between the output voltage and the input voltage of the rectifier shown in FIG. The operating input voltage range of the bipolar rectifier using the differential pair to which the dynamic bias current technology is applied is very wide, and the transistor in the circuit is saturated by internal resistance.
However, since the exponential characteristic and the logarithmic characteristic have mutually inverse functional relationships, as it is, the logarithmic input dynamic range can be utilized only at 10 dB (decibel) or less as shown in FIG. If an emitter resistor is inserted in the transistor and emitter degeneration is applied, the exponential characteristic of the rectifier can be rounded, the slope can be made gentle, and the logarithmic input dynamic range can be widened. However, if the emitter resistance is inserted, the power supply voltage must be increased correspondingly, which is unsuitable for low voltage operation.
On the other hand, if the output current of the rectifier is logarithmically compressed via the diode, it is possible to utilize up to the logarithmic input dynamic range corresponding to the gain of the differential amplifier.
The output voltage when the output current of the rectifier is output via the diode-connected transistor is logarithmically compressed from the relationship of the equation (1). Therefore, it can be regarded as an approximately linear rectifier until the differential amplifier is saturated and becomes a limiter. Therefore, the logarithmic amplifier circuit can be configured by using the rectifier shown in FIG. 2 as the rectifier of the circuit shown in FIG.

Since the differential amplifiers 11 _{1 to} 11 _N each have a limiting characteristic, the current after adding the output currents of all the rectifiers 12 _{1 to} 12 _{N +1} by the adder 13 to the diode 14 Similar results can be obtained by logarithmic compression via. In the logarithmic amplifier circuit shown in FIG. 1, logarithmic compression is performed after addition.

FIG. 5 shows the relationship between the input voltage of the logarithmic amplifier shown in FIG. 1 and the output current of each rectifier and adder. The differential amplifier 11 ₁ shown in FIG.
Since ~ 11 _N are cascade-connected, the differential amplifier 11 _{N at the} final stage is sequentially saturated with an increase in the input voltage. For example, if the input voltage range of 80 dB is divided into 10, the logarithmic characteristic is obtained by using the rectifier 12 _{N +1} connected to the output terminal of the differential amplifier 11 _{N at} the final stage for the first 10 dB. It has become. The limiting characteristic of the differential amplifier 11 _{N at the} final stage is set so as to be saturated when the input voltage becomes 10 dB or more. As a result, as indicated by the characteristic curve 41, even if the input voltage further increases, the output current of the rectifier 12 _{N +1} does not increase beyond a certain value. For the input voltage range of 10 dB to 20 dB, the logarithmic characteristic is obtained by using the second rectifier 12 _N from the final stage. When the input voltage exceeds 20 dB, the differential amplifier 11 _{N -1} from the final stage to the second stage is saturated, and the output current of the rectifier does not increase even if the input voltage becomes higher. The characteristic curve 42 represents the output current characteristic of the rectifier 12 _N. In this way, the input voltage range of each rectifier is divided for each 10 dB,
By taking the sum of these output currents, it is possible to realize a logarithmic amplifier circuit having a wide dynamic range as shown by the characteristic curve 45.

Next, a rectifier using MOS transistors will be described.

FIG. 6 shows a circuit configuration when the rectifier of the logarithmic amplifier circuit shown in FIG. 1 is configured by using MOS transistors. This is a modification of each transistor of the rectifier shown in FIG. 2 from bipolar type to MOS type. The input / output characteristics of this rectifier will be described.

The drain current of the MOS transistor operating in the saturation region can be expressed by the following equation, ignoring the channel length modulation and the substrate effect.

(Equation 5) Here, β = μ (C _OX / 2) (W / L) is a transconductance parameter. μ represents the carrier's effective mobility, C _OX represents the gate oxide film capacitance per unit area, and W and L represent the gate width and the gate length, respectively. V _TH is the threshold voltage, V
_GSi represents the gate-source voltage.

The differential output current of the MOS differential pair driven by the tail current I _SS is assumed to have good matching between elements, the substrate effect is ignored, and the drain current of the MOS transistor operating in the saturation region is ignored. If the relationship between the gate-source voltage and the gate-source voltage follows the square law shown in the equation (6), it is expressed by the following equation.

(Equation 6) Here, the relation of each current is expressed by the following equation.

(Equation 7) Therefore, when I _D1 is obtained by substituting the equations (6) and (7), the following is obtained.

(Equation 8)

FIG. 7 shows the relationship between the input voltage and the drain current of the rectifier shown in FIG. Also from this figure, it can be seen that the drain current of one of the differential pairs to which the dynamic bias current technique is applied has a square characteristic. Comparing the relationship between the gate voltage and the drain voltage of the MOS transistor expressed by the equations (6) and (7) with the equations (11) and (12), the gate-source voltage V _GSi is different. The dynamic input voltage V _i and the threshold voltage V _TH correspond to SQR (I ₀ / β), respectively.
Here, SQR indicates a route. Thus, the drain current is all represented by only electrically programmable parameters.

FIG. 8 is a logarithmic representation of the output current characteristic of a rectifier using MOS transistors. The operating input voltage range of the rectifier using the differential pair applying the dynamic bias current technology is very wide. It has a range until the transistor in the circuit is saturated by internal resistance or the like. However, since the square characteristic and the logarithmic characteristic are originally in the opposite functional relationship, if the rectifier is used as it is, the dynamic range that can be used as the logarithmic input is only about 10 dB. Therefore,
The dynamic range can be widened by root-compressing the output current of the rectifier. That is, the output current of the rectifier is diode-connected to the MOS transistor and the route is compressed, whereby the dynamic range as a logarithmic input can be expanded to a range corresponding to the gain of the differential amplifier. The output voltage output via the diode-connected transistor is route-compressed by the equation (6), and can be regarded as an approximately linear rectifier until the differential amplifier saturates and becomes a limiter. Therefore, by using the rectifier of the logarithmic amplifier circuit shown in FIG. 1 as shown in FIG. 6, it is possible to realize a logarithmic amplifier circuit having a wide dynamic range with a small number of rectifiers.

The rectifying characteristics of the rectifier described so far are half-wave rectifiers. A double-wave rectifier can be obtained by using two of these half-wave rectifiers, connecting their inputs to each other and connecting them, and adding their outputs.

FIG. 9 shows a circuit configuration of a double-wave rectifier using bipolar transistors. The transistors 51 and 52 constitute one half-wave rectifier. The transistors 53 and 54 form the other half-wave rectifier. The positive and negative of the input voltage V _i are reversed, and the transistor 51 of each half-wave rectifier is
To 54 bases. Then, by commonly connecting the collectors of the transistors 52 and 53, the output currents of the respective half-wave rectifiers are added.

FIG. 10 shows a circuit configuration of a double-wave rectifier using CMOS transistors. The transistors 61 and 62 form one half-wave rectification circuit, and the transistors 63 and 64 form the other half-wave rectification circuit. The input voltage V _i is input to each half-wave rectifier so that its positive and negative polarities are reversed. The drains of the transistor 62 and the transistor 63 are commonly connected, so that the output currents of the half-wave rectifiers are added.

[0033]

As described above, according to the first aspect of the invention, since the rectifier having a wide operating input voltage is used, the logarithmic amplifier circuit can be composed of a small number of rectifiers. Also, by using a rectifier that uses a differential pair to which the dynamic bias current technology is applied, the logarithmic accuracy and the stability of temperature characteristics are excellent, and since no emitter resistor is inserted, it is possible to operate at a low voltage. it can. Therefore, it is possible to easily form a logarithmic amplifier circuit in a semiconductor integrated circuit driven at a low voltage.

According to the second aspect of the present invention, by using two half-wave rectifiers utilizing the dynamic bias current technique, a double-wave rectifier having a wide operating input voltage range can be obtained. As a result, it is possible to configure a logarithmic amplifier circuit that can obtain an output voltage that is double-wave rectified with a small number of rectifiers.

Further, according to the third aspect of the invention, the rectifier is constructed by using the bipolar transistor, and the bipolar transistor is used as the diode-connected transistor. Thus, the exponential characteristic of the rectifier can be logarithmically compressed by the diode-connected transistor, so that a rectifier with a wide dynamic range can be obtained.

According to the invention of claim 4, a MOS is provided.
A rectifier is formed by using a transistor, and a MOS transistor is used as a diode-connected transistor. As a result, the square characteristic of the rectifier can be route-compressed by the diode-connected transistor, so that a rectifier with a wide dynamic range can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an outline of a circuit configuration of a logarithmic amplifier circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an outline of a circuit configuration of a rectifier using a bipolar transistor.

FIG. 3 is a characteristic diagram showing input / output characteristics of a rectifier using the bipolar transistor shown in FIG.

FIG. 4 is a characteristic diagram showing the input / output characteristics of the rectifier shown in FIG. 3 in logarithmic form.

5 is a characteristic diagram showing input / output characteristics of the logarithmic amplifier circuit shown in FIG.

FIG. 6 is a circuit diagram showing a circuit configuration of a rectifier using CMOS transistors.

7 is a characteristic diagram showing an input / output characteristic of a rectifier using the CMOS transistor shown in FIG.

8 is a characteristic diagram showing the input / output characteristics of the rectifier shown in FIG. 6 in logarithmic form.

FIG. 9 is a circuit diagram showing a circuit configuration of a double-wave rectifier configured by using two half-wave rectifiers using bipolar transistors.

FIG. 10 is a circuit diagram showing a circuit configuration of a double-wave rectifier configured by using two half-wave rectifiers using CMOS transistors.

[Explanation of symbols]

11 _{1 to} 11 _N differential amplifier circuit 12 _{1 to} 12 _{N +1} rectifier 13 adder 14 diode-connected transistor 21, 22, 51-54 bipolar transistor 23 constant current source 61-64 MOS transistor

Claims (4)

(57) [Claims] 1. A plurality of differential amplifiers having a limiting characteristic, which are cascade-connected in multiple stages, and a rectifier that detects an input signal or an output signal of each of the differential amplifiers, one of which constitutes a differential pair. Current generating means for generating a current equal to the collector current or drain current of the transistor, and the one transistor
A current equal to the collector current or drain current of the star and an addition means for adding a predetermined constant current.
A plurality of rectifiers composed of differential circuits driven by the current of the added value of the stages, an adder that adds all the detected rectified currents output from these rectifiers, and a diode that inputs the output of this adder A logarithmic amplifier circuit comprising a connected transistor . 2. A plurality of differential amplifiers having a limiting characteristic, which are cascade-connected in multiple stages, and a rectifier for rectifying both input signals or output signals of the differential amplifiers, respectively, which constitutes a differential pair. A current generating means for generating a current equal to the collector current or the drain current of one of the transistors;
Current equal to the collector or drain current of the transistor.
Current and a predetermined constant current are added to the addition means.
A plurality of rectifiers having inputs of two half-wave rectifiers, which are constituted by a differential circuit driven by the current of the added value of the calculation means, are cross-connected to each other, and all the detected rectified currents output from these rectifiers are added. And a diode-connected transistor for inputting the output of the adder . 3. A logarithmic amplifier circuit according to claim 1, wherein the rectifier transistor and the diode-connected transistor are bipolar transistors. 4. The logarithmic amplifier circuit according to claim 1, wherein the rectifier transistor and the diode-connected transistor are MOS transistors.