JP2682381B2 - Parallel address generator using 3D digital differential analyzer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention
The present invention relates to an image processing method for continuously obtaining in parallel three-dimensional DDA converted data from a frame memory.

[0002]

2. Description of the Related Art In moving image processing, as an image processing method for continuously obtaining in parallel three-dimensional DDA-converted data from a frame memory, for example, a ray tracing method of three-dimensional voxel data shown in the following documents is cited. To be

[1] A. Fujimoto, T .; Tan
aka, K .; Iwata, "ARTS: Acceler"
ated Ray-Tracing System ”,
IEEE Computer Graphics &
Application, 6, 4, pp. 16-26
(April 1986) [2] Zhang, So, Aoki, "High-speed voxel tracking algorithm for ray tracing based on LCDDA method and its hardware", IEEJ (DII), J74-D-II, 6, pp. 7
08-717 (1991) [3] Tayama, Shimizu, Chiba, Otawara, "Voxel tracking method for generating cut-out stereoscopic images at high speed", Theoretical theory (DII),
J72-D-II, 9, pp. 1332-1340 (19
89) [1] is a method for realizing a three-dimensional DDA (hereinafter, 3D-DDA) by two-dimensional two-dimensional DDA (hereinafter, 2D-DDA) orthogonal to each other. Further, [2]-[3] is a high-speed ray tracking algorithm which does not cause 3D-DDA in the voxel space.

[0004]

However, in the prior art, when it is applied to a multiprocessor method to realize a real-time operation, a multistage switch is provided between memory processors or a high speed bus is provided to prevent data collision. It is necessary to make special efforts to use a protocol that does not occur as much as possible.

An object of the present invention is to perform ray tracing in an arbitrary direction continuously so as not to miss the 3D memory when reading data from the 3D voxel memory in order to realize real-time volume rendering. And to provide a three-dimensional DDA image processing method for parallel data processing.

[0006]

Means for Solving the Invention

1.2 First 2D-DD to calculate D-DDA address
The A address generating circuit and the axis perpendicular to the two-dimensional plane which is the calculation area of the first 2D-DDA address generating circuit and passes through the 2D-DDA address point coordinates calculated by the first 2D-DDA address generating circuit. A first three-dimensional memory having a configuration capable of writing or reading data on a straight line in a three-dimensional space along a single read cycle or several read cycles, and a linear shape similar to the first three-dimensional memory In order to read the data read from the first three-dimensional memory in a two-set configuration in which two units each have a same size as the first three-dimensional memory in which data can be written and read and which can operate as a double buffer. Double-buffer the data read linearly from the connected second three-dimensional memory and the first three-dimensional memory to the second three-dimensional memory. And three data buses that are writable and readable with and transfer the data that are read out linearly from the second three-dimensional memory, and calculate two-dimensional addresses for each set of the second three-dimensional memory. One second total of 2D-DDA address generation circuits and a linear data string read by the pipeline from the second three-dimensional memory in each read cycle. A plurality of processor modules each including an address generating circuit for individually selecting a general purpose processor and a general-purpose processor for performing data processing on the selected data, all of which are connected in parallel to the data bus to simultaneously read data from the data bus. 2D-DDA consisting of multi-processor modules that can operate simultaneously in parallel
3D-DDA with pipeline configuration by two-stage cascade connection
Is calculated in parallel.

2.2 first 2D-DDA address generation circuits for calculating a 2D-DDA address, and 2D-DDA calculated by the first 2D-DDA address generation circuit
The three-dimensional spatial data along the axis perpendicular to the two-dimensional plane which is the calculation area of the first 2D-DDA address generation circuit passing through the address point coordinates is written and read in parallel in a single read cycle or several read cycles. In the configuration, each is connected to the two first 2D-DDA address generation circuits, and data is preliminarily obtained from a three-dimensional data called an Octree division method or a voxel division method from a place where the data exists from the whole three-dimensional data. When the extracted data is continuously input by the extracting algorithm, a first three-dimensional memory composed of two sets for enabling double buffer operation, and the first three-dimensional memory Similarly, it is composed of two units of the same size as the first three-dimensional memory capable of linearly writing and reading data and has a double buffer. A second three-dimensional memory connected to read the data read from the first three-dimensional memory in a two-set configuration to enable operation, and data read linearly from the first three-dimensional memory Three data buses that can be written to and read from the second three-dimensional memory by a double buffer operation, and transfer data that is read linearly from the second three-dimensional memory;
2D-DDA address generating circuits for calculating 2D-DDA addresses for each set of 3D memory, and a pipeline read from the second 3D memory for each read cycle. A plurality of processor modules each having a built-in address generating circuit for individually selecting data from the data column and a general-purpose processor for processing the selected data, A multiprocessor module that is connected to a data bus in parallel and simultaneously reads data from the data bus and can operate in parallel at the same time is configured to calculate 3D-DDA in parallel by a pipeline configuration with two-stage cascade connection of 2D-DDA. Characterize.

[0008]

Operation: An address generation circuit (1
The data is linearly read from the three-dimensional memory (31) by the address of 1) and written into the second-stage three-dimensional memory (32) and (33) or (34) and (35) having the double buffer configuration, 2 Two-dimensional 2D DDA generation circuit 1
The address given by 2 or 13 to the three-dimensional memory (32) and (34 or (35) and (36))
Similar to the dimensional memory (31), data is read out linearly and transferred to the data bus (43), and multiplexers (61) to (63) connected to the data bus 43 respectively follow address generating circuits (13) to (15), respectively. By fetching the data in the calculation area that it is in charge of and processing it by the processors (70) to (72), respectively, 3
Process the dimension DDA in parallel.

[0009]

Next, the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.

The image memory device of this embodiment, as shown in FIG. 1, is a 3D-to-arbitrary direction vector h = (A, B, C).
In realizing DDA, the address generation circuit 11 is XY
2D-DDA as described later is calculated in the hxy = (A, B, 0) direction corresponding to the plane.

The calculated address data is transferred to the three-dimensional memory 31 through the address bus 21. The three-dimensional memory 31 linearly writes and reads data along the axis passing through the XY plane address coordinates of the address bus 21 and perpendicular to the XY plane in a single read cycle or several read cycles.

Since the data linearly read from the three-dimensional memory 11 has a double buffer structure, when the demultiplexer 51 provided selects the data bus 41 which can linearly transfer data on the output side, Dimensional memory 32
And the read data from the three-dimensional memory 31 is transferred to the three-dimensional memory 33.

When the demultiplexer 51 selects the data bus 42 capable of linear data transfer on the output side, the above-mentioned 3
The linear data read from the three-dimensional memory 31 is transferred to the three-dimensional memory 34 and the three-dimensional memory 35 having the same shape as the three-dimensional memory 31.

Next, when the output side of the demultiplexer 51 is selecting the data bus 42, the address generating circuit 12 this time causes the direction vector hyz = (0,
The address signal calculated by the address generation circuit 12 by executing the 2D-DDA along (B, C) passes through the address bus 22 and the three-dimensional memory 32 having the same shape as the three-dimensional memory 31.
And the linear data along the axis perpendicular to the transmitted address in the YZ plane are linearly read from the three-dimensional memory 32 and the three-dimensional memory 33.
The output data of the three-dimensional memory 33 is the data bus 4 as it is.
3 is output. The output data of the three-dimensional memory 32 is output to the data bus 41, and when the output of the demultiplexer 60 selects the data bus 42, the multiplexer 60 selects the data bus 41 on the input side and outputs the three-dimensional memory 32. The data is output to the data bus 43.

When the demultiplexer 51 selects the data bus 41, the address generation circuit 13 executes 2D-DDA in the hyz = (0, B, C) direction as described above, and the address generation circuit 13 is executed. Of the address signal from the three-dimensional memory 34 and the three-dimensional memory 35 is read out from the three-dimensional memory 34 and the data of the three-dimensional memory 34 is output to the data bus 43 as it is, and the multiplexer 60 selects the data bus 42 on the input side. The data of the three-dimensional memory 35 is also output to the data bus 43.

The data bus 43 is used for the address generation circuit 13.
And the address bus 23, the multiplexer 61 and the processor 70. In the processor module, the address generation circuit 13 pre-calculates the ray in charge of its own processor module and outputs it to the address bus 23.

The multiplexer 61 selects the data corresponding to the address bus 23 from the data bus 43 and reads it into the processor 70. The processor 70 processes the data read as described above and outputs the result to the output data bus 44. All of the processor modules have the same structure, and a plurality of processors are connected to the input to the data bus 43 and the output to the data bus 44.

According to the present invention, as described above, 2D-DDA is executed two times in a dependent manner, and each processor module determines the coordinate of the ray it is in charge of with respect to the linear data string read by the pipeline. Read processing.

The 2D-DDA used in this method is described in [3] Tayama, Shimizu, Chiba, Otawara, “Voxel tracking method for generating cut-out stereoscopic image at high speed”, Theoretical theory (DII),
J72-D-II, 9, pp. 1332-1340 (19
89) The method introduced in 89) is expanded and improved as follows so that it can be applied to this method.

However, since I and II have two memories for writing data as described later, they are used as descriptors for distinguishing them.

[Procedure 1] (1) When the traveling direction vector of a ray is (x1, y1), the larger direction of x1 and y1 is determined as the reference direction.

(2) The increment width in the reference direction is set to 1, and the increment x1 / y1 in the other direction (when x1≤y1) or y1
Calculate / x1 (when y1 <x1).

(3) The address of the initial pixel is output from the integer part of the viewpoint coordinates of the line segment.

(4) Advance 2D-DDA one step (reference direction +
1, non-reference direction + inclination increment) and generate the address of the next pixel candidate from the integer part at that coordinate.

If it is outside the target tracking area, the process ends. When it is inside (i) When both the integer parts of the coordinates in the two directions are incremented by 1,
Before the generated pixel candidate, it is possible that another pixel was passed, and the following is executed. Otherwise (i
Go to i).

If the minority part of the coordinates in the non-reference direction is not (a) 0, it is determined that the pixel at the address with the integer part of the coordinates in the reference direction being -1 is passed before passing through the pixel candidate, and The address (integer part-1) is output to I. It is determined that only the generated pixel candidate passes next, and the address is output to II.

(B) If 0, it is determined that another voxel has not been passed and the address of the pixel candidate is output to I.

Return to (c) (4).

(Ii) It is determined that only the generated pixel candidate passes next, and the address is output to II. Return to (4).

In FIG. 2 , the larger component of the direction vector of the straight line is the reference direction (Driving axis in FIG. 2 ).
s), at least one pixel row is generated in the reference direction (■ in FIG. 2 ), but the non-reference direction (same Pass)
One or two are lined up on the ive axis) (the same as ●).

As for I and II in [Procedure 1], one and two cases occur in the non-reference direction in FIG. 3, but in the case of two cases, priority is given to the non-reference direction as shown in FIG. When outputting in order (as the ray passes in the order of → → ● for the non-reference direction in Fig. 2, the order of ■ and ●), ■ is I, ● is
It corresponds to II.

The parallel 3D-DDA algorithm used in this method is the following [Procedure 2].

[Procedure 2] (1) Execute [Procedure 1] on the XY plane, and obtain the result as I.
Write to memory and II memory.

(2) Execute (a) [Procedure 1] for both the I memory and the II memory on the YZ plane. If all the components have been executed on the YZ plane, the processing is finished. (B) For each of the data read in (a), each processor module takes out the ray data for which it is in charge and performs rendering processing (c) (a).

FIG. 3 is a diagram showing an outline of [Procedure 2]. Any direction vector h in FIG. 3 = (A, B, C )
And First, 2D-DDA of [Procedure 1] is executed in the (A, B) direction on the XY plane (A, B).
B, t) (0 ≦ t ≦ L−1) (L is the length of one side of the three-dimensional cube) data on a straight line is fetched in one read cycle or divided into several blocks and several read cycles are taken. , From memory i to memory I and memory II.

Next, in the YZ plane of [Procedure 1] (B, C)
Similarly, 2D-DDA is executed for the direction and the memory I
Then, the linear data of (t, B, C) (0≤t≤L-1) is fetched from the memory II in one read cycle or several read cycles.

At this time, when paying attention to one ray, four or less pieces of cube data in the non-reference direction are generated in two executions, but the 2D-DDA of [Procedure 1] does not cause the cube data to be lost. You can take it out in the order that Ray passes. Lastly, the multiprocessor module fetches the ray for which each processor module is responsible for the calculation from the linearly pipeline read data according to the address previously calculated by the address generating circuit.

As described above, pipeline reading of arbitrary coordinate data can be realized from the three-dimensional frame memory,
The present invention can be implemented.

FIG. 4 shows an embodiment of the second invention. As shown in FIG. 4, the image memory device of the present embodiment realizes 3D-DDA to arbitrary direction vector h = (A, B, C) in advance from the whole three-dimensional data by the Octree division method or voxel division. It is assumed that the extracted data is continuously input from the data bus 40 by an algorithm called a method for extracting data from a place where the data exists from three-dimensional data.

The data from the data bus 40 is written to two three-dimensional memories, that is, the three-dimensional memory 30 and the three-dimensional memory 31 which operate in a double buffer, and when one is full, the data is switched to the other and written. When the data is fully written in the three-dimensional memory 30, immediately after that, the address generation circuit 10 corresponds to the XY plane hxy = (A, B, 0).
Direction 2D-DDA is calculated, and the calculated address data passes through the address bus 20 and the three-dimensional memory 3
Transfer to 0.

The three-dimensional memory 30 linearly writes and reads data along the axis passing through the XY plane address coordinates of the address bus 21 and perpendicular to the XY plane in a single read cycle or several read cycles.

The data read out linearly from the three-dimensional memory 10 is a data bus 41 to which data on a line can be transferred.
Data is transferred to the three-dimensional memory 31 through the three-dimensional memory 32 and the three-dimensional memory 33.

Further, when the data is fully written in the three-dimensional memory 30 as in the above, the address generation circuit 13 then causes the direction vector hyz in the YZ plane to be hyz = (0, B, C).
2D-DDA is executed along the
The address signal calculated by the
The three-dimensional memory 34 having the same shape as that of the three-dimensional memory 30 and the three-dimensional memory 3 transmitted to the three-dimensional memory 35 and the linear data along the axis perpendicular to the transmitted address in the YZ plane are stored.
The data is read out linearly from the 4-dimensional and 3-dimensional memory 35 and the output data of the 3-dimensional memory 35 is directly output to the data bus 43.

The output data of the three-dimensional memory 34 is output to the data bus 42, the multiplexer 60 selects the data bus 42 on the input side, and as a result, the output data of the three-dimensional memory 34 is output to the output bus 43. Furthermore, three-dimensional memory 3
When the data to 1 is written to full, the corresponding address generating circuit 1 having the double buffer structure is formed.
0 to the address generating circuit 11, the address bus 20 to the address bus 21, the three-dimensional memory 30 to the same 31, the three-dimensional memory 32 to the same 34, the three-dimensional memory 33 to the same 35, and the data bus 41 to the data bus 42. Correspondingly, the same operation is alternately executed. The data bus 43 is the address generation circuit 1
3 to the address bus 23, the multiplexer 61, and the processor 70.

In the processor module, the address generation circuit 13 calculates in advance the ray in charge of its own processor module and outputs it to the address bus 23.

The multiplexer 61 selects the data corresponding to the address bus 23 from the data bus 43 and reads it into the processor 70. The processor 70 processes the data read as described above and outputs the result to the output data bus 44.

All of the processor modules have the same structure, and a plurality of processor modules inputs to the data bus 43 and outputs to the data bus 4.
4 is connected.

The operating principle of the second invention is the first.
It is the same as the invention of.

In the first and second inventions, the former realizes parallel 3D-DDA for fixed data, but the latter realizes parallel 3D-DDA even when data is continuously input.
Is the difference.

[0051]

For example, in the case of a 2563 three-dimensional memory area, the depth is half the average depth (256
It is assumed that ray tracing is performed up to / 2 = 128), each cube data (each voxel data) in the three-dimensional memory area is 1 byte, and slice data is 128 sheets, and one slice is interpolated.

When data is written and read from the three-dimensional memory at 20 MHz, the time required to read the three-dimensional data by executing 3D-DDA by a sequential method without considering parallelization is 50 [nsec] × 2.
It takes 562 × 128 = 419 [ms].

According to the present invention, the time required to read the result of 3D-DDA conversion from the entire three-dimensional memory area is 50 [ns.
ec] × 256 × 256 = 3.3 [ms], the parallelization speeds up 128 times, and 3D-DDA can be realized in real time.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the first invention.

FIG. 2 is a diagram showing an operation outline of the first invention.

FIG. 3 is a diagram showing an outline of operation of the first invention.

FIG. 4 is a diagram showing an embodiment of the second invention.

[Explanation of symbols]

 10-16 Address generation circuit 20-26 Address bus 30-35 Three-dimensional memory 40-44 Data bus 51 Demultiplexer 60-63 Multiplexer 70-72 Processor

Claims (2)

(57) [Claims] 1. A first two-dimensional DDA (digital differential analyzer) address generating circuit, a first three-dimensional memory, a second three-dimensional memory, three data buses, and a second two-dimensional DDA address generating circuit. And a multiprocessor module, wherein the first two-dimensional DDA address generation circuit is a two-dimensional DDA
A DA address is calculated, and the first three-dimensional memory writes or reads linear data in a three-dimensional space based on a read cycle, and the linear data is stored in a calculation area of the two-dimensional address generation circuit. Along a line perpendicular to a certain two-dimensional plane, passing through the two-dimensional DDA address calculated by the first two-dimensional DDA address generation circuit, and arranged in a straight line in a three-dimensional space, The three-dimensional memory is for performing the writing and reading of the linear data in the three-dimensional space continuously based on the read cycle, and is the same as the first three-dimensional memory for the two-dimensional memory. 2 as one set
A pair of memory pairs, the two pairs of memory pairs being connected to continuously read data from the first three-dimensional memory in the configuration of the two memory pairs, the three data buses being the first three-dimensional The linear two-dimensional data read from the memory is connected to the second three-dimensional memory so as to be continuously read, and the second two-dimensional DDA address generation circuit includes the second two-dimensional DDA address generation circuit.
For calculating a two-dimensional address in the three-dimensional memory of each of the second three-dimensional memories, the multi-processor module being provided in each of the three-dimensional memories of the second three-dimensional memory individually. A column of the linear data obtained from the second three-dimensional memory via the data bus is read based on a pipeline operation, and the second address generation circuit Data is individually selected from the column of data for the linear column of data read by the pipeline operation from the three-dimensional memory 2 for each read cycle, and the processor module is connected to the data bus in parallel. Connected to each other, performing parallel operation, performing data processing on the sequence of the data, and orthogonalizing the two-dimensional DDA to 2 A parallel address generator using a three-dimensional digital differential analyzer, which is connected in stages and calculates three-dimensional DDA in parallel by a pipeline structure. 2. Two first two-dimensional address generating circuits, a first three-dimensional memory, a second three-dimensional memory, three data buses, a second two-dimensional DDA address generating circuit, and a multiprocessor module. The first two-dimensional address generation circuit is provided with two units to calculate a two-dimensional DDA address, and the first three-dimensional memory is composed of two sets to store three-dimensional spatial data. Data is written and read in parallel, and the data extracted beforehand from the whole three-dimensional data using the Octree division method or the voxel division method (the algorithm that extracts the data from the location where the data exists in the three-dimensional data) the de performs a double buffer operation, each of the first two-dimensional address generating circuit is connected to output data to the second three-dimensional memory Is connected to data bus, the three-dimensional spatial data, through the 2-dimensional DDA address the first two-dimensional DDA address generator has calculated,
The first two-dimensional DDA is perpendicular to a two-dimensional plane which is a calculation area of the first two-dimensional DDA address generation circuit, and
The second three-dimensional memory is created along a straight line in a three-dimensional space by passing through the two-dimensional DDA address calculated by the address generation circuit, and the second three-dimensional memory has the same three-dimensional memory as the first three-dimensional memory. The first three-dimensional memory is provided with two sets of two memory pairs, which are connected so as to continuously read data from the first three-dimensional memory in the configuration of the two sets of memory pairs. Connected to the data bus for reading data read from the three data buses, the double buffer operation is performed, and the first three-dimensional memory and the second three-dimensional memory are provided on the bus. Writing and reading of the linear data on the memory are performed, and the second two-dimensional DDA address generating circuit
Two sets are provided for calculating a two-dimensional DDA address for each set of the three-dimensional memory, and the multiprocessor module includes the second address generation circuit, a plurality of processor modules, and a plurality of general-purpose processors. The data is read from the data bus at the same time, and the second address generation circuit reads data from the column of linear data with respect to the column of linear data read by the pipeline from the second three-dimensional memory in each read cycle. The processor module is configured to include a plurality of general-purpose processors, operate in parallel and at the same time, and are connected to the data bus in parallel. Data processing is performed on the data, and the two-dimensional DDA is orthogonally connected in a two-stage dependent manner. , The parallel address generator using a three-dimensional digital differential analyzer, characterized by parallel computation 3D DDA by pipeline configuration.